Line recognition module and display device

Abstract

A kind of line identification module, comprising: base (1), including line identification area (101) and the peripheral area (102) located in the periphery of line identification area (101);Photoelectric sensing structure (2) is located on base (1) and in line identification area (101), including: multiple grid lines (11a), multiple signal sensing lines (15) and multiple pixel units defined by multiple grid lines (11a) and multiple signal sensing lines (15);Wherein, pixel unit includes: thin film transistor (16), the gate electrode (11) of thin film transistor (16) is electrically connected with corresponding grid line (11a), the first electrode (13) of thin film transistor (16) is electrically connected with corresponding signal sensing line (15);Wherein, line identification area (101) includes: photosensitive area (A1), the pixel unit in photosensitive area (A1) further includes: photoelectric sensor (20), photoelectric sensor (20) includes third electrode (17), photosensitive pattern (18) and fourth electrode (19) sequentially stacked in the direction away from base (1), third electrode (17) is connected with the second electrode (14) of the same pixel unit of thin film transistor (16);Photoelectric sensor (20) and the area ratio of corresponding pixel unit is 40%-90%.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a texture recognition module and display device. Background Technology

[0002] In optical texture recognition, a pixel array is typically used for identification. Specifically, the pixel array includes multiple texture recognition pixel units arranged in an array. Each pixel unit includes a thin-film transistor (TFT) and a photoelectric sensor. The TFT provides a driving signal to the photoelectric sensor to control its operation. The photoelectric sensor receives detection light and outputs a corresponding electrical signal. This electrical signal is transmitted through the TFT to the sense line for processing by an external chip to obtain the valley and ridge information at the corresponding location. Summary of the Invention

[0003] This disclosure provides a texture recognition module, its preparation method, and a display device.

[0004] In a first aspect, embodiments of this disclosure provide a texture recognition module, including:

[0005] The substrate includes a texture recognition area and a surrounding area located around the texture recognition area;

[0006] A photoelectric sensing structure, located on the substrate and within the texture recognition area, includes: multiple gate lines, multiple signal sensing lines, and multiple pixel units defined by the intersection of the multiple gate lines and the multiple signal sensing lines; wherein, the pixel unit includes: a thin-film transistor, the gate of the thin-film transistor is electrically connected to the corresponding gate line, and the first electrode of the thin-film transistor is electrically connected to the corresponding signal sensing line;

[0007] The texture recognition area includes a photosensitive area, and the pixel unit located in the photosensitive area further includes a photoelectric sensor. The photoelectric sensor includes a third electrode, a photosensitive pattern, and a fourth electrode stacked sequentially along the direction away from the substrate. The third electrode is connected to the second electrode of the thin-film transistor located in the same pixel unit.

[0008] The area ratio of the photoelectric sensor to its corresponding pixel unit is 40% to 90%.

[0009] In some embodiments, the channel region of the thin-film transistor is inverted L-shaped or arc-shaped.

[0010] In some embodiments, the orthographic projection of the photoelectric sensor on the substrate does not overlap with the orthographic projection of the active layer of the thin-film transistor on the substrate.

[0011] In some embodiments, the gate line extends along a first direction, the signal sensing line extends along a second direction, and the first direction is perpendicular to the second direction;

[0012] The thin-film transistor includes: a gate, an active layer, a first electrode, and a second electrode. The first electrode has a rectangular cross-section parallel to the plane of the substrate. The first electrode has a first side and a second side disposed opposite to each other in the first direction, and a third side and a fourth side disposed opposite to each other in the second direction. The first electrode is electrically connected to the signal sensing line closest to its first side. The gate is electrically connected to the gate line closest to the third side of the first electrode.

[0013] The second electrode includes a first conductive portion and a second conductive portion. The first conductive portion extends along a first direction and is disposed opposite to a second side of the first electrode. The second conductive portion extends along a second direction and is disposed opposite to a fourth side of the first electrode. The first conductive portion and the second conductive portion are electrically connected.

[0014] In some embodiments, the second electrode further includes a third conductive portion, wherein the first conductive portion, the second conductive portion, and the third conductive portion are disposed in the same layer, the extension direction of the third conductive portion intersects both the first direction and the second direction, and the two ends of the third conductive portion are respectively connected to the first conductive portion and the second conductive portion.

[0015] In some embodiments, the texture recognition area further includes a virtual area located around the photosensitive area, wherein pixel units located in the virtual area are configured to output a reference noise signal to the corresponding signal sensing line.

[0016] In some embodiments, a planarization layer and a passivation layer are sequentially disposed on the side of the photosensitive pattern facing away from the substrate, and the fourth electrode is located on the side of the passivation layer facing away from the substrate and is electrically connected to the corresponding photosensitive pattern through vias on the planarization layer and the passivation layer.

[0017] The pixel unit located in the virtual region further includes a fifth electrode and a sixth electrode. The fifth electrode is electrically connected to the second electrode of the thin-film transistor located in the virtual region. The planarization layer and the passivation layer are located between the fifth electrode and the sixth electrode.

[0018] In some embodiments, a first insulating layer is formed on the side of the thin-film transistor away from the substrate, and a photosensitive sensor located in the photosensitive area is connected to the second electrode of the thin-film transistor through a via on the first insulating layer;

[0019] A planarization layer and a passivation layer are sequentially disposed on the side of the photosensitive pattern facing away from the substrate. The fourth electrode is located on the side of the passivation layer facing away from the substrate and is electrically connected to the corresponding photosensitive pattern through vias on the planarization layer and the passivation layer.

[0020] The pixel unit located in the virtual region further includes a fifth electrode and a sixth electrode. The fifth electrode is electrically connected to the second electrode of the thin-film transistor located in the virtual region. The fifth electrode and the third electrode are disposed in the same layer and with the same material. The sixth electrode and the fourth electrode are disposed in the same layer and with the same material. The fifth electrode and the sixth electrode include the first insulating layer, the planarization layer and the passivation layer.

[0021] In some embodiments, the pixel unit located in the virtual region further includes: a sensor reference structure, the sensor reference structure including: a fifth electrode, a reference pattern and a sixth electrode sequentially stacked along a direction away from the substrate, the fifth electrode being electrically connected to the second electrode of the thin film transistor located in the virtual region, the fifth electrode being disposed in the same layer and material as the third electrode, and the sixth electrode being disposed in the same layer and material as the fourth electrode;

[0022] The material of the reference pattern is a non-photoelectric material and its dielectric constant is approximately the same as that of the photosensitive pattern.

[0023] In some embodiments, the device further includes: a first light-shielding pattern located on the side of the photoelectric sensor away from the substrate, wherein the orthographic projection of the first light-shielding pattern on the substrate completely covers the virtual area but does not cover the photosensitive area.

[0024] In some embodiments, the virtual area is located on one side of the photosensitive area.

[0025] In some embodiments, the virtual area is located on opposite sides or intersecting sides of the photosensitive area.

[0026] In some embodiments, the virtual area is located on all four sides of the photosensitive area.

[0027] In some embodiments, the thin-film transistor contained in the pixel unit located in the photosensitive area and the thin-film transistor contained in the pixel unit located in the virtual area have the same structure, shape and size.

[0028] In some embodiments, the texture recognition module further includes:

[0029] A collimation structure is located on the side of the photoelectric sensing structure away from the substrate, and at least covers the photosensitive area;

[0030] The collimation structure includes an aperture layer, which includes a plurality of light-transmitting holes arranged in an array.

[0031] In some embodiments, the collimation structure further includes: a dielectric light-transmitting layer, a lens layer, and a planar light-transmitting layer, which are sequentially stacked on the side of the aperture layer away from the substrate and in a direction away from the substrate;

[0032] The lens layer includes a plurality of convex lenses that correspond one-to-one with the light-transmitting holes, and the optical axis of the convex lenses passes through the corresponding light-transmitting holes.

[0033] In some embodiments, the convex lens is a plano-convex lens, wherein the planar surface of the plano-convex lens faces the light-transmitting medium and is in contact with the surface of the light-transmitting medium, and the convex surface of the plano-convex lens faces the light-transmitting medium and is in contact with the surface of the light-transmitting medium.

[0034] In some embodiments, one photoelectric sensor corresponds to multiple light-transmitting holes, and one light-transmitting hole corresponds to one photoelectric sensor.

[0035] In some embodiments, the number of light-transmitting holes corresponding to each photoelectric sensor is the same;

[0036] The number of light-transmitting holes corresponding to one of the photoelectric sensors ranges from 4 to 100.

[0037] In some embodiments, the texture recognition module further includes:

[0038] A non-visible light filter layer is located on the side of the photoelectric sensor away from the substrate and is configured to filter out non-visible light in the transmitted light.

[0039] In some embodiments, the non-visible light filter layer includes an infrared filter layer configured to filter out infrared light from the transmitted light.

[0040] In some embodiments, the infrared filter layer includes: an infrared absorbing layer with infrared absorption function or an infrared reflecting layer with infrared reflection function.

[0041] In some embodiments, the non-visible light filter layer is located between the collimation structure and the photoelectric sensor.

[0042] In some embodiments, the non-visible light filter layer is integrated within the collimation structure.

[0043] In some embodiments, the non-visible light filter layer fills the light-transmitting hole.

[0044] In some embodiments, the collimation structure includes: the aperture layer, the dielectric light-transmitting layer, the lens layer and the planar light-transmitting layer sequentially stacked along a direction away from the substrate, wherein the lens layer includes a plurality of convex lenses corresponding one-to-one with the light-transmitting aperture, and the optical axis of the convex lens passes through the corresponding light-transmitting aperture;

[0045] At least one of the medium light-transmitting layer and the planar light-transmitting layer is reused as the non-visible light filter layer.

[0046] In some embodiments, the photoelectric sensing structure includes: a gate, a gate insulating layer, an active layer, a first conductive electrode layer, a first insulating layer, a photosensitive pattern, a planarization layer, a passivation layer, and a second conductive electrode layer, which are sequentially stacked along a direction away from the substrate, wherein the first light-shielding pattern is located on the side of the second conductive electrode layer away from the substrate;

[0047] The first conductive electrode layer includes: the first electrode, the second electrode and the third electrode, and the second conductive electrode layer includes: the fourth electrode.

[0048] In some embodiments, a second insulating layer is provided on the side of the fourth electrode away from the substrate, and a bias trace is provided on the side of the second insulating layer away from the substrate and located in the peripheral region. The fourth electrode extends to the peripheral region and is electrically connected to the bias trace through a via on the second insulating layer.

[0049] In some embodiments, the material of the bias trace includes a metallic material, and the first light-shielding pattern is disposed on the same layer as the bias trace.

[0050] In some embodiments, the texture recognition module further includes: a second light-shielding pattern, wherein the second light-shielding pattern is disposed on the same layer as the offset trace;

[0051] The orthographic projection of the second light-shielding pattern onto the substrate completely covers the orthographic projection of the channel region portion of the active layer within the thin-film transistor onto the substrate.

[0052] In some embodiments, the texture recognition module further includes: a barrier layer located on the side of the second light-shielding pattern away from the substrate and a ground shielding layer located on the side of the barrier layer away from the substrate, wherein the orthogonal projection of the ground shielding layer on the substrate completely covers the texture recognition area.

[0053] In some embodiments, the grounding shielding layer is electrically connected to the first light-shielding pattern and the second light-shielding pattern through a via on the barrier layer.

[0054] In some embodiments, the substrate is a flexible substrate, and a third insulating layer is disposed between the substrate and the photoelectric sensing structure.

[0055] Secondly, embodiments of this disclosure also provide a display device, comprising: the texture recognition module as provided in the first aspect, and a display panel located on the side of the first light-shielding pattern away from the substrate.

[0056] In some embodiments, the display panel and the texture recognition module are fixed together by optical adhesive;

[0057] Alternatively, the display panel and the texture recognition module may be spaced apart.

[0058] In some embodiments, the display panel is an OLED display panel, which includes an OLED display backplate, a polarizer, and a protective cover plate stacked sequentially along a direction away from the texture recognition module, wherein the material of the protective cover plate includes polyimide.

[0059] In some embodiments, the display device further includes:

[0060] The middle frame includes a base plate and a side wall formed by bending the edge of the base plate towards the front side. The base plate and the side wall form a receiving groove. The texture recognition module and the display panel are fixed in the receiving groove. The display panel is located on the side of the texture recognition module away from the base plate.

[0061] In some embodiments, the texture recognition module is fixed to the base plate.

[0062] In some embodiments, a stepped support structure is formed on the sidewall, and the display panel is fixed to the stepped support structure.

[0063] In some embodiments, a through hole is formed on the base plate, and the display device further includes: a flexible circuit board for texture recognition and a chip for texture recognition;

[0064] A flexible circuit board for texture recognition passes through the through hole, with one end electrically connected to a bonding electrode for texture recognition located in the peripheral area of ​​the texture recognition module, and the other end electrically connected to a texture recognition chip located on the back of the base plate.

[0065] In some embodiments, the display device further includes: a flexible circuit board for texture recognition and a chip for texture recognition, one end of the flexible circuit board for texture recognition being electrically connected to a bonding electrode for texture recognition located in the peripheral area of ​​the texture recognition module, and the other end of the flexible circuit board for texture recognition being electrically connected to the chip for texture recognition.

[0066] Both the flexible circuit board for texture recognition and the chip for texture recognition are located within the receiving slot.

[0067] Thirdly, embodiments of this disclosure also provide a method for preparing a texture recognition module as described in the first aspect, comprising:

[0068] A substrate is provided, including a texture recognition region and a peripheral region located around the texture recognition region;

[0069] A photoelectric sensing structure is formed on the substrate, located on the substrate and within the texture recognition area, including: multiple gate lines, multiple signal sensing lines, and multiple pixel units defined by the multiple gate lines and multiple signal sensing lines; wherein, the pixel unit includes: a thin-film transistor, the gate of the thin-film transistor is electrically connected to the corresponding gate line, and the first electrode of the thin-film transistor is electrically connected to the corresponding signal sensing line; the texture recognition area includes: a photosensitive area, and the pixel unit located within the photosensitive area further includes: a photoelectric sensor, the photoelectric sensor including a third electrode, a photosensitive pattern, and a fourth electrode sequentially stacked along a direction away from the substrate, the third electrode being connected to the second electrode of the thin-film transistor located in the same pixel unit; the area ratio of the photoelectric sensor to the corresponding pixel unit is 40% to 90%. Attached Figure Description

[0070] Figure 1 A top view schematic diagram of a texture recognition module provided in an embodiment of this disclosure;

[0071] Figure 2 A cross-sectional schematic diagram of the texture recognition module provided in an embodiment of this disclosure in the texture recognition area;

[0072] Figure 3 This is a top view of a pixel unit and its corresponding gate line and signal sensing line in an embodiment of this disclosure;

[0073] Figure 4a Another top view schematic diagram of the texture recognition module provided in the embodiments of this disclosure;

[0074] Figure 4b Another top view schematic diagram of the texture recognition module provided in the embodiments of this disclosure;

[0075] Figure 4c Another top view schematic diagram of the texture recognition module provided in the embodiments of this disclosure;

[0076] Figure 5 Another cross-sectional schematic diagram of the texture recognition module provided in the embodiment of this disclosure in the texture recognition area;

[0077] Figure 6 Another cross-sectional schematic diagram of the texture recognition module provided in the embodiment of this disclosure in the texture recognition area;

[0078] Figure 7 Another cross-sectional schematic diagram of the texture recognition module provided in the embodiment of this disclosure in the texture recognition area;

[0079] Figure 8 Another cross-sectional schematic diagram of the texture recognition module provided in the embodiment of this disclosure in the texture recognition area;

[0080] Figure 9a Another cross-sectional schematic diagram of the texture recognition module provided in the embodiment of this disclosure in the texture recognition area;

[0081] Figure 9b for Figure 9a A schematic cross-section of a collimation structure;

[0082] Figure 9c This is a top view schematic diagram of a photoelectric sensor corresponding to multiple light-transmitting holes in an embodiment of this disclosure;

[0083] Figure 9d This is another top view schematic diagram of a photoelectric sensor corresponding to multiple transparent holes in an embodiment of this disclosure;

[0084] Figure 10 Another cross-sectional schematic diagram of the texture recognition module provided in the embodiment of this disclosure in the texture recognition area;

[0085] Figure 11 This is a schematic diagram of the infrared filter layer filling the light-transmitting hole in an embodiment of this disclosure;

[0086] Figure 12 A schematic diagram of the structure of a display device provided in an embodiment of this disclosure;

[0087] Figure 13 This is another schematic diagram of the structure of the display device provided in the embodiments of this disclosure;

[0088] Figure 14 This is another schematic diagram of the structure of the display device provided in the embodiments of this disclosure;

[0089] Figure 15 This is another schematic diagram of the structure of the display device provided in the embodiments of this disclosure;

[0090] Figure 16 for Figures 13 to 15 A top view of the back of the midsole plate;

[0091] Figure 17 This is another schematic diagram of the structure of the display device provided in the embodiments of this disclosure;

[0092] Figure 18 This is a flowchart illustrating a method for preparing a texture recognition module according to an embodiment of the present disclosure. Detailed Implementation

[0093] To enable those skilled in the art to better understand the technical solutions of this disclosure, a texture recognition module, its preparation method, and display device provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0094] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are intended only to illustrate the contents of this disclosure.

[0095] The terminology used herein is for describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Without conflict, the various embodiments of this disclosure and the features within those embodiments may be combined with each other.

[0096] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0097] Display devices with texture recognition function generally include a display panel and a photoelectric sensing structure. When performing texture recognition, the fingerprint comes into contact with the surface of the display panel. The detection light emitted by the display panel is reflected off the fingerprint surface and then shines onto the photoelectric sensing structure. Each photoelectric sensor in the photoelectric sensing structure generates a corresponding electrical signal based on the received light (the detection light reflected off the fingerprint surface). This electrical signal is transmitted to an external chip through electrical structures such as driving transistors and signal sensing lines. The external chip identifies the valleys and ridges of the texture at the corresponding position based on the received electrical signal.

[0098] Figure 1 This is a top view schematic diagram of a texture recognition module provided in an embodiment of this disclosure. Figure 2 This is a cross-sectional schematic diagram of the texture recognition module provided in the embodiments of this disclosure in the texture recognition area, as shown below. Figure 1 and Figure 2 As shown, the texture recognition module includes: a substrate 1 and a photoelectric sensing structure 2.

[0099] The substrate 1 includes a texture recognition region 101 and a peripheral region 102 located around the texture recognition region 101. The substrate 1 can be a glass substrate 1 or a PI flexible substrate 1.

[0100] The photoelectric sensing structure 2 is located on the substrate 1 and within the texture recognition area, including: multiple gate lines 11a, multiple signal sensing lines 15, and multiple pixel units defined by the intersection of the multiple gate lines 11a and the multiple signal sensing lines 15. The pixel unit includes: a thin film transistor 16, the gate 11 of the thin film transistor 16 is electrically connected to the corresponding gate line, and the first electrode 13 of the thin film transistor 16 is electrically connected to the corresponding signal sensing line 15.

[0101] The texture recognition region 101 includes a photosensitive region A1, and the pixel unit located within the photosensitive region further includes a photoelectric sensor 20. The orthographic projection of the photoelectric sensor onto the substrate does not overlap with the orthographic projection of the active layer of the thin-film transistor onto the substrate.

[0102] In some embodiments, a first insulating layer 5 is formed on the side of the thin film transistor 16 away from the substrate 1, and the photoelectric sensor 20 located in the photosensitive area A1 is connected to the second electrode 14 of the corresponding thin film transistor 16 through a via on the first insulating layer 5.

[0103] The pixel unit located within the photosensitive area A1 is configured to generate a corresponding electrical signal (implemented by the photoelectric sensor 20) based on the received light and output the electrical signal (implemented by the thin-film transistor 16) to the corresponding signal sensing line for texture recognition. The area ratio of the photoelectric sensor to the corresponding pixel unit is 40% to 90%.

[0104] The photoelectric sensor 20 can be a PIN photodiode or a PN photodiode. Specifically, the photoelectric sensor 20 includes a third electrode 17, a photosensitive pattern 18, and a fourth electrode 19 sequentially stacked along a direction away from the substrate 1. The third electrode 17 is electrically connected to the second electrode 14 of the thin-film transistor 16 located in the same pixel unit. The voltage applied to the third electrode 17 can be controlled by the thin-film transistor 16, thereby controlling the operating state of the photoelectric sensor 20.

[0105] The photosensitive pattern 18 includes a stacked P-type semiconductor layer and an N-type semiconductor layer (e.g., an N-type Si layer), or a stacked P-type semiconductor layer (e.g., a P-type Si layer), an intrinsic semiconductor layer (e.g., an intrinsic Si layer), and an N-type semiconductor layer (e.g., an N-type Si layer). For example, the I layer is a-Si material, the P layer is a-Si material doped with B ions, and the N layer is a-Si material doped with P ions.

[0106] In some embodiments, the fourth electrode 19 is a transparent electrode, which may be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc gallium oxide (GZO). In some embodiments, an ohmic contact layer 21 is provided between the fourth electrode 19 and the photosensitive pattern 18 to reduce the contact resistance between the fourth electrode 19 and the photosensitive pattern 18. The ohmic contact layer 21 is made of a metallic material and has good overall light transmittance. The third electrode 17 is a metallic electrode, which may be made of metallic materials or alloys such as copper (Cu), aluminum (Al), or titanium (Ti).

[0107] It should be noted that in the embodiments of this disclosure, "transparent" means that the structure can transmit light, not that the structure has a light transmittance of 100%.

[0108] In this embodiment, the pixel unit located in the photosensitive area A1 outputs an electrical signal corresponding to the received light to the corresponding signal sensing line 15 for processing by an external chip to obtain the valley ridge information at the corresponding position, thereby realizing texture recognition.

[0109] It should be noted that the peripheral area 102 of the texture recognition module generally includes a bonding area, within which bonding electrodes are disposed. Depending on their function, the bonding area typically includes a gate driver chip bonding area C1 and a data driver chip bonding area C2. The bonding electrode located in the gate driver chip bonding area C1 is a bonding electrode for the gate driver chip, and the bonding electrode located in the data driver chip bonding area C2 is a bonding electrode for the data driver chip. The arrangement of the bonding area and bonding electrodes is conventional technology in this field and will not be described in detail herein.

[0110] Figure 3 This is a top view schematic diagram of a pixel unit and its corresponding gate line and signal sensing line in an embodiment of this disclosure, as shown below. Figure 3 As shown, the thin-film transistor 16 includes: a gate 11, an active layer 12, a first electrode 13, and a second electrode 14. The first electrode 13 specifically refers to the source of the thin-film transistor 16, and the second electrode 14 specifically refers to the drain of the thin-film transistor 16. The region on the active layer 12 located between the first electrode 13 and the second electrode 14 is a channel region, and the channel region of the thin-film transistor is in the shape of an inverted L or an arc.

[0111] In some embodiments, the gate line 11a extends along a first direction X, and the signal sensing line 15 extends along a second direction Y, wherein the first direction X and the second direction Y are perpendicular; Figure 5In the diagram, the first direction X is horizontal, and the second direction Y is vertical. The first electrode 13 has a rectangular cross-section parallel to the plane of the substrate 1. The first electrode 13 has a first side and a second side disposed opposite to each other in the first direction, and a third side and a fourth side disposed opposite to each other in the second direction. The first electrode 13 is electrically connected to the signal sensing line 15 closest to its first side, and the gate 11 is electrically connected to the gate line 11a closest to the third side of the first electrode 13. The second electrode 14 includes a first conductive portion 14a and a second conductive portion 14b. The first conductive portion 14a extends along the first direction and is disposed opposite to the second side of the first electrode 13, and the second conductive portion 14b extends along the second direction and is disposed opposite to the fourth side of the first electrode 13. The first conductive portion 14a and the second conductive portion 14b are electrically connected.

[0112] Unlike conventional thin-film transistors (TFTs) where the source and drain are strip-shaped and parallel to each other, in this embodiment, the source is rectangular, and the drain is positioned opposite to two sides (the second and fourth sides) of the source. This increases the width of the channel region on the active layer 12. With a fixed channel width-to-length ratio for the TFT 16, the size of the source can be reduced accordingly (the overall length of the drain is approximately equal to the length of the strip-shaped drain in a conventional TFT 16). This reduces the overlap capacitance between the source and other structures (e.g., the capacitance between the source and gate 11), which helps reduce the inherent noise of the TFT 16 and improves the accuracy of texture recognition.

[0113] In some embodiments, the second electrode 14 further includes a third conductive portion 14c. The first conductive portion 14a, the second conductive portion 14b, and the third conductive portion 14c are disposed in the same layer. The extending direction of the third conductive portion 14c intersects both the first direction and the second direction. The two ends of the third conductive portion 14c are respectively connected to the first conductive portion 14a and the second conductive portion 14b. In this case, the channel region on the active layer 12 is inverted "L" shape.

[0114] It should be noted that the thin-film transistor 16 with the inverted "L"-shaped channel region described above is an optional embodiment of the present disclosure and does not limit the technical solution of the present disclosure.

[0115] In practical applications, it has been found that the electrical signals generated by the pixel units within the photosensitive area and ultimately transmitted to the external chip are subject to noise interference, resulting in inaccurate electrical signals received by the external chip and thus affecting the accuracy of texture recognition. To solve this technical problem, noise reduction processing can be performed on the output electrical signals of the pixel units within the photosensitive area A1 received by the external chip before imaging based on the electrical signals.

[0116] In some embodiments, to facilitate subsequent noise reduction processing of the electrical signals output by the pixel units located in the photosensitive area A1, a dummy area A2 located outside the photosensitive area A1 is also provided in the texture recognition area 101. The pixel units located in the dummy area A2 are configured to output a reference noise signal to the corresponding signal sensing line. The reference noise signal can be used to perform noise reduction processing on the electrical signals output by the pixel units in the photosensitive area A1 received by the external chip, which is beneficial to improving the recognition accuracy of texture information in the photosensitive area A1.

[0117] In some embodiments, the number of pixel units within the virtual area A2 is multiple. The noise signals output by all pixel units within the virtual area A2 can be pre-processed to obtain a reference noise signal (e.g., averaging all noise signals, selecting the noise signal with the largest current value, or selecting the noise signal with the smallest current value, etc.). Then, the electrical signal output by the pixel units within the photosensitive area A1 is denoised based on the reference noise signal. As an example, the magnitude of the current (or voltage) of the electrical signal output by the pixel units within the photosensitive area A1 can be directly subtracted from the magnitude of the current (voltage) of the reference noise signal. It should be noted that the specific algorithm for denoising the signal based on the noise signal is not limited in this disclosure.

[0118] Figure 4a This is another top view schematic diagram of the texture recognition module provided in the embodiments of this disclosure. Figure 4b This is another top view schematic diagram of the texture recognition module provided in the embodiments of this disclosure. Figure 4c This is another top view schematic diagram of the texture recognition module provided in the embodiments of this disclosure, as shown below. Figure 1 as well as Figures 4a-4b As shown, Figure 1 The image shows the case where virtual area A2 is located to one side of photosensitive area A1. Figure 4a The image shows a scenario where virtual area A2 is located on either side of photosensitive area A1. Figure 4b The image shows a scenario where virtual area A2 is located on either side of the intersection with photosensitive area A1. Figure 4c The image shows a case where the virtual area A2 is located on all four sides of the photosensitive area A1.

[0119] Of course, in some embodiments, the virtual area A2 may also be located on three different sides of the photosensitive area A1, in which case no corresponding figure is given.

[0120] In some embodiments, the thin-film transistor 16 included in the pixel unit located in the photosensitive area A1 and the thin-film transistor 16 included in the pixel unit located in the virtual area A2 have the same structure, shape, and size. In this case, the inherent noise of the thin-film transistor 16 included in the pixel unit located in the photosensitive area A1 and the thin-film transistor 16 included in the pixel unit located in the virtual area A2 is the same or approximately the same. Therefore, noise reduction processing is performed on the electrical signal output by the pixel unit (thin-film transistor 16) in the photosensitive area A1 based on the noise signal output by the pixel unit (thin-film transistor 16) in the virtual area A2, resulting in better noise reduction and improved texture recognition accuracy.

[0121] See Figure 2 As shown, in some embodiments, a planarization layer 6 and a passivation layer 7 are sequentially disposed on the side of the photosensitive pattern 18 facing away from the substrate 1. Vias corresponding to the photosensitive pattern 18 are formed on the planarization layer 6 and the passivation layer 7, so that at least a portion of the surface of the photosensitive pattern 18 facing away from the substrate 1 is exposed. The fourth electrode 19 is located on the side of the passivation layer 7 facing away from the substrate 1 and is electrically connected to the corresponding photosensitive pattern 18 through the vias on the planarization layer 6 and the passivation layer 7. The pixel unit located in the virtual region A2 further includes a fifth electrode 17a and a sixth electrode 19a. The fifth electrode 17a is connected to the second electrode 14 of the thin-film transistor in the virtual region. A planarization layer 6 and a passivation layer 7 are included between the fifth electrode 17a and the sixth electrode 19a. Optionally, the fifth electrode and the second electrode of the thin-film transistor can be disposed in the same layer or in different layers.

[0122] See Figure 2 As shown, in some embodiments, a planarization layer 6 and a passivation layer 7 are sequentially disposed on the side of the photosensitive pattern 18 facing away from the substrate 1. Through holes corresponding to the photosensitive pattern 18 are formed on the planarization layer 6 and the passivation layer 7, so that at least part of the surface of the photosensitive pattern 18 facing away from the substrate 1 is exposed. The fourth electrode 19 is located on the side of the passivation layer 7 facing away from the substrate 1 and is electrically connected to the corresponding photosensitive pattern 18 through the through holes on the planarization layer 6 and the passivation layer 7. The pixel unit located in the virtual region A2 further includes: a fifth electrode 17a and a sixth electrode 19a. The fifth electrode 17a is connected to the second electrode 14 of the thin film transistor in the virtual region. The fifth electrode 17a and the third electrode are disposed in the same layer and with the same material. The sixth electrode 19a and the fourth electrode are disposed in the same layer and with the same material. A first insulating layer 5, a planarization layer 6, and a passivation layer 7 are included between the fifth electrode 17a and the sixth electrode 19a.

[0123] exist Figure 2 In the case shown, the pixel unit located in the virtual area A2 does not have a photosensitive pattern 18 (filled by a planarization layer), that is, the pixel unit located in the virtual area A2 will not produce a photoelectric effect. At this time, the electrical signal output by the pixel unit located in the virtual area A2 can be used as a reference noise signal.

[0124] Figure 5 This is another cross-sectional schematic diagram of the texture recognition module provided in the embodiments of this disclosure in the texture recognition area, as shown below. Figure 5 As shown, with Figure 2 The pixel units located within virtual area A2 are different. Figure 5 The pixel unit located in the virtual area A2 shown includes not only the thin-film transistor 16, but also a sensor reference structure 25. The sensor reference structure 25 includes a fifth electrode 17a, a reference pattern 24, and a sixth electrode 19a stacked sequentially along the direction away from the substrate 1. The fifth electrode 17a is electrically connected to the second electrode 14 of the corresponding thin-film transistor. The dielectric constant of the reference pattern 24 is approximately the same as that of the photosensitive pattern 18, and the reference pattern 25 is made of a non-photoelectric material. The connection method between the sixth electrode 19a and the reference pattern 24 in the sensor reference structure 25 is the same as the connection method between the fourth electrode 19 and the photoelectric pattern 18 in the photoelectric sensing structure 2.

[0125] In this embodiment, the sensor reference structure 25 is similar in structure to the photoelectric sensing structure 2, and the dielectric constant of the reference pattern 24 is the same as that of the photosensitive pattern 18. This allows the pixel units located in the virtual area A2 and the pixel units located in the photosensitive area A1 to have the same or approximately the same noise. In this case, the electrical signal output by the pixel units in the photosensitive area A1 is denoised based on the noise signal output by the pixel units in the virtual area A2, resulting in better noise reduction and improved texture recognition accuracy. Furthermore, even if there is illumination at the virtual area A2, the reference pattern, being made of non-photoelectric materials, will not generate current due to illumination, thus preventing the illumination from affecting the noise signal output by the pixel units in the virtual area A2.

[0126] Figure 6 This is another cross-sectional schematic diagram of the texture recognition module provided in the embodiments of this disclosure in the texture recognition area. Figure 7 This is another cross-sectional schematic diagram of the texture recognition module provided in the embodiments of this disclosure in the texture recognition area, as shown below. Figure 6 and Figure 7 As shown, with Figure 2 and Figure 5 The situation shown is different, in Figure 6 In the illustrated case, the texture recognition module further includes: a first light-shielding pattern 3, which is located on the side of the sixth electrode 19a away from the substrate 1. The orthographic projection of the first light-shielding pattern 3 on the substrate 1 completely covers the virtual area A2 but does not cover the photosensitive area A1.

[0127] By setting the first light-blocking pattern 3, light can be effectively prevented from shining on the pixel units located in the virtual area A2, so as to ensure that the noise signal output by the pixel units located in the virtual area A2 is not affected by the lighting factor, which is conducive to improving the subsequent noise reduction effect.

[0128] See Figure 2 , Figures 5-7 As shown, the third electrode 17 and the fifth electrode 17a are arranged in the same layer as the second electrode 14, that is, each third electrode 17 and the fifth electrode 17a is directly connected to the corresponding second electrode 14.

[0129] In some embodiments, the photoelectric sensing structure 2 includes: gates 11 (generally made of metal material, with a thickness of [missing information]) sequentially stacked along a direction away from the substrate 1. ), gate insulating layer 4 (generally made of inorganic insulating material, including: SiNx or SiO2), active layer 12 (material is a-Si or single crystal silicon), first conductive electrode layer (generally made of metal material, thickness is...), Specifically, it includes: a first electrode 13, a second electrode 14, a third electrode 17, a fifth electrode 17a, a signal sensing line 15, a first insulating layer 5 (generally made of inorganic insulating material, including SiNx or SiO2), and a photosensitive pattern 18 (thickness is...). Photoelectric conversion material), planarization layer 6 (thickness is Organic materials), passivation layer 7 (thickness is...) The SiNx or SiO2 is used to ensure the adhesion of subsequent film layers to the surface of planarization layer 6, and the second conductive electrode layer (thickness is...) The transparent conductive material specifically includes: a fourth electrode 19 and a sixth electrode 19a). The gate electrode 11, the active layer 12, the first electrode 13, and the second electrode 14 constitute a thin-film transistor 16, while the third electrode 17, the photosensitive pattern 18, and the fourth electrode 19 constitute a photoelectric sensor 20.

[0130] Correspondingly, the fabrication process of each film layer mask within the texture recognition area 101 includes: gate 11 → gate insulating layer 4 → active layer 12 → first conductive electrode layer → first insulating layer 5 → third electrode 17 → photosensitive pattern 18 → planarization layer 6 → passivation layer 7 → second conductive electrode layer. The fourth electrode 19 is electrically connected to the photosensitive pattern 18 through vias on the passivation layer 7 and the planarization layer 6. The planarization layer 6 and the passivation layer 7 can be patterned separately, therefore the via sizes on them are different; in some embodiments, the via size on the passivation layer 7 is smaller than the via size on the planarization layer 6. For example, the via radius on the passivation layer 7 is 3.5µm to 4µm smaller than the corresponding via radius on the planarization layer 6.

[0131] It should be noted that when a reference pattern 24 exists in the virtual area, and the material of the reference pattern 24 is different from that of the photosensitive pattern 18, the process of preparing the third electrode 17 / fifth electrode 17a and the planarization layer 6 includes not only the process of preparing the photosensitive pattern 18, but also the process of preparing the reference pattern 24.

[0132] Figure 8 This is another cross-sectional schematic diagram of the texture recognition module provided in the embodiments of this disclosure in the texture recognition area, as shown below. Figure 8 As shown, with Figure 2 , Figures 5-7 The third electrode shown is arranged in a different layer than the second electrode. Figure 8 In the case shown, the third electrode 17 and the second electrode 14 are disposed in different layers, and each third electrode 17 is connected to the corresponding second electrode 14 through a via on the first insulating layer 5; this case should also fall within the protection scope of this disclosure.

[0133] In addition, when the third electrode 17 of the photoelectric sensor 20 is electrically connected to the second electrode 14 of the thin film transistor 16 through a via on the first insulating layer 5, the via is preferably located at the edge of the reference pattern 24, which helps to reduce the leakage current of the photoelectric sensor.

[0134] See you again Figures 1-8 As shown, in some embodiments, a second insulating layer 8 is provided on the side of the fourth electrode 19 away from the substrate 1, and a bias trace 22 is provided on the side of the second insulating layer 8 away from the substrate 1 and located in the peripheral area. The fourth electrode 19 extends to the peripheral area 102 and is electrically connected to the bias trace 22 through a via on the second insulating layer 8.

[0135] In some embodiments, the bias trace 22 is made of a metallic material, and the first light-shielding pattern 3 is disposed on the same layer as the bias trace 22. That is, the first light-shielding pattern 3 can be fabricated simultaneously based on the existing manufacturing process of the bias trace 22, thus effectively shortening the product manufacturing cycle and reducing production costs. In addition, generally speaking, the bias trace 22 is disposed on the same layer as the bonding electrode located in the peripheral region 102.

[0136] In some embodiments, the texture recognition module further includes a second light-shielding pattern 23, which is disposed on the same layer as the bias trace 22, and the orthographic projection of the second light-shielding pattern 23 on the substrate 1 completely covers the orthographic projection of the channel region portion of the active layer 12 within the thin-film transistor 16 on the substrate 1. The second light-shielding pattern 23 is used to prevent external light from shining on the channel region of the active layer 12, so as to prevent the electrical characteristics of the thin-film transistor 16 from shifting due to light illumination.

[0137] In some embodiments, the texture recognition module further includes a barrier layer 9 and a grounding shielding layer 10. The barrier layer 9 is located on the side of the second light-shielding pattern 23 away from the substrate 1, and the grounding shielding layer 10 is located on the side of the barrier layer 9 away from the substrate 1. The orthographic projection of the grounding shielding layer 10 onto the substrate 1 completely covers the texture recognition area 101. In this embodiment, by providing the grounding shielding layer 10, the noise influence caused by the electromagnetic coupling of the display panel 28 to the photoelectric sensor 20 can be effectively shielded, which is beneficial to improving the accuracy of texture recognition.

[0138] In some embodiments, the grounding shielding layer 10 is electrically connected to the second light-shielding pattern 23 through a via on the barrier layer 9, which can effectively prevent the problem of charge accumulation and discharge on the second light-shielding pattern 23. Additionally, when the first light-shielding pattern 3 and the bias trace are disposed on the same layer, the grounding shielding layer 10 is electrically connected to the first light-shielding pattern 3 through a via on the barrier layer 9, which can effectively prevent the problem of charge accumulation and discharge on the first light-shielding pattern 3.

[0139] Figure 9a This is another cross-sectional schematic diagram of the texture recognition module provided in the embodiments of this disclosure in the texture recognition area. Figure 9b for Figure 9a A schematic diagram of a cross-section of a collimation structure. Figure 9c This is a top view schematic diagram of a photoelectric sensor corresponding to multiple light-transmitting holes in an embodiment of this disclosure. Figure 9d This is another top view schematic diagram of a photoelectric sensor corresponding to multiple transparent holes in an embodiment of this disclosure, as shown below. Figures 9a to 9d As shown, in some embodiments, the texture recognition module further includes: a collimation structure 26, located on the side of the photoelectric sensing structure 2 away from the substrate 1, and the collimation structure 26 at least covers the photosensitive area A2; the collimation structure 26 includes: an aperture layer 261, which includes: a plurality of light-transmitting holes 261a arranged in an array. The light-transmitting holes 261a can collimate the light.

[0140] In some embodiments, one photoelectric sensor 20 corresponds to multiple light-transmitting holes 261a, and one light-transmitting hole 261a corresponds to one photoelectric sensor 20. Further, the number of light-transmitting holes 261a corresponding to each photoelectric sensor 20 is the same; the number of light-transmitting holes 261a corresponding to one photoelectric sensor 20 includes 4 to 100. Specifically, the number of light-transmitting holes 261a corresponding to the photoelectric sensor 20 refers to the number of light-transmitting holes 261a located within the area of ​​the photosensitive pattern 18 within the photoelectric sensor 20. The intensity of the light signal received by the photoelectric sensor 20 is related to the number of light-transmitting holes 261a corresponding to the photoelectric sensor 20. Generally speaking, the more light-transmitting holes 261a there are, the stronger the light signal intensity received by the photoelectric sensor 20, and the larger the current of the electrical signal output by the photoelectric sensor 20, which is more beneficial for electrical signal detection. Meanwhile, when the number of light-transmitting holes 261a is too large, the spacing between adjacent light-transmitting holes 261a decreases, increasing the risk of light crosstalk. Considering the difficulty of signal detection and the risk of light crosstalk, the number of light-transmitting holes 261a in this embodiment is 4 to 100; in principle, each photoelectric sensor 20 corresponds to at least one light-transmitting hole 261a. Furthermore, by ensuring that the number of light-transmitting holes 261a corresponding to each photoelectric sensor 20 is the same, it helps to avoid the difference in the number of light-transmitting holes 261a interfering with the imaging quality.

[0141] Multiple light-transmitting holes 261a corresponding to the same photoelectric sensor 20 are uniformly distributed within the area where the photosensitive pattern 18 is located in the photoelectric sensor 20. See, as an example... Figure 9c As shown, the multiple light-transmitting holes 261a corresponding to the same photoelectric sensor 20 are arranged in a matrix in the row and column directions, and the distance between two adjacent light-transmitting holes 261a in the row direction or in the column direction is equal. See also [reference needed]. Figure 9d As shown, the multiple light-transmitting holes 261a corresponding to the same photoelectric sensor 20 are arranged in a hexagonal pattern, with the distance between any two adjacent light-transmitting holes 261a being [not specified]. Of course, the light-transmitting holes 261a in this embodiment can also adopt other arrangements, which will not be described in detail here.

[0142] See Figure 9b As shown, in some embodiments, the collimation structure 26 further includes: a dielectric light-transmitting layer 262, a lens layer 263, and a planar light-transmitting layer 264, which are sequentially stacked on the side of the aperture layer 261 away from the substrate 1 and in the direction away from the substrate 1; the lens layer 263 includes a plurality of convex lenses 263a corresponding one-to-one with the light-transmitting holes 261a, and the optical axis of the convex lens 263a passes through the corresponding light-transmitting hole 261a.

[0143] Furthermore, the convex lens is a plano-convex lens 263a, with the planar surface of the plano-convex lens 263a facing the medium light-transmitting layer 262 and being attached to the surface of the medium light-transmitting layer 262, and the convex surface of the plano-convex lens 263a facing the plano light-transmitting layer 264 and being attached to the surface of the plano light-transmitting layer 264.

[0144] In this embodiment, the convex lens 263a modulates the propagation direction of light reflected by the texture, reducing the tilt angle of some light rays and concentrating the propagation direction of the resulting converging beam. The aperture layer 261 only allows converging beams at specific angles to pass through, collimating the converging beam output by the convex lens and improving the directional consistency of the converging beam received by the sensor. Specifically, the light-transmitting holes 261a of the aperture layer 261 correspond one-to-one with the convex lenses 263a, ensuring that the light converged by each convex lens 263a passes through the same-sized hole and undergoes the same collimation, reducing signal differences.

[0145] It should be noted that the collimation structure 26 can be bonded and fixed to the photoelectric sensing structure 2 by optical OCA adhesive, or it can be directly prepared on the photoelectric sensing structure 2 by thin film deposition, thin film patterning and other processes. Both of these situations are within the protection scope of this disclosure.

[0146] Figure 10 This is another cross-sectional schematic diagram of the texture recognition module provided in the embodiments of this disclosure in the texture recognition area, as shown below. Figure 10 As shown, in some embodiments, the texture recognition module further includes a non-visible light filter layer 27. The non-visible light filter layer 27 is located on the side of the photoelectric sensor 20 away from the substrate 1 and is configured to filter out non-visible light from the transmitted light.

[0147] In some embodiments, the non-visible light filter layer 27 is an infrared filter layer, configured to filter out infrared light from the transmitted light. Under strong ambient light, most of the light transmitted through a finger is infrared light (wavelength range of 760nm to 1mm), while the detection light emitted by the display panel 28 after reflection from the fingerprint surface is visible light (wavelength range of 400nm to 700nm). In this embodiment, the infrared filter layer is configured to block infrared light while allowing visible light to pass through, so that the detection light reflected from the finger can pass through but the infrared light transmitted through the finger cannot, thereby reducing the influence of ambient light signals on the photoelectric sensor 20 and improving the product's resistance to strong light.

[0148] In some embodiments, the infrared filter layer includes: an infrared absorbing layer with infrared absorption function or an infrared reflective layer with infrared reflection function. When the infrared filter layer is an infrared absorbing layer with infrared absorption function, it may be composed of a material with infrared filtering function; when the infrared filter layer is an infrared reflective layer with infrared reflection function, it may be composed of a material with infrared reflection function or a stack of materials with different dielectric constants.

[0149] In some embodiments, when the texture recognition module includes a collimation structure 26, the non-visible light filter layer 27 is located between the collimation structure 26 and the photoelectric sensor 20, or the non-visible light filter layer 27 is integrated within the collimation structure 26.

[0150] See Figure 10 As shown, the non-visible light filter layer 27 is disposed as an independent structure between the collimation structure 26 and the photoelectric sensor 20.

[0151] The non-visible light filter layer 27 can be attached to the photoelectric sensing structure 2 by optical OCA adhesive, or it can be directly formed on the surface of the photoelectric sensing structure 2 by coating process. Both of these situations are within the protection scope of this disclosure.

[0152] Figure 11 This is a schematic diagram of a non-visible light filter layer filling the light-transmitting hole in an embodiment of this disclosure, as shown below. Figure 11 As shown, when the non-visible light filter layer 27 is integrated into the collimation structure 26, as an example, the non-visible light filter layer 27 fills the light transmission hole 261a.

[0153] See also Figure 9b As shown, as another example, when the collimation structure 26 includes a dielectric light-transmitting layer, a lens layer 263 and a planar light-transmitting layer 264, at least one of the dielectric light-transmitting layer and the planar light-transmitting layer 264 is made of an organic material with non-visible light absorption (e.g., infrared light absorption) and is reused as a non-visible light filter layer 27.

[0154] In some embodiments, the substrate 1 is a flexible substrate 1, and a third insulating layer (not shown) is disposed between the substrate 1 and the photoelectric sensing structure 2. Before fabricating the photoelectric sensing structure 2 on the PI flexible substrate 1, a third insulating layer of a certain thickness is first formed on the substrate 1. The material of the third insulating layer includes SiNx and SiO2, which can block water and oxygen, prevent water and oxygen from penetrating from the back side of the PI flexible substrate 1 after peeling and damaging the device and optical film, and facilitate the deposition of subsequent film layers; on the other hand, by adjusting the process conditions of SiNx or the SiNx / SiO2 ratio, the film layer stress can be changed, which can offset the stress of subsequent film layers, avoid stress accumulation, and prevent excessive stress and spontaneous curling after the flexible device is peeled off, which would lead to film layer breakage.

[0155] It should be noted that the different technical features in the above embodiments can be combined with each other, and the technical solution of the texture recognition module obtained by combining technical features is also within the protection scope of this disclosure.

[0156] Based on the same inventive concept, this disclosure also provides a display device. Figure 12 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure, such as... Figure 12 As shown, the display device includes a texture recognition module and a display panel 28, wherein the texture recognition module can be the texture recognition module 100 provided in any of the preceding embodiments, and the display panel 28 is located on the side of the first light-shielding pattern 3 away from the substrate 1.

[0157] In some embodiments, the display panel 28 may be an organic light-emitting diode (OLED) display panel 28 or a quantum dot light-emitting diode (QLED) display panel 28, etc., and the embodiments disclosed herein are not specifically limited thereto. The OLED display panel 28 may be, for example, a flexible OLED display panel 28. For example, both the OLED display panel 28 and the QLED display panel 28 have self-emissive characteristics, and the emission of their display pixel units can be controlled or modulated as needed, thereby facilitating texture acquisition and helping to improve the integration of the device.

[0158] The OLED display panel 28 generally includes a flexible OLED display backplate 281, a polarizer 282, and a protective cover plate 283, which are sequentially stacked along a direction away from the texture recognition module 100. The protective cover plate 283 can be made of polyimide (PI). The substrate of the flexible OLED display backplate 281 is a flexible substrate, and the specific material can be PI or other flexible materials.

[0159] In some embodiments, the display panel 28 and the texture recognition module 100 are fixed together by optical adhesive. In other embodiments, the display panel 28 and the texture recognition module 100 are spaced apart. These will be described in detail below with reference to specific embodiments.

[0160] Figure 13 This is another schematic diagram of the structure of the display device provided in the embodiments of this disclosure, such as... Figure 13As shown, in some embodiments, the display device further includes: a middle frame 400, the middle frame 400 including a base plate 401 and a side wall 402 formed by bending the edge of the base plate 401 toward the front side, the base plate 401 and the side wall 402 forming a receiving groove, the texture recognition module 100 and the display panel 28 are fixed in the receiving groove, and the display panel 28 is located on the side of the texture recognition module 100 away from the base plate 401.

[0161] See Figure 13 As shown, the texture recognition module 100 is fixed on the base plate 401, and the display panel 28 and the texture recognition module 100 are fixed together by optical adhesive, thereby realizing the fixation of the display panel 28, the texture recognition module 100 and the middle frame 400.

[0162] Figure 14 This is another schematic diagram of the structure of the display device provided in the embodiments of this disclosure, such as... Figure 14 As shown, with Figure 13 The situation shown is different, Figure 14 In the illustrated case, the display panel 28 and the texture recognition module 100 are fixed together by optical adhesive. A stepped support structure 404 is formed on the side wall 402. The display panel 28 is fixed on the stepped support structure 404, which can also achieve the fixation of the display panel 28, the texture recognition module 100 and the middle frame 400.

[0163] Figure 15 This is another schematic diagram of the display device provided in the embodiments of this disclosure, such as... Figure 15 As shown, with Figure 13 and Figure 14 The situation shown is different, Figure 15 In the illustrated configuration, the display panel 28 and the texture recognition module 100 are spaced apart, with an air gap 29 between them. At this time, the texture recognition module 100 is fixed to the base plate 401 and the display panel 28 is fixed to the stepped support structure 404.

[0164] In some embodiments, the minimum spacing between the display panel 28 and the texture recognition module 100 is greater than or equal to 100 μm.

[0165] If the display panel 28 and the texture recognition module 100 are too close, electromagnetic coupling will occur, increasing the noise of the photoelectric sensor 20 within the texture recognition module 100 and resulting in poor final image quality. Furthermore, moiré patterns will form between the display pixel units within the display panel 28 and the texture recognition pixel units within the texture recognition module 100, affecting subsequent image processing and texture recognition. In this embodiment, by spacing the display panel 28 and the texture recognition module 100, the distance between them is increased, reducing coupling noise and avoiding moiré patterns, thus improving texture imaging quality.

[0166] Figure 16 for Figures 13 to 15 A top view of the back of the midsole plate, such as... Figure 16 As shown, in some embodiments, a through hole 403 is formed on the base plate 401. The display device further includes a flexible circuit board 501 for texture recognition and a texture recognition chip 502. The flexible circuit board 501 for texture recognition passes through the through hole 403, with one end electrically connected to a bonding electrode located in the bonding area within the texture recognition module 100 (generally achieved through a bonding process), and the other end electrically connected to the texture recognition chip 502 located on the back of the base plate 401 (generally achieved through a die-bonding thin film process). Similarly, the display chip (not shown) and the flexible circuit board for display can also be electrically connected to the display panel 28 located in the receiving groove in the same manner.

[0167] Figure 17 This is another schematic diagram of the display device provided in the embodiments of this disclosure, such as... Figure 17 As shown, with Figures 13 to 15 The situation shown is different, in Figure 17 In the illustrated case, one end of the flexible circuit board 501 for texture recognition is electrically connected to the bonding electrode for texture recognition located in the peripheral area of ​​the texture recognition module 100, and the other end of the flexible circuit board 501 for texture recognition is electrically connected to the chip for texture recognition. Both the flexible circuit board 501 for texture recognition and the chip for texture recognition 502 are located in the receiving groove.

[0168] In some embodiments, the display panel 28 also has functional layers such as an encapsulation layer and a touch layer. These functional layers can be referred to in related technologies and will not be described in detail here.

[0169] The display device provided in this embodiment can be any product or component with texture recognition function, such as a mobile phone, tablet computer, monitor, or laptop computer. The embodiments disclosed herein do not specifically limit this.

[0170] Based on the same inventive communication, this disclosure also provides a method for preparing a texture recognition module, which can be used to prepare the texture recognition module provided in any of the preceding embodiments. Figure 18 This is a flowchart of a method for preparing a texture recognition module provided in this disclosure embodiment, as shown below. Figure 18 As shown, the fabrication method of this texture recognition module includes:

[0171] Step S1: Provide a substrate.

[0172] The substrate can be a glass substrate or a PI flexible substrate.

[0173] When the substrate is flexible, the glass substrate should first be cleaned and the surface moisture dried to remove surface stains; then, liquid PI should be coated on the glass, or the PI film should be directly hot-pressed onto the glass surface using a silane coupling agent.

[0174] Before step S2 begins and after step S1 ends, a certain thickness of SiNx or SiNx+SiO2 can be deposited on the clean PI surface as a third insulating layer to prevent water and oxygen from penetrating from the back of the PI after peeling, which would damage the device and optical film, and to facilitate the deposition of subsequent film layers. On the other hand, by adjusting the process conditions of SiNx or the SiNx / SiO2 ratio, the stress of the film layer can be changed, which can offset the stress of subsequent film layers, avoid stress accumulation, and prevent excessive stress after the flexible device is peeled off, which could cause spontaneous curling and lead to film layer breakage.

[0175] The substrate is divided into a texture recognition area and a surrounding area. The texture recognition area includes a photosensitive area.

[0176] Step S2: Form a photoelectric sensing structure on the substrate.

[0177] The photoelectric sensing structure is located on the substrate and within the texture recognition region, including: multiple gate lines, multiple signal sensing lines, and multiple pixel units defined by the multiple gate lines and multiple signal sensing lines; wherein, the pixel unit includes: a thin-film transistor, the gate of the thin-film transistor is electrically connected to the corresponding gate line, and the first electrode of the thin-film transistor is electrically connected to the corresponding signal sensing line; the texture recognition region includes: a photosensitive area, and the pixel unit located in the photosensitive area further includes: a photoelectric sensor, the photoelectric sensor including a third electrode, a photosensitive pattern, and a fourth electrode stacked sequentially along the direction away from the substrate, the third electrode being connected to the second electrode of the thin-film transistor located in the same pixel unit; the area ratio of the photoelectric sensor to the corresponding pixel unit is 40% to 90%.

[0178] In some embodiments, after forming the photoelectric sensing structure, the process may further include forming a bias trace (first / second light-shielding pattern), a collimation structure, an infrared filter layer, and other structural steps. For the specific fabrication steps of the photoelectric sensing structure, the bias trace collimation structure, the infrared filter layer, and other structures, please refer to the corresponding content in the previous embodiments, which will not be repeated here.

[0179] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A texture recognition module, comprising: The substrate includes a texture recognition area and a surrounding area located around the texture recognition area; A photoelectric sensing structure, located on the substrate and within the texture recognition area, includes: multiple gate lines, multiple signal sensing lines, and multiple pixel units defined by the intersection of the multiple gate lines and the multiple signal sensing lines. The pixel unit includes: a thin-film transistor, the gate of the thin-film transistor is electrically connected to the corresponding gate line, and the first electrode of the thin-film transistor is electrically connected to the corresponding signal sensing line. The texture recognition area includes a photosensitive area, and the pixel unit located in the photosensitive area further includes a photoelectric sensor. The photoelectric sensor includes a third electrode, a photosensitive pattern, and a fourth electrode stacked sequentially along the direction away from the substrate. The third electrode is connected to the second electrode of the thin-film transistor located in the same pixel unit. The area ratio of the photoelectric sensor to its corresponding pixel unit is 40% to 90%. The gate line extends along a first direction, and the signal sensing line extends along a second direction, wherein the first direction is perpendicular to the second direction; The thin-film transistor includes: a gate, an active layer, a first electrode, and a second electrode. The first electrode has a rectangular cross-section parallel to the plane of the substrate. The first electrode has a first side and a second side disposed opposite to each other in the first direction, and a third side and a fourth side disposed opposite to each other in the second direction. The first electrode is electrically connected to the signal sensing line closest to its first side. The gate is electrically connected to the gate line closest to the third side of the first electrode. The second electrode includes: a first conductive portion and a second conductive portion, wherein the first conductive portion extends along a first direction and is disposed opposite to a second side of the first electrode, and the second conductive portion extends along a second direction and is disposed opposite to a fourth side of the first electrode, and the first conductive portion and the second conductive portion are electrically connected. The second electrode further includes a third conductive portion, wherein the first conductive portion, the second conductive portion, and the third conductive portion are disposed in the same layer, the extension direction of the third conductive portion intersects both the first direction and the second direction, and the two ends of the third conductive portion are respectively connected to the first conductive portion and the second conductive portion.

2. The texture recognition module according to claim 1, wherein, The channel region of the thin-film transistor is inverted L-shaped or arc-shaped.

3. The texture recognition module according to claim 1, wherein, The orthographic projection of the photoelectric sensor on the substrate does not overlap with the orthographic projection of the active layer of the thin-film transistor on the substrate.

4. The texture recognition module according to any one of claims 1 to 3, wherein, The texture recognition area further includes a virtual area located around the photosensitive area, wherein the pixel units located in the virtual area are configured to output a reference noise signal to the corresponding signal sensing line.

5. The texture recognition module according to claim 4, wherein, A planarization layer and a passivation layer are sequentially disposed on the side of the photosensitive pattern facing away from the substrate. The fourth electrode is located on the side of the passivation layer facing away from the substrate and is electrically connected to the corresponding photosensitive pattern through vias on the planarization layer and the passivation layer. The pixel unit located in the virtual region further includes a fifth electrode and a sixth electrode. The fifth electrode is electrically connected to the second electrode of the thin-film transistor located in the virtual region. The planarization layer and the passivation layer are located between the fifth electrode and the sixth electrode.

6. The texture recognition module according to claim 5, wherein, A first insulating layer is formed on the side of the thin-film transistor away from the substrate, and the photosensitive sensor located in the photosensitive area is connected to the second electrode of the thin-film transistor through a via on the first insulating layer; A planarization layer and a passivation layer are sequentially disposed on the side of the photosensitive pattern facing away from the substrate. The fourth electrode is located on the side of the passivation layer facing away from the substrate and is electrically connected to the corresponding photosensitive pattern through vias on the planarization layer and the passivation layer. The pixel unit located in the virtual region further includes a fifth electrode and a sixth electrode. The fifth electrode is electrically connected to the second electrode of the thin-film transistor located in the virtual region. The fifth electrode and the third electrode are disposed in the same layer and with the same material. The sixth electrode and the fourth electrode are disposed in the same layer and with the same material. The fifth electrode and the sixth electrode include the first insulating layer, the planarization layer and the passivation layer.

7. The texture recognition module according to claim 5, wherein, The pixel unit located in the virtual area further includes a sensor reference structure, which includes a fifth electrode, a reference pattern, and a sixth electrode stacked sequentially along a direction away from the substrate. The fifth electrode is electrically connected to the second electrode of the thin-film transistor located in the virtual area. The fifth electrode and the third electrode are disposed in the same layer and with the same material. The sixth electrode and the fourth electrode are disposed in the same layer and with the same material. The material of the reference pattern is a non-photoelectric material and its dielectric constant is approximately the same as that of the photosensitive pattern.

8. The texture recognition module according to claim 5, wherein, Also includes: The first light-shielding pattern is located on the side of the sixth electrode away from the substrate, and the orthographic projection of the first light-shielding pattern on the substrate completely covers the virtual area but does not cover the photosensitive area.

9. The texture recognition module according to claim 4, wherein, The virtual area is located on one side of the photosensitive area.

10. The texture recognition module according to claim 4, wherein, The virtual area is located on opposite sides or intersecting sides of the photosensitive area.

11. The texture recognition module according to claim 4, wherein, The virtual area is located on the four sides of the photosensitive area.

12. The texture recognition module according to claim 4, wherein, The thin-film transistor contained in the pixel unit located in the photosensitive area has the same structure, shape, and size as the thin-film transistor contained in the pixel unit located in the virtual area.

13. The texture recognition module according to any one of claims 1 to 3, wherein, Also includes: A collimation structure is located on the side of the photoelectric sensing structure away from the substrate, and at least covers the photosensitive area; The collimation structure includes an aperture layer, which includes a plurality of light-transmitting holes arranged in an array.

14. The texture recognition module according to claim 13, wherein, The collimation structure further includes: a dielectric light-transmitting layer, a lens layer, and a planar light-transmitting layer, which are sequentially stacked on the side of the aperture layer away from the substrate and in a direction away from the substrate; The lens layer includes a plurality of convex lenses that correspond one-to-one with the light-transmitting holes, and the optical axis of the convex lenses passes through the corresponding light-transmitting holes.

15. The texture recognition module according to claim 14, wherein, The convex lens is a plano-convex lens, with its flat surface facing the light-transmitting medium and in contact with the surface of the light-transmitting medium, and its convex surface facing the light-transmitting medium and in contact with the surface of the light-transmitting medium.

16. The texture recognition module according to claim 13, wherein, One photoelectric sensor corresponds to multiple light-transmitting holes, and one light-transmitting hole corresponds to one photoelectric sensor.

17. The texture recognition module according to claim 16, wherein, The number of light-transmitting holes corresponding to each of the photoelectric sensors is the same; The number of light-transmitting holes corresponding to one of the photoelectric sensors ranges from 4 to 100.

18. The texture recognition module according to claim 13, wherein, Also includes: A non-visible light filter layer is located on the side of the photoelectric sensor away from the substrate and is configured to filter out non-visible light in the transmitted light.

19. The texture recognition module according to claim 18, wherein, The non-visible light filter layer includes an infrared filter layer configured to filter out infrared light from the transmitted light.

20. The texture recognition module according to claim 19, wherein, The infrared filter layer includes: an infrared absorption layer with infrared absorption function or an infrared reflection layer with infrared reflection function.

21. The texture recognition module according to claim 18, wherein, The non-visible light filter layer is located between the collimation structure and the photoelectric sensor.

22. The texture recognition module according to claim 18, wherein, The non-visible light filter layer is integrated within the collimation structure.

23. The texture recognition module according to claim 22, wherein, The non-visible light filter layer fills the light-transmitting hole.

24. The texture recognition module according to claim 22, wherein, The collimation structure includes: the aperture layer, the dielectric light-transmitting layer, the lens layer and the planar light-transmitting layer, which are sequentially stacked along the direction away from the substrate. The lens layer includes a plurality of convex lenses that correspond one-to-one with the light-transmitting apertures, and the optical axis of the convex lens passes through the corresponding light-transmitting aperture. At least one of the medium light-transmitting layer and the planar light-transmitting layer is reused as the non-visible light filter layer.

25. The texture recognition module according to any one of claims 1 to 3, wherein, The photoelectric sensing structure includes: a gate, a gate insulating layer, an active layer, a first conductive electrode layer, a first insulating layer, a photosensitive pattern, a planarization layer, a passivation layer, and a second conductive electrode layer, which are sequentially stacked along a direction away from the substrate, wherein the first light-shielding pattern is located on the side of the second conductive electrode layer away from the substrate; The first conductive electrode layer includes: the first electrode, the second electrode and the third electrode, and the second conductive electrode layer includes: the fourth electrode.

26. The texture recognition module according to claim 25, wherein, A second insulating layer is provided on the side of the fourth electrode away from the substrate. A bias trace is provided on the side of the second insulating layer away from the substrate and located in the peripheral region. The fourth electrode extends to the peripheral region and is electrically connected to the bias trace through a via on the second insulating layer.

27. The texture recognition module according to claim 26, wherein, The material of the bias trace includes a metallic material, and the first light-shielding pattern is set in the same layer and material as the bias trace.

28. The texture recognition module according to claim 27, wherein, Also includes: The second light-shielding pattern is set in the same layer and material as the offset trace; The orthographic projection of the second light-shielding pattern onto the substrate completely covers the orthographic projection of the channel region portion of the active layer within the thin-film transistor onto the substrate.

29. The texture recognition module according to claim 28, wherein, It also includes: a barrier layer located on the side of the second light-shielding pattern away from the substrate and a ground shielding layer located on the side of the barrier layer away from the substrate, wherein the orthogonal projection of the ground shielding layer on the substrate completely covers the texture recognition area.

30. The texture recognition module according to claim 29, wherein, The grounding shielding layer is electrically connected to the first light-shielding pattern and the second light-shielding pattern through a via on the barrier layer.

31. The texture recognition module according to any one of claims 1 to 3, wherein, The substrate is a flexible substrate, and a third insulating layer is disposed between the substrate and the photoelectric sensing structure.

32. A display device, wherein, include: The texture recognition module as described in any one of claims 1 to 31, and the display panel located on the side of the first light-shielding pattern away from the substrate.

33. The display device according to claim 32, wherein, The display panel and the texture recognition module are fixed together by optical adhesive; Alternatively, the display panel and the texture recognition module may be spaced apart.

34. The display device according to claim 32 or 33, wherein, The display panel is an OLED display panel, which includes an OLED display backplate, a polarizer, and a protective cover plate stacked sequentially along the direction away from the texture recognition module. The material of the protective cover plate includes polyimide.

35. The display device according to claim 32 or 33, wherein, Also includes: The middle frame includes a base plate and a side wall formed by bending the edge of the base plate towards the front side. The base plate and the side wall form a receiving groove. The texture recognition module and the display panel are fixed in the receiving groove. The display panel is located on the side of the texture recognition module away from the base plate.

36. The display device according to claim 35, wherein, The texture recognition module is fixed to the base plate.

37. The display device according to claim 35, wherein, A stepped support structure is formed on the side wall, and the display panel is fixed to the stepped support structure.

38. The display device according to claim 35, wherein, A through hole is formed on the base plate, and the display device further includes: a flexible circuit board for texture recognition and a chip for texture recognition; A flexible circuit board for texture recognition passes through the through hole, with one end electrically connected to a bonding electrode for texture recognition located in the peripheral area of ​​the texture recognition module, and the other end electrically connected to a texture recognition chip located on the back of the base plate.

39. The display device according to claim 35, wherein, The display device further includes: a flexible circuit board for texture recognition and a chip for texture recognition, one end of the flexible circuit board for texture recognition is electrically connected to a bonding electrode for texture recognition located in the peripheral area of ​​the texture recognition module, and the other end of the flexible circuit board for texture recognition is electrically connected to the chip for texture recognition. Both the flexible circuit board for texture recognition and the chip for texture recognition are located within the receiving slot.

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