Method for adding redundant transistor-like patterns and storage medium
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Patent Information
- Application Number
- CN202210597555.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-30
- Publication Date
- 2025-04-22
- Estimated Expiration
- 2042-05-30
AI Technical Summary
In the manufacturing process of integrated circuits, when the size of the addable region is not an integer multiple of the size sum of the transistor-like redundant graphics cells, the amount of adding transistor-like redundant graphics is limited, and sufficient redundant graphics cannot be achieved.
By splitting the transistor-like redundant graphics unit, we define the repeatable region and the stretchable region, and judge whether to copy and/or stretch according to the minimum distance from the unit distance to avoid the region boundary, and copy or stretch the relevant region in the direction of the transistor-like redundant graphics to increase the amount of redundant graphics.
The amount of redundant transistor-like graphics is added to make the layout distribution more uniform, reduces manufacturing defects in process manufacturing, and improves product yield and reliability.
Smart Images
Figure CN115081379B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a method for adding a quasi-transistor redundant pattern, and a computer-readable storage medium for executing the steps in the method for adding a quasi-transistor redundant pattern. Background Art
[0002] In the process of integrated circuit manufacturing, in order to improve the manufacturability of processes such as etching and grinding, it is usually necessary to add redundant graphics to areas with sparse graphic distribution after the layout design is completed to make the layout density distribution more uniform, thereby reducing manufacturing defects in the process manufacturing process and improving product yield and reliability.
[0003] With the continuous development of semiconductor technology nodes, especially 28nm and below, in order to improve the reliability of the front-end process, the structure of the front-end redundant graphics added has changed from a simple rectangle to a transistor-like shape. When the structure of the layout AA and POLY is similar to the redundant graphics structure added around it, the overall uniformity of the layout will be improved, thereby improving the process window of the relevant process manufacturing.
[0004] The transistor-like redundant pattern is a designed combination unit, and the redundant patterns of the entire unit are added together. When the size of the addable area is not an integer multiple of the sum of the size spacing of the transistor-like redundant pattern unit, the amount of transistor-like redundant patterns added is limited, and the addable area cannot achieve sufficient redundant pattern addition. Summary of the invention
[0005] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.
[0006] The technical problem to be solved by the present invention is to provide a method for adding transistor-like redundant graphics, which can increase the amount of transistor-like redundant graphics added and achieve more sufficient redundant graphics addition compared to the prior art when the size of the addable area is not an integer multiple of the sum of the size spacing of the transistor-like redundant graphics units.
[0007] The present invention also provides a computer-readable storage medium for executing the steps in the transistor-like redundant pattern adding method.
[0008] In order to solve the above technical problems, the present invention provides a method for adding a transistor-like redundant pattern, comprising the following steps:
[0009] S1, select the region where the redundant transistor-like pattern can be added;
[0010] S2, adding transistor-like redundant patterns in the addable area;
[0011] S3, splitting and defining transistor-like redundant graphic units to define repeatable regions and stretchable regions;
[0012] S4, judging whether to copy and / or stretch the transistor-like redundant graphic unit according to the minimum distance between the transistor-like redundant graphic unit and the boundary of the avoidance area;
[0013] S5, replicating a repeatable gate region along a first direction of the transistor-like redundant pattern;
[0014] and / or, stretching the stretchable gate region along the second direction of the transistor-like redundant pattern;
[0015] S6, merging the unprocessed transistor-like redundant pattern with the transistor-like redundant pattern after partial region replication and stretching;
[0016] The transistor-like redundant patterns include: five POLY redundant patterns arranged horizontally in parallel and two AA redundant patterns arranged vertically in parallel;
[0017] Among them, two AA redundant patterns arranged vertically in parallel overlap with three POLY redundant patterns in the middle, and the overlapped area of the AA redundant pattern and the POLY redundant pattern is a redundant pattern grid area.
[0018] Optionally, the first direction is a gate length direction, and the second direction is a gate width direction, the gate length is a POLY redundant pattern width, and the gate width is a AA redundant pattern height.
[0019] Optionally, in step S1, a region where a redundant pattern of a transistor can be added is selected through a redundant pattern-related hierarchical logic operation;
[0020] Optionally, step S3 includes:
[0021] Split the transistor-like redundant graphic unit along the gate length direction and split it into:
[0022] Left repeatable area A1: the area between the left side of the second POLY redundant pattern on the left and the left side of the third POLY redundant pattern on the left;
[0023] Right repeatable area A2: the area between the right side of the second POLY redundant pattern on the right and the right side of the third POLY redundant pattern on the right;
[0024] Left fixed area A3: the area between the left side of the first POLY redundant pattern on the left and the left side of the second POLY redundant pattern on the left;
[0025] Middle fixed area A4: the third POLY redundant pattern;
[0026] Right fixed area A5: the area between the right side of the first POLY redundant pattern on the right and the right side of the second POLY redundant pattern on the right;
[0027] The transistor-like redundant graphic unit is split along the gate width direction and is split into:
[0028] Lower stretchable area B1: the area between the upper and lower edges of the lower AA redundant pattern;
[0029] Upper stretchable area B2: an area between the upper and lower edges of the upper AA redundant pattern;
[0030] Lower fixed area B3: an area located between the lower side of the lower AA redundant pattern and the lower side of the transistor-like redundant pattern unit;
[0031] Middle fixed area B4: the area between two AA redundant patterns;
[0032] Upper fixed area B5: an area located between the upper edge of the upper AA redundant pattern and the upper edge of the transistor-like redundant pattern unit;
[0033] Among them, the width of the left repeatable area A1 is W1, the width of the right repeatable area A2 is W2, the width of the lower stretchable area B1 is W3, and the width of the upper stretchable area B2 is W4.
[0034] Optionally, step S4 includes:
[0035] Calculate the minimum distance L on the left side and the minimum distance R on the right side of each transistor-like redundant pattern along the gate length direction to avoid the region boundary, calculate L divided by W1 and rounded to get C1, and R divided by W2 and rounded to get C2;
[0036] Calculate the minimum distance T of the upper margin to avoid the region boundary and the minimum distance B of the lower margin to avoid the region boundary along the gate width direction of each type of transistor redundant pattern:
[0037] If the replicable attribute value C1=0 and C2=0 of each class transistor redundant pattern, the shape and position of the class transistor redundant pattern remain unchanged;
[0038] If the stretchable property value of each type of transistor redundant pattern is T=0 and B=0, the shape and position of the type of transistor redundant pattern remain unchanged.
[0039] Optionally, step S5 includes:
[0040] If the replicable attribute value C1>0 or C2>0 of each class transistor redundant pattern, the repeatable gate region is replicated along the gate length direction of the class transistor redundant pattern:
[0041] Region A4 of the transistor-like redundant pattern is fixed, region A1 is copied C1 times to the left based on the original position, region A3 is shifted to the left by C1*W1, region A2 is copied C2 times to the right based on the original position, and region A5 is shifted to the right by C2*W2.
[0042] Optionally, step S5 further includes:
[0043] If the stretchable property value T of each type of transistor redundant pattern is greater than 0 or greater than 0, the stretchable region is stretched along the gate width direction of the type of transistor redundant pattern:
[0044] When B-E1≥0, the region B3 of the transistor-like redundant pattern D1 is shifted downward by B, the width of the region B1 is stretched by E1 based on the original width, and then shifted downward by B, the region B4 is shifted downward by B-E1, the width of the region B2 is stretched by E2 based on the original width, and then shifted downward by B-E1, and the region B5 is shifted upward by T;
[0045] When B-E1<0, the region B3 of the transistor-like redundant pattern D1 is shifted downward by B, the width of region B1 is stretched by E1 based on the original width, and then shifted downward by B, the region B4 is shifted upward by the absolute value of B-E1, the width of region B2 is stretched by E2 based on the original width, and then shifted upward by the absolute value of B-E1, and the region B5 is shifted upward by T;
[0046] Among them, the stretch width E1 of the lower stretchable area B1 = (T+B)*W3 / (W3+W4); the stretch width E2 of the upper stretchable area B2 = (T+B)*W4 / (W3+W4).
[0047] The present invention provides a computer-readable storage medium for executing the steps in any one of the above-mentioned transistor-like redundant pattern adding methods.
[0048] Traditional methods of adding redundant transistor-like patterns include:
[0049] Step 1: Obtain the avoidance area of the transistor-like redundant pattern through logical operation of the relevant levels of the redundant pattern, thereby selecting the addable area of the transistor-like redundant pattern.
[0050] Step 2: Add redundant transistor-like graphics of complete cells in the addable area. Figure 1 As shown in FIG. 1 , the remaining addable area is smaller than the unit size spacing of the transistor-like redundant pattern, and the transistor-like redundant pattern of the complete unit cannot be added.
[0051] After adding, directly outputting the transistor-like redundant pattern is a traditional method of adding the transistor-like redundant pattern. The amount of redundant pattern added is limited, and the area that can be added cannot achieve sufficient redundant pattern addition.
[0052] The present invention provides a method for adding a transistor-like redundant pattern based on a traditional method. In the remaining addable area where a whole transistor-like redundant pattern unit cannot be added, the adjacent transistor-like redundant pattern is partially replicated and stretched so that the transistor-like redundant pattern can be added more fully in the addable area, thereby increasing the amount of redundant pattern added. Compared with the traditional method, the present invention can further increase the amount of transistor-like redundant pattern added, making the layout distribution more uniform, thereby reducing manufacturing defects in the process of manufacturing and improving product yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0053] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:
[0054] Figure 1 This is a schematic diagram of the transistor-like redundant graphics added by the traditional method.
[0055] Figure 2 It is a schematic diagram of the process of the present invention.
[0056] Figure 3 It is a schematic diagram of the redundant graphic structure of the transistor of the present invention.
[0057] Figure 4 It is a schematic diagram of splitting redundant transistors along the gate length direction.
[0058] Figure 5 and Figure 6 It is a schematic diagram of splitting redundant transistors along the gate width direction.
[0059] Figure 7 It is a schematic diagram of a transistor-like redundant pattern obtained by replicating a portion of the area in the gate length direction.
[0060] Figure 8 It is a schematic diagram of a transistor-like redundant pattern obtained by stretching part of the area in the gate width direction. DETAILED DESCRIPTION
[0061] The following is an explanation of the embodiments of the present invention by specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the general design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described here. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art. In addition, it should also be understood that although the terms "first", "second", etc. can be used here to describe different elements, parameters, components, regions, layers and / or parts, these elements, parameters, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or part from another element, parameter, component, region, layer or part.
[0062] First embodiment;
[0063] like Figure 2 As shown, the present invention provides a method for adding a transistor-like redundant pattern, comprising the following steps:
[0064] S1, select the region where the redundant transistor-like pattern can be added;
[0065] S2, adding transistor-like redundant patterns in the addable area;
[0066] S3, splitting and defining transistor-like redundant graphic units to define repeatable regions and stretchable regions;
[0067] S4, judging whether to copy and / or stretch the transistor-like redundant graphic unit according to the minimum distance between the transistor-like redundant graphic unit and the boundary of the avoidance area;
[0068] S5, replicating a repeatable gate region along the first direction of the transistor-like redundant pattern
[0069] and / or, stretching the stretchable gate region along the second direction of the transistor-like redundant pattern;
[0070] S6, merging the unprocessed transistor-like redundant pattern with the transistor-like redundant pattern after partial region replication and stretching;
[0071] refer to Figure 3As shown, the transistor-like redundant pattern includes: five POLY redundant patterns arranged horizontally in parallel and two AA redundant patterns arranged vertically in parallel;
[0072] Among them, two AA redundant patterns arranged vertically in parallel overlap with three POLY redundant patterns in the middle, and the overlapped area of the AA redundant pattern and the POLY redundant pattern is a redundant pattern grid area.
[0073] Second embodiment;
[0074] The present invention provides a method for adding a transistor-like redundant pattern, comprising the following steps:
[0075] S1, through the redundant pattern related hierarchical logic operation, select the area where the transistor-like redundant pattern can be added;
[0076] S2, adding transistor-like redundant patterns in the addable area;
[0077] S3, splitting and defining transistor-like redundant graphic units to define repeatable regions and stretchable regions;
[0078] refer to Figure 4 As shown, the transistor-like redundant graphic unit is split along the gate length direction and split into:
[0079] Left repeatable area A1: the area between the left side of the second POLY redundant pattern on the left and the left side of the third POLY redundant pattern on the left;
[0080] Right repeatable area A2: the area between the right side of the second POLY redundant pattern on the right and the right side of the third POLY redundant pattern on the right;
[0081] Left fixed area A3: the area between the left side of the first POLY redundant pattern on the left and the left side of the second POLY redundant pattern on the left;
[0082] Middle fixed area A4: the third POLY redundant pattern;
[0083] Right fixed area A5: the area between the right side of the first POLY redundant pattern on the right and the right side of the second POLY redundant pattern on the right;
[0084] refer to Figure 5 and Figure 6 As shown, the transistor-like redundant graphic unit is split along the gate width direction and split into:
[0085] Lower stretchable area B1: the area between the upper and lower edges of the lower AA redundant pattern;
[0086] Upper stretchable area B2: an area between the upper and lower edges of the upper AA redundant pattern;
[0087] Lower fixed area B3: an area located between the lower side of the lower AA redundant pattern and the lower side of the transistor-like redundant pattern unit;
[0088] Middle fixed area B4: the area between two AA redundant patterns;
[0089] Upper fixed area B5: an area located between the upper edge of the upper AA redundant pattern and the upper edge of the transistor-like redundant pattern unit;
[0090] The width of the left repeatable area A1 is W1, the width of the right repeatable area A2 is W2, the width of the lower stretchable area B1 is W3, and the width of the upper stretchable area B2 is W4;
[0091] S4, calculating the minimum distance L on the left side and the minimum distance R on the right side of each transistor-like redundant pattern along the gate length direction to avoid the region boundary, and calculating L divided by W1 to obtain C1, and R divided by W2 to obtain C2;
[0092] Calculate the minimum distance T of the upper margin to avoid the region boundary and the minimum distance B of the lower margin to avoid the region boundary along the gate width direction of each type of transistor redundant pattern:
[0093] If the replicable attribute value C1=0 and C2=0 of each class transistor redundant pattern, the shape and position of the class transistor redundant pattern remain unchanged;
[0094] If the stretchable property value of each transistor-like redundant pattern is T=0 and B=0, the shape and position of the transistor-like redundant pattern remain unchanged;
[0095] S5, reference Figure 7 As shown, a repeatable gate region is replicated along the gate length direction of the redundant pattern of the transistor class; if the replicable attribute value C1>0 or C2>0 of each redundant pattern of the transistor class, a repeatable gate region is replicated along the gate length direction of the redundant pattern of the transistor class:
[0096] The region A4 of the transistor-like redundant pattern is fixed, the region A1 is copied to the left by C1 duplicated regions A1 based on the original position, the region A3 is shifted to the left by C1*W1, the region A2 is copied to the right by C2 duplicated regions A2 based on the original position, and the region A5 is shifted to the right by C2*W2;
[0097] and / or, reference Figure 8 As shown, the stretchable gate region is stretched along the gate width direction of the redundant pattern of the transistor; if the stretchable attribute value T>0 or B>0 of each redundant pattern of the transistor, the stretchable region is stretched along the gate width direction of the redundant pattern of the transistor:
[0098] When B-E1≥0, the region B3 of the transistor-like redundant pattern D1 is shifted downward by B, the width of the region B1 is stretched by E1 based on the original width, and then shifted downward by B, the region B4 is shifted downward by B-E1, the width of the region B2 is stretched by E2 based on the original width, and then shifted downward by B-E1, and the region B5 is shifted upward by T;
[0099] When B-E1<0, the region B3 of the transistor-like redundant pattern D1 is shifted downward by B, the width of region B1 is stretched by E1 based on the original width, and then shifted downward by B, the region B4 is shifted upward by the absolute value of B-E1, the width of region B2 is stretched by E2 based on the original width, and then shifted upward by the absolute value of B-E1, and the region B5 is shifted upward by T;
[0100] Wherein, the stretch width E1 of the lower stretchable area B1 = (T+B)*W3 / (W3+W4); the stretch width E2 of the upper stretchable area B2 = (T+B)*W4 / (W3+W4);
[0101] S6, merging the unprocessed transistor-like redundant pattern with the transistor-like redundant pattern after partial region replication and stretching;
[0102] The transistor-like redundant patterns include: five POLY redundant patterns arranged horizontally in parallel and two AA redundant patterns arranged vertically in parallel;
[0103] Among them, two AA redundant patterns arranged vertically in parallel overlap with three POLY redundant patterns in the middle, and the overlapped area of the AA redundant pattern and the POLY redundant pattern is a redundant pattern grid area;
[0104] The gate length is the width of the POLY redundant pattern, and the gate width is the height of the AA redundant pattern.
[0105] Third embodiment
[0106] The present invention provides a computer-readable storage medium for executing the steps in the method for adding a quasi-transistor redundant pattern described in any one of the first embodiment or the second embodiment.
[0107] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.
[0108] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.
Claims
1. A method for adding a redundant transistor-like pattern, characterized in that: The following steps are involved: S1, select the region where the redundant transistor-like pattern can be added; S2, adding transistor-like redundant patterns in the addable area; S3, splitting and defining transistor-like redundant graphic units to define repeatable regions and stretchable regions; S4, judging whether to copy and / or stretch the transistor-like redundant graphic unit according to the minimum distance between the transistor-like redundant graphic unit and the boundary of the avoidance area; S5, replicating a repeatable gate region along a first direction of the transistor-like redundant pattern; and / or, stretching the stretchable gate region along the second direction of the transistor-like redundant pattern; S6, merging the unprocessed transistor-like redundant pattern with the transistor-like redundant pattern after partial region replication and stretching; The transistor-like redundant patterns include: five POLY redundant patterns arranged horizontally in parallel and two AA redundant patterns arranged vertically in parallel; Among them, two AA redundant patterns arranged vertically in parallel overlap with three POLY redundant patterns in the middle, and the overlapped area of the AA redundant pattern and the POLY redundant pattern is a redundant pattern grid area.
2. The method for adding a redundant transistor pattern as claimed in claim 1, characterized in that: The first direction is the gate length direction, and the second direction is the gate width direction. The gate length is the width of the POLY redundant pattern, and the gate width is the height of the AA redundant pattern.
3. The method for adding a redundant transistor-like pattern as claimed in claim 2, characterized in that: Step S1, selecting an addable region of a transistor-like redundant pattern through a redundant pattern-related hierarchical logic operation.
4. The method for adding a redundant transistor-like pattern as claimed in claim 3, characterized in that: Step S3 includes: Split the transistor-like redundant graphic unit along the gate length direction and split it into: Left repeatable area A1: the area between the left side of the second POLY redundant pattern on the left and the left side of the third POLY redundant pattern on the left; Right repeatable area A2: the area between the right side of the second POLY redundant pattern on the right and the right side of the third POLY redundant pattern on the right; Left fixed area A3: the area between the left side of the first POLY redundant pattern on the left and the left side of the second POLY redundant pattern on the left; Middle fixed area A4: the third POLY redundant pattern; Right fixed area A5: the area between the right side of the first POLY redundant pattern on the right and the right side of the second POLY redundant pattern on the right; The transistor-like redundant graphic unit is split along the gate width direction and is split into: Lower stretchable area B1: the area between the upper and lower edges of the lower AA redundant pattern; Upper stretchable area B2: an area between the upper and lower edges of the upper AA redundant pattern; Lower fixed area B3: an area located between the lower side of the lower AA redundant pattern and the lower side of the transistor-like redundant pattern unit; Middle fixed area B4: the area between two AA redundant patterns; Upper fixed area B5: an area located between the upper side of the upper AA redundant pattern and the upper side of the transistor-like redundant pattern unit; Among them, the width of the left repeatable area A1 is W1, the width of the right repeatable area A2 is W2, the width of the lower stretchable area B1 is W3, and the width of the upper stretchable area B2 is W4.
5. The method for adding a redundant transistor-like pattern as claimed in claim 4, characterized in that: Step S4 includes: Calculate the minimum distance L on the left side and the minimum distance R on the right side of each transistor-like redundant pattern along the gate length direction to avoid the region boundary, calculate L divided by W1 and rounded to get C1, and R divided by W2 and rounded to get C2; Calculate the minimum distance T of the upper margin to avoid the region boundary and the minimum distance B of the lower margin to avoid the region boundary along the gate width direction of each type of transistor redundant pattern: If the replicable attribute value C1=0 and C2=0 of each class transistor redundant pattern, the shape and position of the class transistor redundant pattern remain unchanged; If the stretchable property value of each type of transistor redundant pattern is T=0 and B=0, the shape and position of the type of transistor redundant pattern remain unchanged.
6. The method for adding a redundant transistor-like pattern as claimed in claim 5, characterized in that: Step S5 includes: If the replicable attribute value C1>0 or C2>0 of each class transistor redundant pattern, the repeatable gate region is replicated along the gate length direction of the class transistor redundant pattern: Region A4 of the transistor-like redundant pattern is fixed, region A1 is copied C1 times to the left based on the original position, region A3 is shifted to the left by C1*W1, region A2 is copied C2 times to the right based on the original position, and region A5 is shifted to the right by C2*W2.
7. The method for adding a redundant transistor-like pattern as claimed in claim 6, characterized in that: Step S5 also includes: If the stretchable property value T of each type of transistor redundant pattern is greater than 0 or greater than 0, the stretchable region is stretched along the gate width direction of the type of transistor redundant pattern: When B-E1≥0, the region B3 of the transistor-like redundant pattern D1 is shifted downward by B, the width of the region B1 is stretched by E1 based on the original width, and then shifted downward by B, the region B4 is shifted downward by B-E1, the width of the region B2 is stretched by E2 based on the original width, and then shifted downward by B-E1, and the region B5 is shifted upward by T; When B-E1<0, the region B3 of the transistor-like redundant pattern D1 is shifted downward by B, the width of region B1 is stretched by E1 based on the original width, and then shifted downward by B, the region B4 is shifted upward by the absolute value of B-E1, the width of region B2 is stretched by E2 based on the original width, and then shifted upward by the absolute value of B-E1, and the region B5 is shifted upward by T; Among them, the stretch width E1 of the lower stretchable area B1 = (T+B)*W3 / (W3+W4); the stretch width E2 of the upper stretchable area B2 = (T+B)*W4 / (W3+W4).
8. A computer-readable storage medium for executing the steps in the method for adding a redundant transistor-like pattern as claimed in any one of claims 1 to 7.
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