Memory device

Abstract

Embodiments provide a memory device capable of reducing leakage current. According to one embodiment, a memory device includes first wiring extending in a first direction and second wiring extending in a second direction. A memory cell is connected between the first wiring and the second wiring and includes a variable resistance memory element. A first drive circuit is provided to supply a voltage to the first wiring, and a second drive circuit is provided to supply a voltage to the second wiring. The first drive circuit applies a first voltage to a selected first wiring, and the second drive circuit applies a second voltage to a selected second wiring. A voltage between half of a sum of the first voltage and the second voltage and the second voltage is applied to an unselected first wiring, and a voltage between half of the sum of the first voltage and the second voltage and the first voltage is applied to an unselected second wiring.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2021-039536, filed March 11, 2021, and U.S. Patent Application No. 17 / 459467, filed August 27, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to storage devices. Background Technology

[0004] Memory devices that integrate variable resistance memory elements, such as magnetoresistive elements, onto a semiconductor substrate have been proposed. Summary of the Invention

[0005] The embodiment provides a storage device that can reduce leakage current.

[0006] Typically, according to one embodiment, a memory device includes a plurality of first wirings extending along a first direction and a plurality of second wirings extending along a second direction intersecting the first direction. A plurality of memory cells are respectively connected between the plurality of first wirings and the plurality of second wirings. Each memory cell includes a variable-resistance memory element. A first driving circuit is configured to provide a voltage to the plurality of first wirings. A second driving circuit is configured to provide a voltage to the plurality of second wirings. The first driving circuit applies a first voltage V1 to a selected first wiring connected to a selected memory cell. The second driving circuit applies a second voltage V2 (lower than the voltage V1) to a selected second wiring connected to the selected memory cell. The first driving circuit applies a voltage between (V1+V2) / 2 and V2 to unselected first wirings other than the selected first wirings. The second driving circuit applies a voltage between V1 and (V1+V2) / 2 to unselected second wirings other than the selected second wirings. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the overall schematic layout configuration of the storage device according to the first embodiment.

[0008] Figure 2A This is a perspective view schematically showing the memory cell array section of the memory device according to the first embodiment.

[0009] Figure 2B This is a perspective view schematically showing a modified example of the memory cell array section of the memory device according to the first embodiment.

[0010] Figure 3 is a cross-sectional view schematically showing a configuration of a magnetoresistive effect element in a memory device according to a first embodiment.

[0011] Figure 4 is a cross-sectional view schematically showing a configuration of a selector in a memory device according to the first embodiment.

[0012] Figure 5 is a graph schematically showing current-voltage (I-V) characteristics of a selector in a memory device according to the first embodiment.

[0013] Figure 6 is a graph showing aspects related to operation of a memory device according to the first embodiment.

[0014] Figure 7 is a graph showing aspects related to operation of a memory device according to the second embodiment and according to the third embodiment. DETAILED DESCRIPTION

[0015] Hereinafter, certain example embodiments will be described with reference to the accompanying drawings.

[0016] (First Embodiment)

[0017] Figure 1 is a block diagram showing an overall schematic configuration of a nonvolatile memory device according to the first embodiment. In the following description, a magnetic memory device is described as an example of the nonvolatile memory device, but the present disclosure is not limited thereto.

[0018] The magnetic memory device of the first embodiment includes a memory cell array section 100, a word line (WL) drive circuit 200 (also referred to as a first drive circuit 200), and a bit line (BL) drive circuit 300 (also referred to as a second drive circuit 300).

[0019] Figure 2A is a perspective view schematically showing a configuration of the memory cell array section 100.

[0020] The memory cell array section 100 is provided on a base region including a semiconductor substrate. The memory cell array section 100 includes a plurality of word lines 10 (first wiring lines 10), a plurality of bit lines 20 (second wiring lines 20) crossing the plurality of word lines 10. A plurality of memory cells 30 are located between the plurality of word lines 10 and the plurality of bit lines 20. Each memory cell 30 is located at an intersection (or a cross point) of a word line 10 and a bit line 20.

[0021] When write or read of data is performed on a certain memory cell 30, the word line 10 and the bit line 20 provide a predetermined signal to the memory cell 30. In the following description, the word line 10 and the bit line 20 are collectively referred to as a wiring line 10 / 20. Figure 2AIn the present embodiment, although the word line 10 is located on the lower layer side and the bit line 20 is located on the upper layer side, the word line 10 can be located on the upper layer side and the bit line 20 can be located on the lower layer side.

[0022] Each memory cell 30 includes a magnetoresistive effect element 40 (also referred to as a nonvolatile variable resistance memory element) and a selector 50 (also referred to as a switching element 50). The magnetoresistive effect element 40 and the selector 50 are connected in series between the word line 10 and the bit line 20.

[0023] In the present embodiment, although the word line 10 is located on the lower layer side and the bit line 20 is located on the upper layer side, the word line 10 can be located on the upper layer side and the bit line 20 can be located on the lower layer side. Figure 2A In the present embodiment, the magnetoresistive effect element 40 is located on the lower layer side and the selector 50 is located on the upper layer side, but as shown in the modified example of the present embodiment, in other embodiments, the magnetoresistive effect element 40 can also be located on the upper layer side and the selector 50 can be located on the lower layer side. Figure 2B

[0024] Figure 3 is a cross-sectional view schematically showing the configuration of the magnetoresistive effect element 40.

[0025] In the present embodiment, a magnetic tunnel junction (MTJ) element is used as the magnetoresistive effect element 40. The magnetoresistive effect element 40 includes a storage layer 41 (also referred to as a first magnetic layer), a reference layer 42 (also referred to as a second magnetic layer), and a tunnel barrier layer 43 (also referred to as a non-magnetic layer).

[0026] The storage layer 41 is a ferromagnetic layer having a variable magnetization direction. In this context, the variable magnetization direction of a layer refers to the ability of the magnetization direction of the layer to change when a predetermined write current or the like is applied across the layer. The storage layer 41 is formed of, for example, a CoFeB layer containing cobalt (Co), iron (Fe), and boron (B).

[0027] The reference layer 42 is a ferromagnetic layer having a fixed magnetization direction. In this context, the fixed magnetization direction of a layer refers to the ability of the magnetization direction of the layer to remain constant (fixed) even when a predetermined write current or the like is applied across the layer. For example, the reference layer 42 is formed of a CoFeB layer containing cobalt (Co), iron (Fe), and boron (B), or a superlattice layer containing cobalt (Co) and an element selected from the group of elements including platinum (Pt), nickel (Ni), and palladium (Pd).

[0028] The tunnel barrier layer 43 is an insulating layer provided between the storage layer 41 and the reference layer 42, and is formed of, for example, magnesium oxide (MgO).

[0029] ​When the magnetization direction of the storage layer 41 is parallel to the magnetization direction of the reference layer 42, the magnetoresistive effect element 40 is in a low resistance state (relatively low resistance). When the magnetization direction of the storage layer 41 is anti-parallel to the magnetization direction of the reference layer 42, the magnetoresistive effect element 40 is in a high resistance state (relatively high resistance). Thus, the magnetoresistive effect element 40 can store binary data according to its resistance state (the low resistance state and the high resistance state indicate respective binary values). The magnetoresistive effect element 40 can be set to the low resistance state or the high resistance state according to the direction of a write current applied thereto.

[0030] The magnetoresistive effect element 40 of the present embodiment is a spin transfer torque (STT) type magnetoresistive effect element, having perpendicular magnetization. That is, the magnetization direction of the storage layer 41 is orthogonal to the film surface of the storage layer 41. The magnetization direction of the reference layer 42 is orthogonal to the film surface of the reference layer 42.

[0031] Although Figure 3 The magnetoresistive effect element 40 illustrated has a bottom-free type structure in which the storage layer 41 is located on the lower layer side and the reference layer 42 is located on the upper layer side, but the present embodiment can instead use a magnetoresistive effect element having a top-free type structure in which the storage layer 41 is located on the upper layer side and the reference layer 42 is located on the lower layer side.

[0032] Figure 4 is a cross-sectional view schematically illustrating the configuration of the selector 50.

[0033] The selector 50 includes a lower electrode 51, an upper electrode 52, and a selector material layer 53 (also referred to as a switching material layer 53) provided between the lower electrode 51 and the upper electrode 52. The selector 50 is a two-terminal type switching element (switch) having a non-linear current-voltage characteristic. When the voltage applied between the two terminals is less than a threshold voltage, the selector 50 is in a high resistance state (e.g., in a non-conductive state). On the other hand, when the voltage applied between the two terminals is equal to or higher than the threshold voltage, the selector 50 is in a low resistance state (e.g., in a conductive state). By using a two-terminal type switching element having a linear current-voltage characteristic, substantially the same effect can also be obtained.

[0034] Figure 5 is a graph schematically illustrating an example of the current-voltage (I-V) characteristic of the selector 50. When the voltage between the two terminals of the selector 50 ramps up and reaches the threshold voltage Vth, the voltage between the two terminals drops to the holding voltage Vhold, and the current increases significantly.

[0035] The selector 50 is turned on (in a conductive state) by applying a voltage equal to or higher than a predetermined voltage between the first wiring 10 and the second wiring 20, so that a write or read can be performed on the magnetoresistive effect element 40 connected in series to the selector 50.

[0036] Next, the operation of the memory device according to the first embodiment will be described with reference to Figure 6 The write operation will be described here as an example operation.

[0037] When the write operation is performed, the word line drive circuit 200 supplies a predetermined voltage to the word line WL (which corresponds to the word line 10 in Figure 2A and 2B ), and the bit line drive circuit 300 supplies a predetermined voltage to the bit line BL (which corresponds to the bit line 20 in Figure 2A and 2B ).

[0038] Specifically, the word line drive circuit 200 applies a voltage VI to the selected word line WLS connected to the selected memory cell MCS. The bit line drive circuit 300 applies a voltage V2 (lower than the voltage VI) to the selected bit line BLS (selected bit line BLS) connected to the selected memory cell MCS.

[0039] The word line drive circuit 200 applies a voltage between (VI + V2) / 2 and V2 to the unselected word line WLN (word line WL other than the selected word line WLS). The bit line drive circuit 300 applies a voltage between VI and (VI + V2) / 2 to the unselected bit line BLN (bit line BL other than the selected bit line BLS).

[0040] More specifically, the word line drive circuit 200 applies a voltage (VI + V2) / 2 - Voffseta to the unselected word line WLN. The bit line drive circuit 300 applies a voltage (VI + V2) / 2 + Voffsetb to the unselected bit line BLN. However, in this context, Voffseta and Voffsetb are both positive values.

[0041] In this way, the voltage applied from the word line drive circuit 200 to the word line WL is set, and the voltage applied from the bit line drive circuit 300 to the bit line BL is set, so that the write operation can be performed in which the write voltage (or write current) is appropriately controlled.

[0042] Here, for simplicity of explanation, it is assumed that the voltage output from the word line drive circuit 200 is applied to the memory cell without voltage drop along the word line WL or the like, and it is assumed that the voltage output from the bit line drive circuit 300 is applied to the memory cell without voltage drop along the bit line BL or the like.

[0043] In the standard write operation, the voltage VI is applied to the selected word line WLS and the voltage V2 is applied to the selected bit line BLS in the same manner as in the case of the above-described embodiment. However, unlike the above-described embodiment, in the standard write operation, the voltage (VI + V2) / 2 is applied to both the unselected word line WLN and the unselected bit line BLN. Thus, in the standard write operation, a voltage of (VI - V2) is applied to the selected memory cell MCS connected between the selected word line WLS and the selected bit line BLS. A voltage of (VI - V2) / 2 is applied to the memory cells connected between the selected word line WLS and the unselected bit line BLN and to the memory cells connected between the unselected word line WLN and the selected bit line BLS. In the following description, these types of memory cells (memory cells connected to either the selected word line WLS or the selected bit line BLS but not to both the selected word line WLS and the selected bit line BLS) can be referred to as "half-selected memory cells" or partially selected memory cells.

[0044] As can be seen from the above description, in the standard write operation, 1 / 2 of the voltage applied to the selected memory cell is applied to the half-selected memory cells. Thus, a leakage current can flow in the half-selected memory cells, and proper write operation can be hindered.

[0045] On the other hand, in the first embodiment, a voltage of VI - {(VI + V2) / 2 + Voffsetb}, i.e., a voltage of (VI - V2) / 2 - Voffsetb is applied to the half-selected memory cell located between the selected word line WLS and the unselected bit line BLN. A voltage of {(VI + V2) / 2 - Voffseta} - V2, i.e., a voltage of (VI - V2) / 2 - Voffseta is applied to the half-selected memory cell located between the unselected word line WLN and the selected bit line BLS. Thus, in any case, a voltage lower than 1 / 2 of the voltage (VI - V2) applied to the selected memory cell will be applied to the half-selected memory cell.

[0046] As described above, in the first embodiment, the magnitude of the voltage applied to the half-selected memory cell can be reduced, and thus the leakage current flowing through the half-selected memory cell can be reduced. Thus, in the first embodiment, the leakage current can be better controlled, and thus the total current consumption can be reduced.

[0047] It is desirable that the voltage applied to the unselected word line WLN and the voltage applied to the unselected bit line BLN be set such that a voltage lower than 1 / 2 of the voltage (VI - V2) applied to the selected memory cell is also applied to the unselected memory cell connected between the unselected word line WLN and the unselected bit line BLN.

[0048] (Second Embodiment)

[0049] The basic matters of the second embodiment are the same as those of the first embodiment unless otherwise stated, and the description of matters already described in the first embodiment can be omitted.

[0050] Figure 7 is a diagram illustrating the operation of the memory device according to the second embodiment. The write operation will also be described as an example.

[0051] In the second embodiment, as with the first embodiment, the word line drive circuit 200 applies the voltage V1 to the selected word line WLS, and the bit line drive circuit 300 applies the voltage V2 (lower than the voltage V1) to the selected bit line BLS.

[0052] The word line drive circuit 200 also applies a voltage between (V1+V2) / 2 and V2 to the unselected word line WLN, and the bit line drive circuit 300 applies a voltage between V1 and (V1+V2) / 2 to the unselected bit line BLN.

[0053] More specifically, in the same manner as in the first embodiment, the word line drive circuit 200 applies the voltage (V1+V2) / 2-Voffseta to the unselected word line WLN, and the bit line drive circuit 300 applies the voltage (V1+V2) / 2+Voffsetb to the unselected bit line BLN.

[0054] While the value of Voffseta and the value of Voffsetb are fixed values in the first embodiment, in the second embodiment, the value of Voffseta is changed in accordance with the position of the unselected word line WLN (more specifically, the position of the word line WLN in the direction in which the word lines WL are spaced apart from each other), and the value of Voffsetb is changed in accordance with the position of the unselected bit line BLN (more specifically, the position of the bit line BLN in the direction in which the bit lines BL are spaced apart from each other). That is, in the second embodiment, the voltage applied to the unselected word line WLN is set in accordance with the position of the unselected word line WLN within the array, and the voltage applied to the unselected bit line BLN is set in accordance with the position of the unselected bit line BLN within the array.

[0055] In general, the value of Voffseta of the unselected word line WLN positioned farther from the bit line drive circuit 300 is set to be smaller than the value of Voffseta of the unselected word line WLN positioned closer to the bit line drive circuit 300. The value of Voffsetb of the unselected bit line BLN positioned farther from the word line drive circuit 200 is set to be smaller than the value of Voffsetb of the unselected bit line BLN positioned closer to the word line drive circuit 200.

[0056] Generally, the voltage output from the word line drive circuit 200 decreases as the distance from the word line drive circuit 200 increases due to the resistance of the word line WL and the like. That is, the amount of voltage drop due to the word line WL increases as the distance from the word line drive circuit 200 increases. Therefore, in the second embodiment, the value of Voffsetb decreases as the distance from the word line drive circuit 200 increases. Likewise, for the unselected word line WLN, the value of Voffseta decreases as the distance from the bit line drive circuit 300 increases.

[0057] With the voltage application operation of the second embodiment, the voltage applied to the semi-selected memory cells can be reduced and uniformized, and thus the leakage current of the semi-selected memory cells can be reduced and uniformized.

[0058] In Figure 7 In the example shown, the word lines WL are grouped into different groups. Specifically, the word lines WL are grouped into a first group consisting of the subarray regions Al l, A21, A31, A41, a second group consisting of the subarray regions A12, A22, A32, A42, a third group consisting of the subarray regions A13, A23, A33, A43, and a fourth group consisting of the subarray regions A14, A24, A34, A44. The voltage applied to the unselected word line WLN is a different value for each group of word lines WL.

[0059] In the same manner, the bit lines BL are grouped into different groups. Specifically, the bit lines BL are grouped into a first group consisting of the subarray regions Al l, A12, A13, A14, a second group consisting of the subarray regions A21, A22, A23, A24, a third group consisting of the subarray regions A31, A32, A33, A34, and a fourth group consisting of the subarray regions A41, A42, A43, A44. The voltage applied to the unselected bit line BLN is set to a different value for each group of bit lines BL.

[0060] More specifically, the value of Voffseta for the unselected word line WLN in a group of word lines WL that is far from the bit line drive circuit 300 is smaller than the value of Voffseta for the unselected word line WLN in a group of word lines WL that is close to the bit line drive circuit 300. The value of Voffsetb for the unselected bit line BLN in a group of bit lines BL that is far from the word line drive circuit 200 is smaller than the value of Voffsetb for the unselected bit line BLN in a group of bit lines BL that is close to the word line drive circuit 200.

[0061] In the second embodiment, a voltage lower than 1 / 2 of the voltage (V1-V2) applied to the selected memory cell is applied to the half-selected memory cell in the same manner as in the first embodiment. Therefore, in the second embodiment, the magnitude of the voltage applied to the half-selected memory cell can be reduced, and thus the leakage current flowing through the half-selected memory cell can be reduced. Therefore, the leakage current can be controlled better, and thus the total current consumption can be reduced.

[0062] In the second embodiment, the voltage applied to the unselected word line WLN is set in accordance with the position of the unselected word line WLN, and the voltage applied to the unselected bit line BLN is set in accordance with the position of the unselected bit line BLN. Therefore, the leakage current of the half-selected memory cell can be reduced and better uniformized.

[0063] (Third Embodiment)

[0064] The basic matters of the third embodiment are the same as those of the first embodiment unless otherwise specified, and the description of matters already described in the first embodiment can be omitted.

[0065] Figure 7 is also a view showing the operation of the memory device according to the third embodiment. In the third embodiment, a write operation will be described as an example operation.

[0066] In the third embodiment, the word line drive circuit 200 applies the voltage V1 to the selected word line WLS, and the bit line drive circuit 300 applies the voltage V2 (lower than the voltage V1) to the selected bit line BLS in the same manner as in the first embodiment.

[0067] The word line drive circuit 200 also applies a voltage between (V1+V2) / 2 and V2 to the unselected word line WLN, and the bit line drive circuit 300 applies a voltage between V1 and (V1+V2) / 2 to the unselected bit line BLN.

[0068] More specifically, the word line drive circuit 200 applies the voltage (V1+V2) / 2-Voffseta to the unselected word line WLN, and the bit line drive circuit 300 applies the voltage (V1+V2) / 2+Voffsetb to the unselected bit line BLN in the same manner as in the first embodiment.

[0069] In the first embodiment, although the voltage V1 applied to the selected word line WLS and the voltage V2 applied to the selected bit line BLS are both fixed values, in the third embodiment, the value of the voltage V1 and the value of the voltage V2 are changed (set) in accordance with the position of the selected memory cell MCS.

[0070] In the third embodiment, the voltage applied to the unselected word lines WLN and the voltage applied to the unselected bit lines BLN are also set in dependence on the location of the selected memory cell M CS. In essence, the voltage applied to the unselected word lines WLN is constant, irrespective of the location of the unselected word lines WLN within the array, and likewise, the voltage applied to the unselected bit lines BLN is constant, irrespective of the location of the unselected bit lines BLN within the array. However, the voltage applied to the unselected word lines WLN and the voltage applied to the unselected bit lines BLN do vary in dependence on the location of the selected memory cell M CS within the array, but the values are constant across the array region (i.e. the same Voffseta or Voffsetb is used for each unselected word line WLN or unselected bit line BLN, irrespective of the array location of the unselected word line WLN or unselected bit line BLN).

[0071] However, in some examples, the techniques of the second embodiment can be combined with the third embodiment, such that the voltage applied to the unselected word lines WLN and the voltage applied to the unselected bit lines BLN vary in dependence on the location of the unselected word lines WLN and the location of the unselected bit lines BLN, in addition to any variation associated with the variation set in dependence on the location of the selected memory cell M CS within the array.

[0072] In the third embodiment, the value of the voltage V1 is higher when the location of the selected memory cell M CS is further from the word line drive circuit 200 than when the selected memory cell M CS is closer to the word line drive circuit 200. Similarly, the value of the voltage V2 is lower when the location of the selected memory cell M CS is further from the bit line drive circuit 300 than when the location of the selected memory cell M CS is closer to the bit line drive circuit 300.

[0073] More specifically, the value of Voffseta is greater when the location of the selected memory cell M CS is further from the bit line drive circuit 300 than when the location of the selected memory cell M CS is closer to the bit line drive circuit 300. The value of Voffsetb is greater when the location of the selected memory cell M CS is further from the word line drive circuit 200 than when the location of the selected memory cell M CS is closer to the word line drive circuit 200.

[0074] Due to the resistance of the word line WL and the like, the voltage output from the word line driver circuit 200 decreases (drops) as the distance from the word line driver circuit 200 increases. The voltage drop amount increases as the distance from the word line driver circuit 200 to the selected memory cell M CS increases. Therefore, in the third embodiment, the voltage output from the selected word line driver circuit 200 to the selected word line WLS is higher than the voltage originally to be applied to the selected memory cell M CS from the selected word line WLS, in consideration of the voltage drop amount. That is, as the distance from the word line driver circuit 200 to the selected memory cell M CS increases, a higher voltage is output from the word line driver circuit 200 to the selected word line WLS. Therefore, a voltage corresponding to the voltage originally to be applied can be applied from the selected word line WLS to the selected memory cell M CS.

[0075] Likewise, as the distance from the bit line driver circuit 300 to the selected memory cell M CS increases, a lower voltage is output from the bit line driver circuit 300 to the selected bit line BLS. Therefore, a voltage corresponding to the voltage originally to be applied can be applied from the selected bit line BLS to the selected memory cell M CS.

[0076] As described above, in the third embodiment, the voltage applied from the word line driver circuit 200 to the selected word line WLS is higher than the voltage originally to be applied to the selected memory cell M CS from the selected word line WLS. Therefore, in the third embodiment, the value of Voffsetb is increased to prevent the voltage applied to the semi-selected memory cell from increasing. Since the voltage applied from the word line driver circuit 200 to the selected word line WLS changes depending on the position of the selected memory cell M CS, the value of Voffsetb also changes depending on the position of the selected memory cell M CS. That is, the voltage applied from the bit line driver circuit 300 to the unselected bit line BLN changes depending on the position of the selected memory cell M CS. The same applies to the voltage applied from the bit line driver circuit 300 to the selected bit line BLS and the voltage applied from the word line driver circuit 200 to the unselected word line WLN. By the above voltage application operation, the leakage current of the semi-selected memory cell can be reduced and better uniformized.

[0077] In Figure 7 In the example shown, the array region in which the memory cells are provided includes a plurality of subarray regions A11 to A44, and the voltage applied to the unselected word line WLN and the voltage applied to the unselected bit line BLN are set depending on the position of the selected memory cell M CS in the subarray regions A11 to A44.

[0078] Specifically, the value of Voffseta is larger when the selected memory cell MCS is located in a subarray region far from the bit line driver circuit 300 (for example, in one of the subarray regions A14, A24, A34, A44) than when the selected memory cell MCS is located in a subarray region close to the bit line driver circuit 300 (for example, in one of the subarray regions A11, A21, A31, A41). The value of Voffsetb is larger when the selected memory cell MCS is located in a subarray region far from the word line driver circuit 200 (for example, in one of the subarray regions A44, A43, A42, A41) than when the selected memory cell MCS is located in a subarray region close to the word line driver circuit 200 (for example, in one of the subarray regions A14, A13, A12, A11).

[0079] In addition, in the third embodiment, a voltage lower than 1 / 2 of the voltage (V1-V2) applied to the selected memory cell is applied to the semi-selected memory cell in the same manner as in the first embodiment. Thus, in the third embodiment, the magnitude of the voltage applied to the semi-selected memory cell can be reduced, and thus the leakage current flowing through the semi-selected memory cell can be reduced. Thus, the leakage current can be better controlled, and thus the total current consumption can be reduced.

[0080] In the third embodiment, the voltage applied to the unselected word line WLN and the voltage applied to the unselected bit line BLN are set in accordance with the position of the selected memory cell MCS, and thus the leakage current of the semi-selected memory cell can be reduced and better uniformized.

[0081] Although the write operation is described in the first to third embodiments, the same operation principle can also be applied to the read operation, and similar effects can be obtained.

[0082] In the first to third embodiments, the magnetoresistive element is a variable resistance memory element, but in other examples, other variable resistance memory element types, such as phase change memory (PCM) elements, etc., can also be used.

[0083] Although certain embodiments have been described herein, these embodiments are presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein can be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

[0084] Explanation of Reference Numerals

[0085] 10: word line (first wiring),

[0086] 20: bit line (second wiring),

[0087] 30: memory cell,

[0088] 40: magnetoresistive element,

[0089] 41: storage layer

[0090] 42: reference layer

[0091] 43: tunnel barrier layer,

[0092] 50: selector

[0093] 51: lower electrode

[0094] 52: upper electrode,

[0095] 53: selector material layer,

[0096] 100: memory cell array portion,

[0097] 200: word line drive circuit (first drive circuit),

[0098] 300: bit line drive circuit (second drive circuit).

Claims

1. A storage device, comprising: Multiple first wirings extending along a first direction; Multiple second wirings extending along a second direction intersecting the first direction; A plurality of memory cells are connected between the plurality of first wirings and the plurality of second wirings, each memory cell including a variable resistor memory element; A first driving circuit is used to provide voltage to the plurality of first wirings; as well as A second driving circuit is used to provide voltage to the plurality of second wirings, wherein The first driving circuit applies a first voltage to a selected first wiring connected to a selected memory cell. The second driving circuit applies a second voltage, lower than the first voltage, to a selected second wiring connected to the selected memory cell. The first driving circuit applies a third voltage to an unselected first wiring connected to a memory cell other than the selected memory cell, the third voltage being within the range of half the sum of the first voltage and the second voltage and the second voltage. The second driving circuit applies a fourth voltage to an unselected second wiring connected to a memory cell other than the selected memory cell, the fourth voltage being within a range between half the sum of the first voltage and the second voltage and the first voltage. The third voltage is set to half the sum of the first voltage and the second voltage minus a first offset voltage, the first offset voltage having a value Voffseta. The fourth voltage is set to half the sum of the first voltage and the second voltage plus a second offset voltage, the second offset voltage having a value Voffsetb, and The first offset voltage and the second offset voltage are positive values.

2. The storage device according to claim 1, wherein The third voltage is set based on the distance between the unselected first wiring and the second driving circuit, and The applied fourth voltage is set based on the distance between the unselected second wiring and the first drive circuit.

3. The storage device according to claim 1, wherein The value Voffseta of the first offset voltage of the unselected first wiring located away from the second drive circuit is less than the value Voffseta of the first offset voltage of the unselected first wiring located close to the second drive circuit. The value Voffsetb of the second offset voltage of the unselected second wiring located away from the first drive circuit is less than the value Voffsetb of the second offset voltage of the unselected second wiring located close to the first drive circuit.

4. The storage device according to claim 1, wherein The first wirings that are adjacent to each other in the second direction are grouped into different groups along the second direction. The voltage applied to unselected first wiring is different for each group of the first wiring. The second wirings adjacent to each other in the first direction are grouped into different groups along the first direction, and The voltage applied to the unselected second wiring is different for each group of the second wiring.

5. The storage device according to claim 4, wherein The value Voffseta of the unselected first wiring in the group of first wirings farther from the second drive circuit is less than the value Voffseta of the unselected first wiring in the group of first wirings closer to the second drive circuit. The value Voffsetb of the unselected second wiring in a set of second wirings away from the first driving circuit is less than the value Voffsetb of the unselected second wiring in a set of second wirings close to the first driving circuit.

6. The storage device according to claim 1, wherein The values ​​of the first voltage and the second voltage are set according to the location of the selected memory cell, and The third voltage and the fourth voltage are also set according to the location of the selected memory cell.

7. The storage device according to claim 6, wherein The value of the first voltage is higher when the selected memory cell is located further away from the first driving circuit compared to when the selected memory cell is close to the first driving circuit. The value of the second voltage is lower when the selected memory cell is located further away from the second driving circuit than when the selected memory cell is located close to the second driving circuit.

8. The storage device according to claim 7, wherein The value Voffseta is larger when the selected memory cell is located further away from the second driving circuit compared to when the selected memory cell is located close to the second driving circuit. The value Voffsetb is larger when the selected memory cell is located further away from the first driving circuit than when the selected memory cell is located close to the first driving circuit.

9. The storage device according to claim 1, wherein The first voltage and the second voltage are set according to the location of the selected memory cell. The array region containing the multiple memory cells is divided into multiple sub-array regions, and The third voltage and the fourth voltage are set according to the location of the subarray region where the selected memory cell is located.

10. The storage device according to claim 9, wherein The first voltage is higher when the selected memory cell is located further away from the first driving circuit compared to when the selected memory cell is close to the first driving circuit. The second voltage is lower when the selected memory cell is located further away from the second drive circuit than when the selected memory cell is located close to the second drive circuit.

11. The storage device according to claim 10, wherein The value Voffseta is larger when the subarray region containing the selected memory cell is closer to the second driving circuit than when the subarray region is farther away from the second driving circuit. The value Voffsetb is larger when the subarray region where the selected memory cell is located is close to the first driving circuit than when the subarray region is far from the first driving circuit.

12. The storage device according to claim 1, wherein the variable resistance storage element is a magnetoresistive element.

13. The memory device of claim 1, wherein each of the plurality of memory cells further comprises a switching element connected in series with the variable resistance memory element.

14. The storage device of claim 13, wherein each switching element is a two-terminal switching element having nonlinear current-voltage characteristics.

15. A storage device comprising: Multiple character lines are routed along the first direction; Multiple bitline wirings extending along a second direction intersecting the first direction; A plurality of memory cells are located between the plurality of word lines and the plurality of bit lines, each memory cell including a variable resistor memory element; A word line driving circuit, which provides voltage to the multiple word line wirings; as well as Bit line driving circuit, which is used to provide voltage to the multiple bit line wirings, wherein The word line driving circuit applies a first voltage to the selected word line connected to the selected memory cell. The bit line driving circuit applies a second voltage, lower than the first voltage, to the selected bit line connected to the selected memory cell. The word line driving circuit applies a third voltage to unselected word lines connected to memory bases other than the selected memory bases. This third voltage is within a range between half the sum of the first and second voltages and the second voltage. The bit line driving circuit applies a fourth voltage to the unselected bit lines connected to memory bases other than the selected memory bases. This fourth voltage is within a range between half the sum of the first and second voltages and the first voltage. The third voltage is set to half the sum of the first voltage and the second voltage minus a first offset voltage, the first offset voltage having a value Voffseta. The fourth voltage is set to half the sum of the first voltage and the second voltage plus a second offset voltage, the second offset voltage having a value Voffsetb, and The first offset voltage and the second offset voltage are positive values.

16. The storage device according to claim 15, wherein The third voltage is set based on the distance between the unselected word line and the bit line driving circuit in the second direction, and The applied fourth voltage is set based on the distance between the unselected positioning line and the word line driving circuit in the first direction.

17. The storage device according to claim 15, wherein The value Voffseta of the first offset voltage of the unselected word line located away from the bit line driving circuit is less than the value Voffseta of the first offset voltage of the unselected word line located near the bit line driving circuit, and The value Voffsetb of the second offset voltage of the unselected positioning line located away from the word line driving circuit is less than the value Voffsetb of the second offset voltage of the unselected positioning line located close to the word line driving circuit.

18. The memory device of claim 15, wherein the first voltage and the second voltage are set according to the location of the selected memory cell.

19. The storage device according to claim 18, wherein The first voltage is higher when the selected memory cell is located further away from the word line driving circuit compared to when the selected memory cell is located close to the word line driving circuit. The second voltage is lower when the selected memory cell is located further away from the bit line driving circuit than when the selected memory cell is located close to the bit line driving circuit.

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