Storage device with separate power supply capability

Abstract

A memory device includes a printed circuit board, memory chips, a first power module, and a second power module. The printed circuit board has a plurality of conductive layers; the memory chips are mounted on the printed circuit board, wherein the memory chips include at least a first number of memory chips and a second number of memory chips; the first power module is mounted on the printed circuit board and provides a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and the second power module is mounted on the printed circuit board and provides a second set of power supplies to the second number of memory chips through the plurality of conductive layers.

Description

TECHNICAL FIELD

[0001] The present application relates generally to storage technology, and more specifically to a memory device with separate power supply capabilities for powering different portions of memory chips of the memory device. BACKGROUND

[0002] A dual in-line memory module (DIMM) is a memory module that integrates multiple memory chips (i.e., memory dies, such as dynamic random access memory (DRAM) chips) on a substrate (e.g., a printed circuit board (PCB)), also known as a raw card. A DIMM can be divided into ranks. Each rank corresponds to a data width (e.g., 32 bits or 64 bits). Specifically, a rank refers to a group of memory chips that are connected in parallel so that the data width meets the requirements of a memory controller. As mentioned above, each rank can correspond to a data width of 32 bits or 64 bits, and a single memory chip can have a data width of 4 bits, 8 bits, or 16 bits, etc., so that multiple memory chips in parallel can form a data width of 32 bits or 64 bits. It can be understood that with the development of technology, the data width corresponding to each rank can also be higher. Generally speaking, one DIMM can include one or more ranks, for example, 4 ranks. When the DIMM is accessed, different ranks can be enabled so that the enabled ranks can be accessed by a chip select (CS) signal issued by a memory controller on the DIMM. A single rank DIMM creates a multi-bit (e.g., 64-bit) data block using the data of its memory chips. A two-rank DIMM contains two data blocks from two groups of memory chips on the DIMM.

[0003] In some cases, a DIMM can be overclocked or overdriven to operate at a higher operating frequency than its rated operating frequency, or at a higher supply voltage than its rated supply voltage, to achieve higher performance. However, since the chip dice produced during the manufacturing process of the DIMM generally follow a normal distribution, the speed of the overclocked operation can be limited by some memory chips. That is, although these memory chips can have different overclocking performance, it is necessary to ensure that each memory chip on the DIMM can operate normally at a higher operating frequency. Therefore, the memory chip with the worst overclocking performance on the DIMM can determine the overall overclocking capability of the DIMM.

[0004] Therefore, there is a need to further improve the existing memory device. SUMMARY

[0005] It is an object of the present application to provide a memory device with separate power supply capabilities for powering different portions of memory chips of the memory device.

[0006] In one aspect of the application, a memory device is provided. The memory device includes a printed circuit board, a plurality of memory chips, a first power module, and a second power module. The printed circuit board has a plurality of conductive layers. The plurality of memory chips are mounted on the printed circuit board, wherein the plurality of memory chips includes at least a first number of memory chips and a second number of memory chips. The first power module is mounted on the printed circuit board and provides a first set of power supplies to the first number of memory chips through the plurality of conductive layers. The second power module is mounted on the printed circuit board and provides a second set of power supplies to the second number of memory chips through the plurality of conductive layers.

[0007] In one embodiment, each of the first power module and the second power module includes a power management chip and a plurality of peripheral electronic components electrically connected to the power management chip.

[0008] In one embodiment, the memory device further includes a first channel and a second channel. The first channel is configured to couple the first number of memory chips to a host device external to the memory device. The second channel is configured to couple the second number of memory chips to the host device.

[0009] In one embodiment, each of the first channel and the second channel is a double data rate channel.

[0010] In one embodiment, each of the first number of memory chips and the second number of memory chips includes one Rank of memory chips.

[0011] In one embodiment, each of the first number of memory chips and the second number of memory chips includes at least two Ranks of memory chips.

[0012] In one embodiment, at least one of the first set of power supplies and the second set of power supplies is configurable to provide an adjustable power voltage or power current.

[0013] In one embodiment, the first set of power supplies is configurable to meet voltage or current requirements of the first number of memory chips.

[0014] In one embodiment, the second set of power supplies is configurable to meet voltage or current requirements of the second number of memory chips.

[0015] In one embodiment, the first power module and the second power module are disposed at two opposite ends of the printed circuit board, and each power module is adjacent to one of the first number of memory chips and the second number of memory chips.

[0016] In one embodiment, the first power module and the second power module are each disposed at a central portion of the printed circuit board, the central portion being between the first number of memory chips and the second number of memory chips.

[0017] In one embodiment, the memory device further includes a double data rate interface through which the memory chips are coupled to the host device.

[0018] In one embodiment, the memory chips are volatile memory chips.

[0019] In one embodiment, the memory device is a non-buffered dual inline memory module (UDIMM) or a small outline dual inline memory module (SODIMM).

[0020] The foregoing is a summary of the application and can be simplified, summarized and / or omitted details. Those skilled in the art will appreciate that this section is merely a summary of the application and is not intended to limit the scope of the application in any way. This brief description does not identify key or essential features of the claimed subject matter and is not intended to be used as an aid in determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0021] The foregoing and other features of the present application will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only some embodiments in accordance with the application and are not to be considered limiting of its scope, the application will be described with additional specificity and detail through the use of the accompanying drawings.

[0022] Figure 1 A memory device 100 having separate power supply capabilities according to one embodiment of the application is shown;

[0023] Figure 2 A memory device 200 having separate power supply capabilities according to another embodiment of the application is shown. DETAILED DESCRIPTION

[0024] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments can be utilized, and other changes can be made, without departing from the spirit or scope of the subject application. It will be appreciated that those skilled in the art will be able to devise numerous

[0025] Figure 1A memory device 100 having decoupled power supply capability is shown in accordance with one embodiment of the present application. The memory device 100 can be coupled to a host device, such as a central processing unit (CPU), via an interface 106 to exchange data therebetween. For example, the interface 106 of the memory device 100 can be plugged into a slot or socket of a motherboard on which the host device is also mounted. In certain embodiments, the memory device 100 can be a memory device compatible with JEDEC DDR SDRAM standards, including JEDEC DDR2, DDR3, DDR4, DDR5, or any other DDR standard, and accordingly, the interface 106 can be a DDR interface.

[0026] As shown in Figure 1 The memory device 100 includes a substrate, which can be a printed circuit board (PCB) 102 having a plurality of conductive layers laminated thereon. The memory device 100 includes memory chips 104 mounted on one or both sides of the PCB 102 for data storage purposes. In the embodiment shown, Figure 1 In some embodiments, the memory chips can be volatile memory chips, such as DRAM chips, and in some other embodiments, some or all of the memory chips can be hybrid memory chips that concurrently have both volatile memory chip(s) and non-volatile memory chip(s).

[0027] Based on the manner in which the memory chips are coupled to the interface 106 of the memory device 100 and the manner in which the memory chips are accessed by the host device, the memory chips can be divided into different sets. For a memory device compliant with the DDR4 standard, the memory chips on the memory device can be divided into two Ranks, and each Rank of memory chips can support a single 64-bit data width (without error checking and correction, ECC) or 72-bit data width (with ECC) during data access operations. The memory chips of the two Ranks can share the interface 106 and can be activated or deactivated by a chip select signal. For a memory device compliant with the DDR5 standard, for example Figure 1As shown in the storage device 100, the storage chips of the storage device 100 can be divided into two Ranks or four Ranks, and each Rank of storage chips can support a single 32-bit data width (without ECC) or 40-bit data width (with ECC) during data access operations. Further, the interface of the DDR5 storage device can include two channels, each coupled to one Rank or two Ranks of storage chips. Those skilled in the art can understand that more channels or more Ranks of storage chips can be integrated in a single memory device compatible with any future JEDEC DDR standard or other suitable memory standard.

[0028] Still referring to Figure 1 , the storage device 100 includes a first Rank of storage chips 104a and a second Rank of storage chips 104b. The interface 106 of the storage device 100 includes a first channel for accessing the first Rank of storage chips 104a, and a second channel for accessing the second Rank of storage chips 104b. A first power module 108a and a second power module 108b are mounted on the PCB 102 to provide power supply to the first Rank of storage chips 104a and the second Rank of storage chips 104b, respectively. In some embodiments, the first power module 108a and the second power module 108b can each include a power management chip and a plurality of peripheral electrical components, such as inductors, capacitors, or other components that are not desired to be integrated within the power management chip.

[0029] The first power module 108a and the second power module 108b can be coupled to the interface 106 to receive power supply and power control signals from the motherboard, and generate two sets of power supply that are further provided to the respective storage chips. The first power module 108a and the second power module 108b are separated from each other, and thus the two sets of power supply can be configured independently from each other, for example, according to the overclocking performance of the particular Rank of storage chips that receive the two sets of power supply.

[0030] In particular, the first power module 108a can be coupled to two or more power input pins of the first channel to receive a bulk input (e.g., 12V power supply input) voltage of a switching regulator integrated in the power management chip of the first power module 108a and management inputs of other components of the power management chip of the first power module 108a. Similarly, the second power module 108b can be coupled to two or more power input pins of the second channel. The first power module 108a and the second power module 108b can also be coupled to other input pins of the corresponding channels to receive respective input signals, which are not described herein again.

[0031] As previously mentioned, the first power module 108a can be coupled to the first Rank of memory chips 104a to provide a first set of power supplies to these memory chips. In some embodiments, the first set of power supplies can include low dropout (LDO) regulator outputs, switching regulator outputs, bias outputs, etc. For example, the LDO regulator outputs can be used as the VDD and VDDQ inputs for the first Rank of memory chips 104a. Similarly, the second power module 108b can be coupled to the second Rank of memory chips 104b to provide a second set of power supplies to the memory chips of this Rank.

[0032] In some embodiments, one or both of the first power module 108a and the second power module 108b can be configurable, e.g., the power modules 108a and / or 108b can be configured by adjusting the output configuration parameters (hereinafter referred to as "power parameters") stored in their respective power management chips. In one embodiment, the first power module 108a can be non-configurable, such that the first power module 108a can only provide a pre-set nominal voltage or current to the first Rank of memory chips 104a in view of the fact that the first Rank of memory chips 104a can have low overclocking performance. But the second power module 108b can be configurable, which can accommodate the second Rank of memory chips 104b that have relatively higher overclocking performance. In another embodiment, both power modules 108a and 108b can be configurable, although they can or can not provide the same power parameters to the two sets of power supplies. For example, if the second Rank of memory chips 104b has better overclocking performance, the LDO output voltages for the first set of power supplies can be set to 1.8V (for VDD) and 1.0V (for VDDQ), while the LDO output voltages for the second set of power supplies can be set to 1.9V (for VDD) and 1.1V (for VDDQ). For another example, if the second Rank of memory chips 104b has better overclocking performance, the maximum LDO output currents for the first set of power supplies can be set to 20mA (for 1.8V LDO output voltage) and 15mA (for 1.0V LDO output voltage), while the LDO output currents for the second set of power supplies can be set to 25mA (for 1.8V LDO output voltage) and 20mA (for 1.0V LDO output voltage). In other words, the voltage or current requirements of the memory chips of different Ranks can be met by changing the voltage or current output capabilities of the corresponding power modules (e.g., adjusting the output configuration parameters).

[0033] For more detailed information on the specifications, signaling protocols, and functions of the power management chips of the first power module 108a and the second power module 108b, reference can be made to JEDEC power management IC specification standards, such as JESD301-1 “PMIC50x0 Power Management IC Specification Rev. 1” published in June 2020 and JESD301-2 “PMIC5100 Power Management IC Specification” to be published, the entire contents of which are incorporated herein by reference. It can be appreciated that the storage device according to embodiments of the present application can be compatible with any future JEDEC power management IC standards.

[0034] Although Figure 1 The storage device 100 depicted in FIG. 1 includes only two ranks of storage chips, but in some embodiments of the present application, the storage device can include more ranks of storage chips, such as four ranks or even more ranks. For example, two ranks of storage chips can be coupled to a first channel of the interface of the storage device and powered by the first power module; other ranks of storage chips can be coupled to a second channel of the interface of the storage device and powered by the second power module. It can be readily appreciated by those skilled in the art that the number of ranks of storage chips coupled to a channel is merely exemplary and not limiting.

[0035] In some embodiments, the storage device 100 can include a test logger (not shown) coupled to one or both of the two power modules, or two test loggers coupled to or integrated within the power modules, respectively. For example, a first test logger can be coupled to the first power module 108a, while a second test logger can be coupled to the second power module 108b. An overdrive test can be performed on the first rank of storage chips 104a to determine the maximum power voltage or power current at which the first power module 108a can function properly. For example, during the overdrive test, the power voltage of the first rank of storage chips 104a can be adjusted from the rated power voltage to 150% or more of the rated power voltage. The test logger can monitor the performance of the first rank of storage chips 104a at the varying power voltage and record the highest power voltage before the first rank of storage chips 104a does not function properly. In this way, the power parameters of the first power module 108a can be configured for the first rank of storage chips 104a according to the highest power voltage recorded by the test logger as needed, such as during initialization or power-up of the storage device 100. Similar overdrive tests can be performed on the second rank of storage chips 104b, which will not be repeated here.

[0036] It can be appreciated that the increased power supply capability can enable the storage chips of the corresponding Rank to operate at a higher operating frequency, and thus the operating frequency of the storage chips of different Ranks can also be adjusted by the power voltage / current to improve their performance.

[0037] Although in the above embodiments, the power supply capability of certain storage chips is increased to obtain better data access performance, in some other embodiments, the power supply capability of certain storage chips can be decreased to reduce power consumption as long as the storage chips can operate normally. The power supply capability can be similarly decreased due to the separate power supply capability of the storage device.

[0038] In Figure 1 In the illustrated implementation, the first power module 108a and the second power module 108b are disposed at two opposite ends of the same side of the PCB 102, and each power module is adjacent to the storage chips of the Rank it powers. This layout of the first power module 108a and the second power module 108b on the PCB 102 can reduce interference and improve the wiring of the PCB. However, it can be appreciated that other layouts can also be employed.

[0039] Figure 2 A storage device 200 with separate power supply capabilities according to another embodiment of the present application is shown. As Figure 2 shown, the storage device 200 includes two power modules 208a and 208b for two groups of storage chips 204a and 204b. The power modules 208a and 208b are disposed at the central portion of the PCB 202 of the storage device 200, where the central portion of the PCB 202 of the storage device 200 is between the first group of storage chips 204a and the second group of storage chips 204b. In some other embodiments, one of the two power modules 208a and 208b can be disposed at one end of the PCB 202, and the other of the two power modules 208a and 208b can be disposed at the central portion of the PCB 202. In another alternative embodiment, one of the two power modules 208a and 208b can be disposed at one side of the PCB 202, and the other of the two power modules 208a and 208b can be disposed at the other side of the PCB 202. There is usually enough space in the PCB 202 for the placement and wiring of the power modules 208a and 208b.

[0040] In some embodiments, the storage device can be an unbuffered dual in-line memory module (UDIMM) or a small outline dual in-line memory module (SODIMM). These types of DIMMs typically do not require a central storage controller, such as a register clock driver (RCD), to be integrated on the DIMM, thereby allowing separate power modules to be provided for different groups of memory chips on the DIMM.

[0041] In addition, although both of the embodiments shown in Figure 1 and Figure 2 show two power modules for providing power to respective groups of memory chips on the printed circuit board of the storage device, it will be readily appreciated that any other number of power modules can be integrated on the printed circuit board of the storage device, e.g., three, four, six, eight or even more power modules can be provided. These different power modules can provide different groups of power supply to respective groups of memory chips.

[0042] It should be noted that although several modules or sub-modules of the storage device having separate power supply capabilities according to embodiments of the present application are described in the above description, this partitioning is merely exemplary and not mandatory. Indeed, features and functions of two or more modules described above can be embodied in one module according to embodiments of the present application. Conversely, features and functions of one module described above can be further partitioned into multiple modules.

[0043] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, the application and the appended claims. In the claims, the word "comprising" or "including" does not exclude other elements and steps than those listed in the claims and the word "a" or "an" preceding the usage of a noun does not exclude a plurality of those elements. In the practical application of the application, a part can perform the functions of several technical features cited in the claims. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A storage device, characterized by, The storage device comprises: a printed circuit board having a plurality of conductive layers; a plurality of memory chips mounted on the printed circuit board, wherein the plurality of memory chips comprises at least a first number of memory chips and a second number of memory chips; a first power module mounted on the printed circuit board and providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted on the printed circuit board and providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers; at least one of the first set of power supplies and the second set of power supplies is configurable to provide an adjustable power voltage or power current to meet voltage or current requirements of a corresponding one of the first number of memory chips and the second number of memory chips.

2. The storage device of claim 1, wherein, Each of the first power module and the second power module comprises a power management chip and a plurality of peripheral electronic components electrically connected to the power management chip.

3. The storage device of claim 1, wherein, The storage device further comprises: a first channel for coupling the first number of memory chips to a host device external to the storage device; and a second channel for coupling the second number of memory chips to the host device.

4. The storage device of claim 3, wherein, The first channel and the second channel are both double data rate channels.

5. The storage device of claim 1, wherein, The first number of memory chips and the second number of memory chips each comprise one Rank of memory chips.

6. The storage device of claim 1, wherein, The first number of memory chips and the second number of memory chips each comprise at least two Ranks of memory chips.

7. The storage device of claim 1, wherein, The first power module and the second power module are disposed at two opposite ends of the printed circuit board, and each power module is adjacent to one of the first number of memory chips and the second number of memory chips.

8. The storage device of claim 1, wherein, The first power module and the second power module are both disposed at a central portion of the printed circuit board, the central portion being between the first number of memory chips and the second number of memory chips.

9. The storage device of claim 1, wherein, The storage device further comprises a double data rate interface through which the plurality of memory chips is coupled to a host device.

10. The storage device of claim 1, wherein, The memory chips are volatile memory chips.

11. The storage device of claim 1, wherein, The storage device is a non-buffered dual in-line memory module (UDIMM) or a small outline dual in-line memory module (SODIMM).

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