Adaptive temperature compensation for memory devices

Abstract

Embodiments of the present disclosure relate to adaptive temperature compensation for memory devices. In one embodiment, a memory system receives a request to perform a memory access operation, the request identifying a memory cell in a segment of the memory system comprising at least a portion of a memory device. The system determines that an operating temperature of the memory device satisfies a threshold criterion. In response to determining that the operating temperature of the memory device satisfies the threshold criterion, the system determines a temperature compensation value corresponding to an access control voltage adjustment value specific to the segment of the memory system. The system adjusts an access control voltage applied to the memory cell during the memory access operation based on an amount represented by the temperature compensation value.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to adaptive temperature compensation for memory devices. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] According to embodiments of the present disclosure, a memory system is provided, the memory system comprising: a memory device; and a processing means operably coupled to the memory device to perform an operation comprising: receiving a request to perform a memory access operation, the request identifying memory cells in a segment of the memory system comprising at least a portion of the memory device; determining that an operating temperature of the memory device satisfies a threshold criterion; in response to determining that the operating temperature of the memory device satisfies the threshold criterion, determining a temperature compensation value corresponding to an access control voltage adjustment value specific to the segment of the memory system; and adjusting an access control voltage applied to the memory cells during the memory access operation based on an amount represented by the temperature compensation value.

[0004] According to embodiments of the present disclosure, a method is provided, the method comprising: receiving a request to perform a memory access operation, the request identifying memory cells in a segment of a memory system comprising at least a portion of a memory device; determining that a number of cross-temperature operations performed on the memory device satisfies a predetermined criterion; in response to determining that the number of cross-temperature operations performed on the memory device satisfies the predetermined criterion, determining a temperature compensation value corresponding to an access control voltage adjustment value specific to the segment of the memory system; and adjusting an access control voltage applied to the memory cells during the memory access operation based on an amount represented by the temperature compensation value.

[0005] According to embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, the instructions which, when executed by a processing device, cause the processing device to perform the following operations: receiving a request to perform a memory access operation, the request identifying memory cells in a segment of a memory system comprising at least a portion of the memory device; determining that the operating temperature of the memory device satisfies a threshold criterion; in response to determining that the operating temperature of the memory device satisfies the threshold criterion, determining a temperature compensation value corresponding to an access control voltage adjustment value specific to the segment of the memory system; and adjusting an access control voltage applied to the memory cells during the memory access operation based on an amount represented by the temperature compensation value. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart of an example method for calculating temperature compensation values ​​to adjust voltage levels according to some embodiments of the present disclosure.

[0009] Figure 3A This is a block diagram illustrating voltage distribution shift according to some embodiments of the present disclosure.

[0010] Figure 3B This is a block diagram illustrating voltage distribution shift according to some embodiments of the present disclosure.

[0011] Figure 4 This is a block diagram illustrating the process of tracking memory blocks programmed in a high or low temperature range according to some embodiments of the present disclosure.

[0012] Figure 5 This is a block diagram illustrating the process of scanning a memory block under cross-temperature conditions and calculating the average threshold voltage of the memory block according to some embodiments of the present disclosure.

[0013] Figure 6 This is a block diagram illustrating the process of adjusting temperature compensation values ​​according to some embodiments of the present disclosure.

[0014] Figure 7 This is a graph illustrating the calculation of temperature compensation values ​​according to some embodiments of this disclosure.

[0015] Figure 8 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0016] This disclosure relates to an adaptive temperature compensation scheme for a memory device in a memory subsystem. The memory subsystem can be a memory device, a memory module, or a combination of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0017] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. The logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0018] A memory system can store data in memory cells within a memory device contained within the memory system. Each memory cell can store one or more bits of binary data corresponding to data received from a host system. In one example, the memory device of the memory system may include a single-level cell (SLC) memory, where each memory cell of the SLC memory can be programmed with a single data bit. When a data bit is stored in the SLC memory, the range of possible voltage levels for the memory cell is divided into two ranges. For example, these two ranges may include a first threshold voltage range corresponding to the logic data value "1" and a second threshold voltage range corresponding to the logic data value "0".

[0019] Some storage systems may include high-density memory devices such as multi-level cell (MLC) memory, which are programmed by storing 2 bits, 3 bits, 4 bits, or more bits per memory cell. Data may be stored in the MLC memory based on a total voltage range divided into a certain number of distinct threshold voltage ranges for the memory cells. Each distinct threshold voltage range corresponds to a predetermined value of data stored in the memory cell.

[0020] One type of memory device includes memory cells configured as four-level cell (QLC) memory. In a QLC memory, each memory cell can store four data bits. For example, in a QLC memory, a memory cell can store four data bits (e.g., 1111, 0000, 1101, etc.) corresponding to data received from a host system. In a QLC memory, each bit of the memory cell is stored in a different part of the memory cell (hereinafter also referred to as a "page"). A QLC memory cell can have a total of four pages. For example, a memory cell can include a lower page (LP), a upper page (UP), an extra page (XP), and a top page (TP), where each page stores one data bit. In a QLC memory cell, each combination of the four bits can correspond to a different threshold voltage range (hereinafter also referred to as a "level"). For example, the first level of the memory cell can correspond to 1111, the second level can correspond to 0111, and so on. Because a QLC memory cell includes four data bits, there are a total of 16 possible combinations of four data bits. Therefore, the memory cells of a QLC memory can be programmed into one of 16 different levels.

[0021] Conventional memory systems can store multiple data bits in a single memory cell by mapping a bit sequence to each of the different voltage levels of the memory cell. For example, a specific logic data value (e.g., '1100') can be assigned to one voltage level, and another logic data value (e.g., '1010') can be assigned to another voltage level of the memory cell. Data can be stored in the memory cell by a programming operation that applies a sequence of programming pulses to the memory cell. The programming pulse sequence can be applied to the memory cell until a voltage level corresponding to the data value has been reached at the memory cell. After the memory cell has been programmed, data can be read from the memory cell by applying a read voltage within the appropriate threshold voltage range and translating the programmed voltage level at the memory cell.

[0022] In some cases, memory systems can operate in environments with varying temperatures (e.g., between 0 and 75 degrees Celsius). The temperature change between when data is written to a memory cell and when data is read from a memory cell can affect the voltage stored in the memory cell and the voltage read from the memory cell. This temperature change between writing data and reading data from a memory cell is known as the cross-temperature.

[0023] Cross-temperature conditions occur when a memory cell is programmed at a high temperature range (65-70°C) and read at a low temperature range (20-25°C), or when a memory cell is programmed at a low temperature range (20-25°C) and read at a high temperature range (65-70°C). For illustrative purposes, temperature ranges (20-25°C) and (65-70°C) are used, but other temperature ranges are also possible.

[0024] refer to Figure 3A For example, if a memory cell in a QLC memory is programmed at 70°C with a voltage level of 2V corresponding to the data value '0100', and the temperature changes to 25°C over time when the memory cell is read, then the apparent voltage level may have shifted to 2.15V. Depending on how the threshold voltage range (i.e., the level) is defined in the memory cell, the apparent read voltage may reflect different data values ​​(e.g., '0101'). This shift may cause an increase in the raw bit error rate (RBER), which may exceed the error correction capability of the underlying error correction code (ECC).

[0025] refer to Figure 3B For another example, if a memory cell in a QLC memory is programmed at 25°C with a voltage level of 2V corresponding to the data value '0100', and the temperature changes to 70°C over time when the memory cell is read, then the apparent voltage level may have shifted to 1.85V. Depending on how the threshold voltage range (i.e., the level) is defined in the memory cell, the apparent read voltage may reflect a different data value (e.g., '0011'). This shift may cause an increase in the raw bit error rate (RBER), which may exceed the error correction capability of the underlying error correction code (ECC).

[0026] The present disclosure addresses the above and other deficiencies by having a memory subsystem that compensates for temperature variations in the memory system at a specific granularity level (e.g., at each die layer). A semiconductor die is an individual segment of semiconductor material on which functional circuitry is fabricated. Each die may contain individual memory devices organized into multiple memory blocks, and multiple dies may exist within a single memory system. Depending on the manufacturing process, memory cells on a particular die may exhibit relatively similar behavior relative to voltage shifts in response to temperature changes. Generally, the voltage shift of one memory cell in response to a temperature change is likely to be more similar to the voltage shift of another cell on the same die than the voltage shift of memory cells on different dies.

[0027] Accordingly, in one embodiment, the memory system may determine an individual temperature compensation (“tempco”) value for each die in the memory system. The temperature compensation value can be calculated from the voltage level (threshold voltage) of a memory cell that experiences a temperature change between the time when the memory cell is read and the time when the memory cell is programmed. More accurate temperature compensation values ​​and read values ​​can be achieved by using the temperature compensation value calculated from the voltage level of the specific memory cell being read (i.e., the specific die holding the memory cell), rather than applying a universal compensation value to the entire memory system.

[0028] Therefore, the error rate in the memory system can be reduced, error correction codes can be used less frequently, and the overall performance of the memory system can be improved. (See below for more information.) Figure 1-7 Additional details on these temperature compensation techniques are provided.

[0029] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0030] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device that includes memory and processing power.

[0032] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0033] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0034] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0038] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0044] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0045] Memory subsystem 110 includes a temperature compensation component 113, which can be used to determine temperature compensation values ​​for memory system 110 at different granular levels (e.g., per-die temperature compensation values). Temperature compensation component 113 can further apply the temperature compensation values ​​during data access operations (e.g., read or write operations) on memory device 130 to account for voltage shifts attributable to temperature changes. In some embodiments, memory subsystem controller 115 includes at least a portion of temperature compensation component 113. In some embodiments, temperature compensation component 113 is part of host system 110, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of temperature compensation component 113 and is configured to perform the functionality described herein.

[0046] Temperature compensation component 113 determines a temperature compensation value for the die and applies the temperature compensation value during data access operations on the die of memory device 130. Further details regarding the operation of temperature compensation component 113 are described below.

[0047] Figure 2 This is a flowchart of an example method 200 for calculating a temperature compensation value to adjust a voltage level according to some embodiments of this disclosure. Method 200 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1 The temperature compensation component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0048] At operation 210, the processing logic receives a request to perform a memory access operation, the request identifying a memory cell in a segment of the memory system that includes at least a portion of the memory device.

[0049] The request to perform a memory access operation can be a programming (write) or reading request. A segment of the memory system can be contained in a semiconductor die on which a memory device with memory cells is fabricated. The memory cells can contain multiple levels of memory cells and are configured to store voltages at one of several voltage levels, each representing a different logic data value.

[0050] At operation 220, the processing logic determines that the operating temperature of the memory device meets the threshold criterion.

[0051] The threshold criterion may be an operating temperature within a high or low temperature range required for a cross-temperature condition to occur. In one embodiment, the threshold criterion may be a pre-configured static range, such as a high temperature range of 65-70 degrees Celsius and / or a low temperature range of 20-25 degrees Celsius. In one embodiment, the threshold criterion may be configured via a profile associated with each die of the memory device. A cross-temperature condition occurs when processing logic programs a block to a segment of the memory system within a first temperature range (high / low temperature range) and reads a page from the segment of the memory system within a second temperature range (low / high temperature range).

[0052] In one embodiment, the processing logic determines that a crossover temperature operation of the memory device has met a predetermined criterion. For example, a counter `sample_cnt` can be incremented to count the number of crossover temperature operations that have occurred. Figure 5 Further illustrated below. In one embodiment, if the number of cross-temperature operations exceeds a counter threshold, then a predetermined criterion is met. The counter threshold adjusts the frequency at which the temperature compensation value is recalculated, as further described below.

[0053] In one embodiment, the processing logic identifies a block that will be programmed within a first temperature range or a second temperature range. In response to the identification that a block will be programmed within the first or second temperature range, the processing logic stores the block identifier of the block to be programmed via a programming request. For example, if a block is programmed at a high temperature range (e.g., 70-75 degrees Celsius), the block identifier may be stored in a hot-write set that identifies blocks programmed at the high temperature range. If a block is programmed at a low temperature range (e.g., 20-25 degrees Celsius), the block identifier may be stored in a cold-write set that identifies blocks programmed at the low temperature range. In one embodiment, if a block is erased from the memory device or scheduled for garbage collection, the block identifier identifying the block may be removed from either the hot-write set or the cold-write set.

[0054] At operation 230, in response to determining that the operating temperature of the memory device meets a threshold criterion, the processing logic determines a temperature compensation value corresponding to the access control voltage adjustment value specific to the memory system segment. In one embodiment, a counter sample_cnt satisfying a predetermined condition (e.g., sample_cnt > 1000) can be used to trigger a recalculation of the temperature compensation value. The access control voltage can be a voltage applied to read the stored voltage level. In another embodiment, the temperature compensation value can be used to compensate for (offset) the voltage level when reading a memory cell.

[0055] For example, if the operating temperature of the memory device is in a low (20-25 degrees Celsius) temperature range, then the processing logic scans memory blocks in the hot write set and cold write set. The hot write set and cold write set can be array data structures used to store memory block identifiers that identify when the block is programmed when the operating temperature is in a high or low temperature range. These sets of memory blocks can be used to calculate the average threshold voltage corresponding to each of the sets for the low operating temperature range, such as in... Figure 5 Further description is provided below. For example, a first average voltage threshold (level) (CT_CT_ave) is calculated, which corresponds to a block programmed and read at a low temperature range. A second average voltage threshold (HT_CT_ave) is calculated, which corresponds to a block programmed at a high temperature range and read at a low temperature range. HT_CT_ave and / or CT_CT_ave can be calculated by measuring the threshold voltage or threshold voltage shift of a random sample of memory cells in the block. For example, HT_CT_ave can be calculated using samples of memory cells from a memory block identified by a hot-write set. Memory cells can be read by shifting against the programming level, probing random memory cells against the threshold voltage level, such as... Figures 3A-3B Further explanation is provided below.

[0056] In one embodiment, if the operating temperature of the memory device is in a high (65-70 degrees Celsius) temperature range, then the logic scans the hot write set and the cold write set to calculate an average threshold voltage corresponding to each of the sets. For example, a third average threshold voltage (level) (CT_HT_ave) is calculated, corresponding to a block programmed at a low temperature range and read at a high temperature range. A fourth average threshold voltage (HT_HT_ave) can be calculated, corresponding to a block programmed at a high temperature range and read at a high temperature range. HT_HT_ave and / or CT_HT_ave can be calculated by measuring the threshold voltage or threshold voltage shift of a random sample of memory cells in the block.

[0057] In one embodiment, the processing logic counts the number of blocks used in the sampling. When the sampling count reaches a predetermined threshold (e.g., 1000), the processing logic uses HT_CT_ave, CT_CT_ave, HT_HT_ave, and CT_HT_ave to calculate temperature compensation values ​​for the high and low temperature ranges. Figure 7 The calculation of the temperature compensation value is further explained below.

[0058] At operation 240, the processing logic adjusts the access control voltage applied to the memory cell during memory access operations based on the amount represented by the temperature compensation value.

[0059] The control voltage of the memory cell can be linearly related to a temperature compensation value and can be adjusted linearly relative to the temperature compensation value. In another embodiment, the temperature compensation value can be used to offset the read voltage level.

[0060] Figure 3A This is a block diagram illustrating voltage distribution shifting according to some embodiments of the present disclosure. For example... Figure 3A As shown above, voltage distribution 300 illustrates two levels, '0100' and '0101', in a 16-level QLC memory cell storing four data bits. The memory cell can be programmed to store the logic data value '0100' corresponding to distribution 301 at a high temperature range by applying a programming pulse sequence to the memory cell until the programming voltage level reaches a value range within distribution 301. As the temperature associated with the memory cell changes over time to a lower temperature range (e.g., during the time interval between programming and reading the memory cell), the programming voltage level (or apparent read voltage) can be affected, and the programming voltage level associated with distribution 301 shifts to distribution 303. Because distribution 303 is within the range of distribution (distribution 305) associated with the logic state value '0101', there is a possibility of read errors. For example, read voltage level 309 could be decoded to correspond to logic state '0101' instead of '0100'.

[0061] Figure 3B This is a block diagram illustrating voltage distribution shifting according to some embodiments of the present disclosure. For example... Figure 3B The above illustrates voltage distribution 330 for two levels, '0100' and '0011', in a 16-level QLC memory cell storing four data bits. The memory cell can be programmed to store the logic data value '0100' corresponding to distribution 331 at a low temperature range by applying a programming pulse sequence to the memory cell until the programming voltage level reaches a value range within distribution 331. As the temperature associated with the memory cell changes over time to a higher temperature range (e.g., during the time interval between programming and reading the memory cell), the programming voltage level (or apparent read voltage) can be affected, and the programming voltage level associated with distribution 331 shifts to distribution 333. Because distribution 333 is within the range of distribution (distribution 335) associated with the logic state value '0011', there is a possibility of read errors. For example, read voltage level 339 could be decoded to correspond to logic state '0011' instead of '0100'.

[0062] Figure 4This is a block diagram illustrating a process for tracking a programmed memory block under high or low temperature ranges according to some embodiments of the present disclosure. Process 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, process 400 is performed by… Figure 1 Temperature compensation component 113 is executed.

[0063] At operation 401, the processing logic determines that data is programmed into a memory block in memory device 130. This programming can be performed in response to a request from host system 120 to store data in memory device 130.

[0064] At operation 403, the processing logic measures the temperature of the memory device 130. For example, temperature measurements may be obtained from one or more temperature sensors located in and around the memory device 130 and / or from other temperature sensors associated with other components of the memory subsystem 110 (e.g., controller 115). The temperature compensation component 113 may obtain temperature measurements from one or more temperature sensors to determine whether the memory subsystem 110 is operating in a high temperature range (65-70 degrees Celsius) or a low temperature range (20-25 degrees Celsius). In some embodiments, the temperature sensors may be configured to periodically measure the temperature of the memory device 130 at predefined time intervals and provide the measured temperature to the temperature compensation component 113. In some embodiments, the temperature sensors may measure the temperature in response to one or more commands (e.g., a command to measure temperature) that may be sent by the memory subsystem controller 115. Depending on the embodiment, the measured temperature may include at least one of the temperature of the semiconductor die on which the memory device 130 is manufactured, the operating temperature of the memory subsystem 110 (e.g., obtained from the memory subsystem controller 115), or the ambient temperature of the region in which the memory subsystem 110 is located.

[0065] At operation 405, the processing logic determines whether the measured temperature falls within the lower temperature range. The lower temperature range can be 20-25 degrees Celsius, or any other temperature range below the higher temperature range.

[0066] At operation 407, if the temperature range is in the low temperature range, the processing logic adds the block identifier of the programmed block to the cold write sample set. The cold write sample set may contain a list of block identifiers that identify blocks programmed in the low temperature range.

[0067] At operation 409, if the temperature range is not within the low temperature range, the processing logic determines whether the measured temperature is within the high temperature range. The high temperature range can be 65-70 degrees Celsius, or any other temperature range. If the measured temperature is outside the high or low temperature range, the processing logic returns to operation 401.

[0068] At operation 411, if the temperature range is in the high temperature range, the processing logic adds the block identifier of the programmed block to the hot-write sample set. The hot-write sample set may contain a list of block identifiers that identify blocks programmed in the high temperature range.

[0069] Cold and / or hot write sample sets can be used to evaluate, for example, cross-temperature conditions that occur when a block is programmed at a first (low / high) temperature range and read at a second (high / low) temperature range. In one embodiment, if a block is erased or scheduled for garbage collection, the corresponding block identifier can be removed from the cold and / or hot write sample set.

[0070] Figure 5 This is a block diagram illustrating a process of scanning a memory block under cross-temperature conditions and calculating the average threshold voltage of the memory block according to some embodiments of the present disclosure. Process 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, process 500 is performed by… Figure 1 Temperature compensation component 113 is executed.

[0071] At operation 501, the temperature of the logic measurement temperature compensation component 113 is processed. For example, temperature measurements may be obtained from one or more temperature sensors located in and around the memory device 130 and / or from other temperature sensors associated with other components of the memory subsystem 110 (e.g., controller 115).

[0072] At operation 503, the processing logic determines whether the temperature is within the low temperature range. The temperature compensation component 113 can obtain temperature measurements from one or more temperature sensors to determine whether the memory subsystem 110 is operating between 20 and 25 degrees Celsius.

[0073] At operation 505, if the temperature range is in the low temperature range, the processing logic can scan blocks in both the hot write set and the cold write set. This block scan involves randomly sampling a predetermined number of memory cells from blocks in both sets to determine the voltage shift of their read voltage at the current operating temperature. The voltage shift of the block can be determined by obtaining the read voltage of the memory cells through random samples of the control voltage applied to them. For the corresponding logic value stored in the memory cell, the read voltage can be compared with the desired programming voltage (e.g., the center of the voltage distribution is...). Figures 3A-3B The expected programming voltage of the logic state in the memory cell (the shifted average of the memory cell) can be used as the shift of the memory block. From the shifts of different memory blocks in the hot write set, the processing logic determines the average voltage shift of these memory blocks for cold reads, such as HT_CT_ave. From the shifts of different memory blocks in the cold write set, the processing logic determines the average voltage shift of these memory blocks for cold reads, such as CT_CT_ave. Next, the counter sample_cnt can be incremented, where the counter can be used to trigger tempco to be recalculated, such as Figure 6 Further explanation follows. In one embodiment, the counter identifies the number of blocks being sampled. In another embodiment, the counter identifies the number of times the low / high temperature range is used to scan the hot / cold write set, or the number of times cross-temperature conditions occur.

[0074] At operation 507, the processing logic determines whether the temperature is within the high temperature range.

[0075] At operation 509, if the temperature range is in the high temperature range, the processing logic can scan blocks in both the hot write set and the cold write set. This block scan involves randomly sampling a predetermined number of memory cells from blocks in both sets to determine the voltage shift of their read voltage at the current operating temperature. The voltage shift of the block can be determined by obtaining the read voltage of the memory cells through random samples of the control voltage applied to them. For the corresponding logic value stored in the memory cell, the read voltage can be compared with the desired programming voltage (e.g., the center of the voltage distribution is...). Figures 3A-3B The expected programming voltage of the logic state in the memory cell (the shifted average of the memory cell) can be used as the shift of the memory block. From the shifts of different memory blocks in the hot write set, the processing logic determines the average voltage shift of these memory blocks for hot read, such as HT_HT_ave. From the shifts of different memory blocks in the cold write set, the processing logic determines the average voltage shift of these memory blocks for hot read, such as CT_HT_ave. Next, the counter sample_cnt can be incremented, where the counter can be used to trigger tempco to be recalculated, such as Figure 6Further explanation follows. In one embodiment, the counter identifies the number of blocks being sampled. In another embodiment, the counter identifies the number of times the low / high temperature range is used to scan the hot / cold write set, or the number of times cross-temperature conditions occur.

[0076] Figure 6 This is a block diagram illustrating a process for adjusting a temperature compensation value according to some embodiments of the present disclosure. Process 550 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, process 550 is performed by… Figure 1 Temperature compensation component 113 is executed.

[0077] At operation 551, the processing logic determines whether the counter sample_cnt meets a threshold criterion. In one embodiment, the threshold criterion is met if the value of the counter is greater than or equal to a predetermined threshold (sample_threshold). In one embodiment, sample_threshold can be 1000 or any other value.

[0078] At operation 553, if the processing logic determines that the counter sample_cnt meets the threshold criterion, then the processing logic adjusts the temperature compensation value tempco, as follows. Figure 7 Further details are provided, and the counter sample_cnt is reset.

[0079] Figure 7 This is a graph illustrating the calculation of temperature compensation values ​​according to some embodiments of this disclosure. (See reference) Figure 7 Figure 700 shows a voltage versus temperature curve. From this graph, four points corresponding to the values ​​HT_CT_ave, CT_CT_ave, CT_HT_ave, and HT_HT_ave can be plotted. These four points can be plotted at (0,y1), (0,y2), (xt,y3), and (xt,y4), respectively. Given an incremental temperature xt = 67.5 - 22.5 = 45 degrees Celsius, which lies between the midpoint of the high temperature range (67.5 degrees Celsius) and the midpoint of the low temperature range (22.5 degrees Celsius), these four points can be plotted on Figure 700.

[0080] The slopes m1 and m2 can be determined from the following formula:

[0081]

[0082]

[0083] The intersection point (x, y) can be determined using the following formula:

[0084]

[0085] y = m1*x + y1

[0086] Furthermore, the temperature compensation value (“tempco”) can be determined as follows:

[0087]

[0088] The calculated temperature compensation value can be stored in an 8-bit register, which is part of the temperature compensation component 113. In one embodiment, each die in the memory device 130 may have a corresponding temperature compensation value. In one embodiment, the read voltage level of the memory cell in the die of the memory device 130 may be adjusted (or compensated) according to the temperature compensation value of the die.

[0089] In one embodiment, the processing logic can use the identified temperature compensation value to adjust the access control voltage of the memory cell on the die to a specific voltage level represented by the temperature compensation value. This adjustment of the access control voltage can take into account any voltage shift attributable to the temperature difference between programming and reading operations of the memory cell.

[0090] Figure 8 An example machine is described as a computer system 600, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 600 may correspond to including, coupled to, or using a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations related to...). Figure 1 The host system (e.g., the operation corresponding to the temperature compensation component 113) Figure 1 (Host system 120). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0091] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0092] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0093] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 to perform the operations and steps discussed herein. Computer system 600 may additionally include a network interface device 608 for communication on network 620.

[0094] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more instruction sets 626 or software embodying any or more of the methods or functions described herein are stored. Instructions 626 may also reside wholly or at least partially in main memory 604 and / or processing device 602 during execution by computer system 600, the main memory 604 and processing device 602 also constituting machine-readable storage medium. Machine-readable storage medium 624, data storage system 618 and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0095] In one embodiment, instruction 626 includes implementing a temperature compensation component (e.g., Figure 1The temperature compensation component 113) contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0096] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0097] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0098] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0099] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0100] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0101] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory system comprising: Memory devices; and A processing device operatively coupled to the memory device to perform operations including the following: Receive a request to perform a memory access operation, the request identifying a memory cell in a segment of the memory system that includes at least a portion of the memory device; Determine that the operating temperature of the memory device meets the threshold criterion; In response to determining that the operating temperature of the memory device satisfies the threshold criterion, a temperature compensation value is determined corresponding to an access control voltage adjustment value specific to the memory system segment, wherein the temperature compensation value is determined based on multiple average voltage thresholds of blocks programmed and read at multiple temperature ranges. and Based on the amount represented by the temperature compensation value, the access control voltage applied to the memory cell during the memory access operation is adjusted.

2. The memory system of claim 1, wherein the segment of the memory system comprises a semiconductor die on which the memory device having the memory cells is fabricated.

3. The memory system of claim 1, wherein determining that the operating temperature of the memory device satisfies the threshold criterion comprises determining the occurrence of a cross-temperature condition caused by programming a block into the segment of the memory system in a first temperature range and reading a page from the segment of the memory system in a second temperature range.

4. The memory system of claim 1, wherein the memory cell comprises a multi-level memory cell and is configured to store a voltage corresponding to one of a plurality of voltage levels, each of the plurality of voltage levels representing a different logical data value.

5. The memory system of claim 1, wherein the request includes a programming request, and wherein the processing means performs an operation that further includes the following: The identification block will be programmed within either a first temperature range or a second temperature range; and In response to identifying that the block will be programmed at the first temperature range or the second temperature range, a block identifier is stored that identifies the block to be programmed via the programming request.

6. The memory system of claim 1, wherein the processing means further performs the operation comprising: Determine a first average voltage threshold for the pages of a block programmed within a first temperature range and the blocks read within the first temperature range; Determine a second average voltage threshold for the pages of a block programmed under the first temperature range and a block read under the second temperature range; A third average voltage threshold is determined for the pages of the block programmed in the second temperature range and the block read in the first temperature range; and A fourth average voltage threshold is determined for the pages of the block programmed under the second temperature range and the block read under the second temperature range, wherein the temperature compensation value is determined based on the first, second, third, and fourth average voltage thresholds.

7. The memory system of claim 1, wherein the temperature compensation value is determined in response to a count of cross-temperature operations satisfying a predetermined criterion.

8. A method for use in a memory, comprising: Receive a request to perform a memory access operation, the request identifying a memory cell in a segment of a memory system comprising at least a portion of a memory device; The count of cross-temperature operations performed on the memory device is determined to meet a predetermined criterion. In response to determining that the count of the cross-temperature operations performed on the memory device satisfies the predetermined criterion, a temperature compensation value is determined corresponding to an access control voltage adjustment value specific to the segment of the memory system, wherein the predetermined criterion adjusts the frequency at which the temperature compensation value is determined. and Based on the amount represented by the temperature compensation value, the access control voltage applied to the memory cell during the memory access operation is adjusted.

9. The method of claim 8, wherein the segment of the memory system comprises a semiconductor die on which the memory device having the memory cells is fabricated.

10. The method of claim 8, wherein determining that the count of the cross-temperature operation of the memory device satisfies the predetermined criterion comprises determining that the occurrence of the cross-temperature condition is caused by programming a block into the segment of the memory system at a first temperature range and reading a page from the segment of the memory system at a second temperature range.

11. The method of claim 8, wherein the memory cell comprises a multi-level memory cell and is configured to store a voltage corresponding to one of a plurality of voltage levels, each of the plurality of voltage levels representing a different logical data value.

12. The method of claim 8, wherein the request includes a programming request, and wherein the method further comprises: The identification block will be programmed within either the first or second temperature range; and In response to identifying that the block will be programmed at the first temperature range or the second temperature range, a block identifier is stored that identifies the block to be programmed via the programming request.

13. The method of claim 8, further comprising: Determine a first average voltage threshold for the pages of a block programmed within a first temperature range and the blocks read within the first temperature range; Determine a second average voltage threshold for the pages of a block programmed under the first temperature range and a block read under the second temperature range; A third average voltage threshold is determined for the pages of the block programmed in the second temperature range and the block read in the first temperature range; and A fourth average voltage threshold is determined for the pages of the block programmed under the second temperature range and the block read under the second temperature range, wherein the temperature compensation value is determined based on the first, second, third, and fourth average voltage thresholds.

14. The method of claim 8, wherein determining that the count of the cross-temperature operation of the memory device has met a predetermined criterion includes determining that the count of the cross-temperature operation is higher than a predetermined threshold.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to further perform the following operations: Receive a request to perform a memory access operation, the request identifying a memory cell in a segment of a memory system comprising at least a portion of a memory device; Determine that the operating temperature of the memory device meets the threshold criterion; In response to determining that the operating temperature of the memory device meets the threshold criterion, a temperature compensation value is determined corresponding to the access control voltage adjustment value specific to the segment of the memory system; and Based on the amount represented by the temperature compensation value, the access control voltage applied to the memory cell during the memory access operation is adjusted, wherein determining the temperature compensation value further includes: Determine a first average voltage threshold for the pages of a block programmed within a first temperature range and the blocks read within the first temperature range; Determine a second average voltage threshold for the pages of a block programmed under the first temperature range and a block read under the second temperature range; Determine a third average voltage threshold for the pages of a block programmed in the second temperature range and a block read in the first temperature range; and A fourth average voltage threshold is determined for the pages of the block programmed under the second temperature range and the block read under the second temperature range, wherein the temperature compensation value is determined based on the first, second, third, and fourth average voltage thresholds.

16. The non-transitory computer-readable storage medium of claim 15, wherein the segment of the memory system comprises a semiconductor die on which the memory device having the memory cells is fabricated.

17. The non-transitory computer-readable storage medium of claim 15, wherein determining that the operating temperature of the memory device satisfies the threshold criterion comprises determining the occurrence of a cross-temperature condition caused by programming a block into the memory system within a first temperature range and reading a page from the memory system within a second temperature range.

18. The non-transitory computer-readable storage medium of claim 15, wherein the memory cell comprises a multi-level memory cell and is configured to store a voltage corresponding to one of a plurality of voltage levels, each of the plurality of voltage levels representing a different logical data value.

19. The non-transitory computer-readable storage medium of claim 15, wherein the request includes a programming request, and wherein the processing means performs the operation further comprising: The identification block will be programmed within either the first temperature range or the second temperature range; and In response to identifying that the block will be programmed at the first temperature range or the second temperature range, a block identifier is stored that identifies the block to be programmed via the programming request.

20. The non-transitory computer-readable storage medium of claim 15, wherein the processing means further performs the operations comprising: The count of cross-temperature operations of the memory device is determined to meet a predetermined criterion.

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