A phase change memory operation method, phase change memory and memory system

Abstract

The embodiment of the present invention provides a phase change memory operation method, a phase change memory and a memory system. The operation method includes: after performing a read operation on a selected phase change memory cell among the plurality of phase change memory cells, performing a weak write operation on the selected phase change memory cell, wherein the weak write operation is used to restore the region of the phase change material layer of the selected phase change memory cell that is transformed into an amorphous phase due to read disturbance to a crystalline phase, thereby improving the life of the phase change memory.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to an operating method of a phase change memory, a phase change memory and a memory system. Background Art

[0002] Conventional read operations of phase change memory may be much more frequent and continuous than weak write operations or other operations, thus becoming a key factor in the life of phase change memory cells. In particular, when the read signal is much higher than the signal that may be required to read the data, a relatively large inrush current is introduced, which is the main factor causing read disturbance. Therefore, how to eliminate the influence of read disturbance on the data stored in the phase change memory cell is a technical problem that needs to be solved urgently. Summary of the invention

[0003] In view of this, the main purpose of the present invention is to provide a phase change memory operation method, a phase change memory and a memory system. After performing a read operation on the phase change memory cell, a weak write operation is performed on the phase change memory cell to eliminate the influence of the read operation on the data stored in the phase change memory cell.

[0004] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides an operating method of a phase change memory, comprising:

[0006] After performing a read operation on a phase change memory cell selected from the plurality of phase change memory cells, a weak write operation is performed on the selected phase change memory cell, wherein the weak write operation is used to restore a region in a phase change material layer of the selected phase change memory cell that has been transformed into an amorphous phase due to read disturbance to a crystalline phase.

[0007] Optionally, a first current is provided to the selected phase change memory unit; the first current is smaller than a reset current; and the reset current is used to transform the entire region of the phase change material layer included in the phase change memory unit from a crystalline phase to an amorphous phase.

[0008] Optionally, before performing the weak write operation on the selected phase change memory cell, the operation method further includes:

[0009] A second current is provided to the selected phase-change memory cell, so that the selector of the selected phase-change memory cell is continuously in the on state.

[0010] Optionally, the operation method further includes:

[0011] Determine whether the number of times the read operation is currently executed is less than a preset number;

[0012] If it is determined that the number of times the read operation is currently performed is not less than the preset number of times, performing a weak write operation on the selected phase change memory unit;

[0013] If it is determined that the number of the currently executed read operations is less than the preset number, the weak write operation is not performed on the selected phase change memory unit.

[0014] Optionally, the more times the read operation is currently performed, the greater the first current provided to the selected phase change memory unit.

[0015] Optionally, the phase change memory includes a memory array and a peripheral circuit coupled to the memory array; the memory array includes a plurality of phase change memory cells; the peripheral circuit is configured to control operations on the plurality of phase change memory cells; and the operating method further includes:

[0016] A first current provided to the selected phase change memory cell is determined according to a distance between the selected phase change memory cell and the peripheral circuit, wherein the farther the selected phase change memory cell is from the peripheral circuit, the smaller the first current provided to the selected phase change memory cell is; and the closer the selected phase change memory cell is to the peripheral circuit, the larger the first current provided to the selected phase change memory cell is.

[0017] Optionally, the setting degree of the selected phase change memory cell by the first current is not greater than the setting degree of the selected phase change memory cell by the setting current; wherein the setting degree is used to measure the degree to which a region in the phase change material layer of the phase change memory cell transforms from an amorphous phase to a crystalline phase under the action of a certain current.

[0018] Optionally, the first current and the second current are controlled by a current mirror coupled to the selected phase change memory cell.

[0019] Optionally, the duration of the second current is determined by a read speed of the phase change memory, wherein the faster the read speed, the shorter the duration of the second current.

[0020] Optionally, the operation method further includes:

[0021] When the read operation is performed on the selected phase change memory cell; a first voltage is applied to the word line coupled to the selected phase change memory cell, so that the bit line coupled to the selected phase change memory cell is in a floating state, a second voltage is applied to all unselected word lines belonging to the same storage array block as the selected phase change memory, and a third voltage is applied to all unselected bit lines belonging to the same storage array block as the selected phase change memory; under the action of the first voltage, the second voltage, and the third voltage, the voltage difference applied to the bit line and the word line corresponding to the selected phase change memory cell is greater than the threshold voltage of the selector of the selected phase change memory cell, and the voltage difference applied to the bit line and the word line corresponding to all unselected phase change memory cells in the storage array block is less than a preset voltage; the preset voltage is less than the threshold voltage.

[0022] In a second aspect, a phase change memory provided by an embodiment of the present invention comprises: a plurality of memory array blocks, each memory array block comprising a plurality of phase change memory cells;

[0023] and a peripheral circuit coupled to the plurality of phase change memory cells; wherein,

[0024] The peripheral circuit is configured to: after performing a read operation on a selected phase change memory cell among the multiple phase change memory cells, perform a weak write operation on the selected phase change memory cell, wherein the weak write operation is used to restore the area in the phase change material layer of the selected phase change memory cell that is transformed into an amorphous phase due to read interference to a crystalline phase.

[0025] Optionally, the peripheral circuit is further configured to: provide a first current to the selected phase change memory unit; the first current is smaller than a reset current; and the reset current is used to transform the entire region of the phase change material layer included in the phase change memory unit from a crystalline phase to an amorphous phase.

[0026] Optionally, the peripheral circuit is further configured to: before performing the weak write operation on the selected phase change memory cell, provide a second current to the selected phase change memory cell so that the selector of the selected phase change memory cell is continuously in an on state.

[0027] Optionally, the peripheral circuit is further configured to: when performing the read operation on the selected phase change memory cell; apply a first voltage to the word line coupled to the selected phase change memory cell, so that the bit line coupled to the selected phase change memory cell is in a floating state, apply a second voltage to all unselected word lines belonging to the same storage array block as the selected phase change memory, and apply a third voltage to all unselected bit lines belonging to the same storage array block as the selected phase change memory; under the action of the first voltage, the second voltage, and the third voltage, the voltage difference applied to the bit line and word line corresponding to the selected phase change memory cell is greater than the threshold voltage of the selector of the selected phase change memory cell, and the voltage difference applied to the bit line and word line corresponding to all unselected phase change memory cells in the storage array block is less than a preset voltage; the preset voltage is less than the threshold voltage.

[0028] In a third aspect, an embodiment of the present invention further provides a memory system, comprising: one or more phase change memories as described above and a memory controller coupled to the phase change memories.

[0029] The embodiment of the present invention provides an operation method of a phase change memory, a phase change memory and a memory system. The phase change memory includes: a plurality of memory array blocks, each memory array block includes a plurality of phase change memory cells; the operation method includes: after performing a read operation on a selected phase change memory cell among the plurality of phase change memory cells, performing a weak write operation on the selected phase change memory cell, wherein the weak write operation is used to restore the region of the phase change material layer of the selected phase change memory cell that is affected by the read disturbance and transformed into an amorphous phase to a crystalline phase. The operation method provided by the embodiment of the present invention reduces the influence of the read disturbance on the phase change memory cell by performing a weak write operation after the read operation, thereby improving the life of the phase change memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of various pulses during the operation of a phase change memory unit provided by an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of threshold voltage distributions of set and reset states of a phase change memory cell provided by an embodiment of the present invention;

[0032] Figure 3 A block diagram of an exemplary system of a memory including a phase change memory cell provided for an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of an exemplary memory including a peripheral circuit provided for an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of a structure of an implementation of a storage array 401 provided in an embodiment of the present invention;

[0035] Figure 6 A partial three-dimensional schematic diagram of a phase change memory unit provided by an embodiment of the present invention;

[0036] Figure 7 Another partial three-dimensional schematic diagram of a phase change memory unit provided by an embodiment of the present invention;

[0037] Figure 8 A block diagram of an exemplary memory including a memory array and peripheral circuits provided for an embodiment of the present invention;

[0038] Fig. 9 A structural schematic diagram of a read operation on a phase change memory cell provided by an embodiment of the present invention;

[0039] Fig.10 A schematic diagram of a flow chart of a method for operating a phase change memory provided by an embodiment of the present invention;

[0040] Fig.11 A relationship diagram of the current-voltage characteristics of the OTS when the selector provided in the embodiment of the present invention is the OTS;

[0041] Fig.12 Timing of the read operation provided by the embodiment of the present invention Figure 1 ;

[0042] Fig.13 Timing of the read operation provided by the embodiment of the present invention Figure 2 ;

[0043] Fig.14 A schematic diagram of the circuit structure of a current mirror provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be very practical without departing from the scope of the present invention. In addition, the present invention may also be used for various other applications. The functions and structural features as described in the present invention may be combined, adjusted and modified with each other and in a manner not specifically shown in the accompanying drawings, so that these combinations, adjustments and modifications are within the scope of the disclosure of the present invention.

[0045] Typically, a term can be understood, at least in part, from usage in context. For example, the term "one or more," as used herein, can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a feature, structure, or combination of features in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of other factors that are not necessarily explicitly described, again depending at least in part on the context.

[0046] Phase Change Memory (PCM) is a non-volatile memory device that uses phase change materials to store data. PCM can be based on heating and quenching the phase change material in an electrothermal manner, using the difference between the resistivity of the amorphous state and the crystalline state in the phase change material (e.g., a chalcogenide alloy). The phase change material in the PCM cell can be located between two electrodes, and a current can be applied to repeatedly switch the material (or at least a portion of it blocking the current path) between the two phases to store data. The set state is a low resistance state of the PCM cell, which can be obtained by generating a crystalline region in the chalcogenide material. When the chalcogenide material is heated at a crystallization temperature for a sufficient time, crystallization occurs. Conversely, the reset state is a high resistance state of the PCM cell, which can be obtained by generating a non-crystalline region in the chalcogenide material. When the chalcogenide material is heated to above its melting temperature and then rapidly quenched to form an amorphous state, an amorphous state can be generated. Among them, the set state can be referred to as the on state; and the reset state can be referred to as the off state.

[0047] As described above, when the phase change material in the PCM switches between the crystalline state and the amorphous state, different pulses (such as light pulses, electric pulses) can be used to control the heating of the phase change material. Figure 1As shown, when a long and medium-intensity programming pulse (also called Set Pulse) is applied to raise the temperature of the phase change material layer of the phase change memory unit to below the melting temperature Tm and above the crystallization temperature Tx, and is maintained for a period of time to promote the growth of the crystal nucleus, the phase change material layer of the phase change memory unit can be transformed from an amorphous state (corresponding to a high resistance state) to a crystalline state (corresponding to a low resistance state). The process of realizing the transformation of the phase change material of the phase change memory unit from a high state (0 state) to a low resistance state (1 state) is usually called a set (Set) process, or a write operation process; after applying a short and strong reset pulse (also called Reset Pulse) to raise the temperature of the phase change material layer of the phase change memory unit to above the melting temperature Tm, and then undergoing rapid cooling (Cooling Down), the phase change material layer of the phase change memory unit can be transformed from a crystalline state to an amorphous state. The process of realizing the transformation of the phase change material layer of the phase change memory unit from a low resistance state (1 state) to a high state (0 state) is usually called a reset (Reset) process, or an erase operation process. The Reset process and the Set process are mutually reversible processes, so that the phase change memory cell can use the crystalline state to represent the unit binary data 1, and use the amorphous state to represent the binary data 0. In some embodiments, the phase change memory may include multiple memory arrays, and the threshold voltage distribution of the phase change memory cells included in each memory array may be as follows: Figure 2 As shown, it can be seen that each phase change memory cell in the storage array can have a different threshold voltage. It should be noted that the distribution of threshold voltages can vary from one storage array to another, that is, there may be some differences in the threshold voltage distributions corresponding to the phase change memory cells in different storage arrays, that is, the threshold voltage distributions statistically obtained for different numbers of phase change memory cells will have slightly different shapes, but the general shapes are similar. The threshold voltage distribution of a storage array can be obtained through a preliminary durability test cycle. In addition, after applying a very weak read pulse that will not affect the phase change material layer, the resistance value of the phase change memory cell is measured to achieve the reading of the data stored in the phase change memory cell.

[0048] At present, in the related technical solutions, a relatively large inrush current spike is introduced during the reading process of the phase change memory cell, wherein the inrush current spike becomes the main factor of the read disturbance, especially the phase change memory cell closer to the peripheral circuit in the storage array suffers from more serious read disturbance due to the relatively large inrush current spike.

[0049] In order to solve the above problems, an embodiment of the present invention solves a method for operating a phase change memory, wherein, after performing a read operation on a selected phase change memory cell, a weak write operation is performed on the selected phase change memory cell to offset the read disturbance caused by a relatively large inrush current spike introduced by the read operation.

[0050] Figure 3 Block diagram of an exemplary system of a memory including a phase change memory cell provided by an embodiment of the present invention. System 300 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 3 As shown, the system 300 may include a host 308 and a memory system 302, wherein the memory system 302 has one or more memories 304 and a memory controller 306; the host 308 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), wherein the system on a chip may be, for example, an application processor (AP). The host 308 may be configured to send data to the memory 304 or receive data from the memory 304.

[0051] Specifically, the memory 304 may be any memory device disclosed in the present invention, as disclosed in detail below, the memory 304, for example, a phase change random access memory (PCRAM); the memory 304 may also refer to a three-dimensional phase change memory.

[0052] According to some embodiments, the memory controller 306 is coupled to the memory 304 and the host 308. And is configured to control the memory 304. The memory controller 306 can manage the data stored in the memory 304 and communicate with the host 308. In some embodiments, the memory controller 306 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 306 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), wherein the SSD or eMMC is used as a data storage device for a mobile device with a high duty cycle environment such as a smart phone, a tablet computer, a laptop computer, and an enterprise storage array. The memory controller 306 can be configured to control the operation of the memory 304, such as read, erase, and program operations. The memory controller 306 may also be configured to manage various functions regarding data stored or to be stored in the memory 304, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 306 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 304. The memory controller 306 may also perform any other suitable functions, such as formatting the memory 304. The memory controller 306 may communicate with an external device (e.g., a host 308) according to a specific communication protocol.For example, the memory controller 306 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0053] The memory controller 306 and one or more memories 304 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 302 can be implemented and packaged into different types of terminal electronic products. In one example, the memory controller 306 and the single memory 304 can be integrated into a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card that connects the memory card to a host (e.g., Figure 3 In another example, the memory controller 306 and the plurality of memories 304 may be integrated into the SSD. The SSD may also include a memory card connector that couples the SSD to a host (e.g., Figure 3 The memory controller 306 may be configured to control the erase, read, and weak write operations of the memory 304.

[0054] Figure 4Schematic diagram of an exemplary memory including peripheral circuits provided for an embodiment of the present invention. The memory 304 may be a three-dimensional phase change memory, which may include a phase change memory array 401 and a peripheral circuit 402 coupled to the phase change memory array 401. The phase change memory array 401 may include a word line 4011, a bit line 4012, and a phase change memory cell 4013 formed between the word line 4011 and the bit line 4012. In some embodiments, each phase change memory cell 4013 may include a PCM element (including a phase change material, not shown in the figure) connected in series with a selector (not shown in the figure). In some embodiments, the phase change memory cell 4013 may include a DRAM cell of a paired transistor and a capacitor. In order to operate the phase change memory array 401, a word line voltage (Vw) may be applied to a selected word line 4011, and a bit line voltage (Vb) may be applied to a selected bit line 4012.

[0055] Regarding the structure of the phase change memory array 401, in some embodiments, as Figure 5 As shown, it is a schematic diagram showing a structure of an implementation method of a phase change memory array 401 provided in an embodiment of the present invention. Figure 5 It can be seen that the phase change memory array 401 is a three-dimensional memory array, which is composed of a plurality of small memory array blocks with a single bit line, a word line and a phase change memory cell. A three-dimensional phase change memory generally includes a top bit line, a word line, a bottom bit line and a memory cell located at the intersection of the bit line and the word line. In practical applications, the word line, the top bit line and the bottom bit line are usually formed by a 20nm / 20nm equal width line (L / S, Line / Space) pattern formed after a patterning process. Among them, the structure of the phase change memory cell 4013, such as Figure 6 As shown, it shows a partial three-dimensional schematic diagram of a phase change memory cell 4013 provided in an embodiment of the present invention. The phase change memory cell 4013 includes: a stacked PCM element 602, a selector 604, and a plurality of electrodes 601, 603, and 605. The PCM element 602 can utilize the difference between the resistivity of the amorphous phase (i.e., amorphous state) and the crystalline phase (i.e., crystalline state) in the phase change material based on the heating and quenching of the phase change material in an electrothermal manner. A current can be applied to cause the phase change material of the PCM element 602 (or at least a portion thereof that blocks the current path) to repeatedly switch between two phases to store data. A single bit of data can be stored in each storage cell 4013, and a single bit of write operation or read operation can be performed by changing the voltage applied to the corresponding selector 604.

[0056] In some embodiments, the material of the PCM element 602 includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material; the material of the selector 604 may include any suitable bidirectional threshold switch (OTS) material, such as ZnxTey, GexTey, NbxOy, SixAsyTez, etc. The electrodes 601, 603, and 605 may include a conductive material, including but not limited to W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of the electrodes 601, 603, and 605 includes carbon, such as amorphous carbon.

[0057] It should be noted that the upper and lower phase change memory cells in the phase change memory array 401 may also share a word line, for example, Figure 7 shown.

[0058] Figure 8 A block diagram of an exemplary memory including a memory array and peripheral circuits provided for an embodiment of the present invention. Figure 8 As shown, the memory 304 includes a phase change memory array 401 and a peripheral circuit 402, wherein the memory array has been described above. The peripheral circuit 402 includes: a control logic 4021, an address register 4022, a voltage generator 4023, a row decoder / word line driver 4024, a page buffer / sense amplifier circuit 4025, a column decoder / bit line driver / data latch 4026, and a data register / data I / O 4027, wherein;

[0059] The page buffer / sense amplifier circuit 4025 can be configured to read data from the phase-change memory array 401 and program (write) data to the phase-change memory array 401 according to the control signal from the control logic 4021. In one example, the page buffer / sense amplifier 4025 can store data to be programmed into the phase-change memory array 401 (e.g., Figure 4In another example, the page buffer / sense amplifier 4025 can perform a program verification operation to ensure that the data has been correctly programmed into the phase change memory cell 4013 coupled to the selected word line 4011. In yet another example, the page buffer / sense amplifier 4025 can also sense a low-power signal from the selected bit line 4012 representing the data bit stored in the phase change memory cell 4013, and amplify the small voltage swing to a recognizable logic level in a read operation. In some embodiments, the page buffer / sense amplifier 4025 may include a comparator (e.g., a voltage comparator) to compare a voltage signal (e.g., a read voltage) with a reference voltage signal (e.g., a predetermined threshold voltage of a memory cell in a "set" state). The column decoder / bit line driver / data latch 4026 can be configured to be controlled by the control logic 4021 and select one or more phase change memory cells 4013 and bit lines 4012. Column decoder / bit line driver / data latch 4026 may be further configured to drive selected bit line 4012. Column decoder / bit line driver / data latch 4026 may be further configured to drive bit line 4012 using a bit line voltage generated from voltage generator 4023. Column decoder / bit line driver / data latch 4026 may be a temporary binary data storage device for storing bits. In some embodiments, column decoder / bit line driver / data latch 4026 may include a read data latch to temporarily store read data.

[0060] The data register / data I / O 416 can be coupled to the page buffer / sense amplifier 4025 and / or the column decoder / bit line driver / data latch 4026, and is configured to direct (route) data input from the data bus 4028 to the desired phase change memory cell 4013 of the phase change storage array 401, and to direct (route) data output from the desired memory cell to the data bus 4028.

[0061] The row decoder / word line driver 4024 may be configured to be controlled by the control logic 4021 and select one or more phase change memory cells 4013 and word lines 4011 of the phase change memory array 401. The row decoder / word line driver 4024 may be further configured to drive the selected word line 4011. The row decoder / word line driver 4024 may be further configured to drive the word line 4011 using the word line voltage generated from the voltage generator 4023.

[0062] The voltage generator 4023 can be configured to be controlled by the control logic 4021 according to a control signal from the control logic 4021, and generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be provided to the phase change memory array 401.

[0063] The control logic 4021 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The control logic 4021 is configured to be received from a host (eg, Figure 3 308 in the figure) receives clock signals, command signals, address signals and data signals, wherein the command signals are received via the command bus 4029; and the data signals are received via the data bus 4028. In some embodiments, the control logic 4021 can be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU, Micro Controller Unit)), a digital signal processor (DSP, Digital Signal Processor), an application specific integrated circuit (ASIC, Application Specific Integrated Circuit), a field programmable gate array (FPGA, Field Programmable Gate Array), a programmable logic device (PLD, Programmable Logic Device), a state machine, a gating logic, a discrete hardware circuit and other appropriate hardware, firmware and / or software configured to perform the various functions described.

[0064] Fig. 9 The structure diagram of the reset operation of the phase change memory unit provided by the embodiment of the present invention is as follows. Fig. 9 As shown, once the control logic 4021 determines that the command signal is a read command, the control logic 4021 triggers a read operation, and then controls the word line driver to introduce a read voltage to the word line of the selected phase change memory cell in the phase change storage array 401, and controls the bit line driver to introduce a bit line voltage to the bit line of the selected phase change memory cell, so as to perform a read operation on the selected phase change memory cell.

[0065] The specific process is as follows: After selecting an appropriate read voltage, the read voltage is applied to the selected phase change memory cell of the phase change memory array 401 via the word line. The sense amplifier 4025 is configured to receive read data, such as a read current or a read voltage. The sense amplifier 4025 may also include a comparator (e.g., a voltage comparator) to compare the read voltage with a reference voltage. According to some embodiments, the reference voltage may be predetermined as a set threshold voltage or a reset threshold voltage. The comparison output signal and / or the read signal may be temporarily stored in Figure 8 In some embodiments, the data buffer may be included in the data register 4027. For example, the read address and read data accompanying the read command are temporarily stored in the data register, and the read address and read data are kept until the next read command. The read data stored in the data register can be output to the next stage via the output of the data register for corresponding signal processing.

[0066] It should be noted that Fig. 9 Vread1, Vreadi, and Vreadn shown in the figure represent different reading voltages applied, and their amplitudes increase successively. It should be understood that the reading voltage applied once may not be able to read out the data, and different reading voltages need to be applied multiple times to accurately read out the data. The application of the reading voltage is not the focus of the present invention and will not be described in detail here.

[0067] Based on the above three-dimensional phase change memory, in order to solve the technical problems described above, an embodiment of the present invention provides an operation method of a phase change memory, such as Fig.10 As shown in FIG. 1 , it is a schematic diagram showing a structure of an operation method of a phase change memory provided by an embodiment of the present invention. It should be noted that the structure of the phase change memory can be as follows: Figure 6 As shown or Figure 7 The phase change memory includes a plurality of storage array blocks, based on which, the operation method may include:

[0068] S1001: After performing a read operation on a phase change memory cell selected from the multiple phase change memory cells, perform a weak write operation on the selected phase change memory cell, wherein the weak write operation is used to restore the region in the phase change material layer of the selected phase change memory cell that has been transformed into an amorphous phase due to read disturbance to a crystalline phase.

[0069] It should be noted that the above Figure 6 and Figure 7 From the structure of the described phase change memory cell, it can be seen that the phase change memory cell is a non-volatile memory cell that uses phase change materials to store data. The difference between the resistivity of the phase change material in the crystalline state and the amorphous state is used to represent a single bit of stored data 1 or 0 to achieve data storage. The conversion between the crystalline state and the amorphous state of the phase change memory cell is achieved by applying current to the phase change material included in the phase change memory cell to control the heating of the phase change material so that the phase change material in the PCM produces crystallization or amorphousness, so as to achieve the conversion of the phase change memory cell between the crystalline state and the amorphous state. In addition, the phase change memory cell also includes an OTS type selector. The current-voltage characteristics of this type of selector are as follows: Fig.11 As shown. Fig.11As shown in the figure, when the voltage across OTS reaches a certain value, the current will increase instantaneously, forming a surge current peak. We should know that when performing a read operation on the selected phase change memory cell, the selector must first be turned on to apply voltage to the PCM element (phase change material) of the selected phase change memory cell to measure the threshold voltage of the PCM element to read out the data stored in the selected phase change memory cell. Therefore, Fig.12 As shown, when a read operation is performed on a selected phase change memory cell, a relatively large current will be introduced into the phase change memory cell at the moment the selector is turned on. The large current may heat the phase change material of the phase change memory cell. When it reaches a certain level, the state of a part of the phase change material will change, causing its resistance to increase and its threshold voltage to increase, thereby interfering with the subsequent reading of the phase change memory cell.

[0070] It should be noted that in Fig.12 In the figure, the curve corresponding to IBL represents the instantaneous current curve flowing through the selected phase change memory cell. The inrush current peak in the current curve is only exemplarily appeared in the T2 stage, and may also appear in the T3 stage. This is introduced into the selected phase change memory cell when the selector included in the selected phase change memory is turned on; the curve corresponding to VWL represents the voltage curve applied to the word line coupled to the selected phase change memory cell. The voltage curve is a description of different voltages required for phase change memory cells with different threshold voltages, not for a phase change memory cell. For a phase change memory cell, the voltage on the word line is either the voltage value corresponding to the first step of the voltage curve, or the voltage value corresponding to the second step of the voltage curve. Voltage value, which depends on which voltage value can turn on the selector included in the phase-change memory cell; the curve corresponding to VBL represents the voltage curve applied to the bit line coupled to the selected phase-change memory cell, and the voltage can be provided by the bit line driver BL_driver through the corresponding selection transistor. The voltage on the bit line is in a floating state during the subsequent operation, and is coupled and increased as the voltage on the word line increases; the curve corresponding to BL_driver represents the voltage curve applied to the bit line driver. Since it is not necessary to maintain current passing through the selected phase-change memory cell during the read operation, the bit line driver BL_driver can only provide a negative voltage at the beginning, and then it can be in a floating state.

[0071] In addition, for the reading of the phase change memory cell, based on the above Figure 1 As shown in FIG. 1 , in theory, when a phase change memory cell is read, a very weak read pulse is applied to the phase change memory cell which will not affect the phase change material layer. However, in actual operation, Figure 2As shown, since a phase change memory array contains phase change memory cells, some of which are in a set state and some are in a reset state, the corresponding Figure 2 As shown in the threshold voltage distribution, when a read operation is performed on a selected phase-change memory cell, a higher read voltage may be used to read the phase-change memory cell with a lower threshold voltage. The higher read voltage applied to the phase-change memory cell may also introduce a relatively large current into the phase-change memory cell, causing the threshold voltage of the phase-change memory cell to change, thereby interfering with the subsequent reading of the phase-change memory cell.

[0072] Therefore, in order to solve the above technical problems, an embodiment of the present invention provides a method for operating a phase change memory, which performs a weak write operation on the selected phase change memory cell after performing a read operation on the selected phase change memory cell, so as to eliminate the influence of the large current introduced by the read operation on the threshold voltage of the selected phase change memory cell and the subsequent interference with the reading of the selected memory cell.

[0073] Specifically, in some embodiments, the weak write operation may include:

[0074] A first current is provided to the selected phase-change memory cell; the first current is smaller than a reset current; and the reset current is used to transform the entire region of the phase-change material layer included in the phase-change memory cell from a crystalline phase to an amorphous phase.

[0075] It should be noted that here a weak write operation is performed on the selected phase change memory cell by a current pulse. The first current is applied to the selected phase change memory cell after the read operation is performed on the selected phase change memory cell. The first current is a write current, which is to restore the part of the selected phase change memory cell that is transformed to the amorphous phase due to the read interference to the crystalline phase, so as to eliminate the interference of the increase in the threshold voltage of the phase change memory cell caused by the surge peak introduced by the read operation on the subsequent reading. Therefore, the first current should be less than the reset current, because the reset current is used to transform the entire area of ​​the phase change material layer of the phase change memory cell from the crystalline phase to the amorphous phase, which is an operation to increase the threshold voltage of the phase change memory cell. Specifically, the amplitude of the first current cannot be greater than the amplitude of the reset current.

[0076] In some embodiments, the more times the read operation is currently performed, the greater the first current provided to the selected phase-change memory cell.

[0077] It should be noted that, since read interference is a cumulative process, after the read operation is performed on the selected phase change memory cell, no weak write operation has been performed. Therefore, when the weak write operation is performed on the selected phase change memory cell for the first time here, the first current used needs to be larger, that is, the more times the read operation is performed currently, the larger the first current provided to the selected phase change memory cell.

[0078] According to the above description, the phase change memory cell closer to the peripheral circuit in the memory array suffers from more serious read disturbance due to a relatively large inrush current peak value. Therefore, in some embodiments, the phase change memory includes a memory array and a peripheral circuit coupled to the memory array; the memory array includes a plurality of phase change memory cells; the peripheral circuit is configured to control the operation of the plurality of phase change memory cells; the operation method further includes:

[0079] A first current provided to the selected phase change memory cell is determined according to a distance between the selected phase change memory cell and the peripheral circuit, wherein the farther the selected phase change memory cell is from the peripheral circuit, the smaller the first current provided to the selected phase change memory cell is; and the closer the selected phase change memory cell is to the peripheral circuit, the larger the first current provided to the selected phase change memory cell is.

[0080] It should be noted that, through research, it is found that the closer the phase change memory unit is to the peripheral circuit, the smaller the loss of the voltage applied from the voltage source is at this time, so the voltage applied to the word line coupled to the selected phase change memory unit will not be reduced due to the loss, and it is a relatively large value, so the current introduced at this time is also relatively large, and the impact of the read disturbance is more serious, so at this time, the first current needs to be larger, so that the area affected by the read disturbance and transformed to the amorphous phase can be fully restored to the crystalline phase. That is to say, as stated in the embodiment of the present invention, when the selected phase change memory unit is farther away from the peripheral circuit, the first current provided to the selected phase change memory unit is smaller; when the selected phase change memory unit is closer to the peripheral circuit, the first current provided to the selected phase change memory unit is larger.

[0081] Here, the first current may be set according to the distance from the peripheral circuit and its magnitude may be set according to actual conditions, and its value may not be specifically limited.

[0082] In some embodiments, the setting degree of the selected phase change memory cell by the first current is no greater than the setting degree of the selected phase change memory cell by the setting current; wherein the setting degree is used to measure the degree to which a region in a phase change material layer of a phase change memory cell is transformed from an amorphous phase to a crystalline phase under the action of a certain current.

[0083] It should be noted that what is described here is the relationship between the first current and the set current. It should be understood that the set current is the current required to transform the entire area of ​​the phase change material layer contained in the selected phase change memory cell from the amorphous phase to the crystalline phase. In other words, the set current is aimed at the phase change memory cell in the reset state, and the phase change materials contained therein are all in the amorphous state, and such a set current is required to transform them all into the crystalline state. The weak write operation provided in the embodiment of the present invention is aimed at reading a phase change memory cell that has undergone write operations multiple times, wherein the phase change material layer contained in the phase change memory cell is not all in the amorphous state. In other words, the area of ​​the selected phase change memory cell that is transformed from the amorphous state to the crystalline state under the action of the first current will not be the entire phase change material layer. It should be known that, from the aforementioned Figure 1 As shown in the schematic diagram of each pulse in the operation process of the phase change memory unit, it can be seen that in order to achieve a certain setting degree of the phase change memory unit, a certain pulse size and its duration are required. In addition, since the setting degree required to be achieved by the aforementioned setting current is to transform all the phase change material layers in the phase change memory unit from the amorphous phase to the crystalline phase, and the weak write operation provided by the implementation of the present application only needs to restore the region of the phase change material layer of the selected phase change memory unit that has been transformed to the amorphous phase due to the read disturbance to the crystalline phase, and the worst case of read disturbance is to transform all the phase change material layers to the amorphous phase, then the setting degree of the weak write operation under the action of the first current is not greater than the setting degree required to be achieved by the setting current. That is, the setting degree of the first current on the selected phase change memory unit is not greater than the setting degree of the setting current on the selected phase change memory unit. In layman's terms, to obtain the setting effect of the above-mentioned weak write operation, it is achieved under the combined action of the amplitude and duration of the first current. That is, the magnitude of the first current is not limited to be greater than the set current, equal to the set current, or less than the set current, and the above effect can be achieved by reasonably setting its amplitude and duration. That is, the first current can be greater than, equal to, or less than the set current.

[0084] In some embodiments, the operating method further includes: before performing the weak write operation on the selected phase change memory cell, the operating method further includes:

[0085] A second current is provided to the selected phase-change memory cell, so that the selector of the selected phase-change memory cell is continuously in the on state.

[0086] It should be known that before a read operation and a weak write operation, the selector included in the selected phase-change memory cell must be turned on before the read operation or the weak write operation can be performed. Fig.11 It can be seen from the current-voltage characteristics of the selector shown that when the selector is turned on instantly, a large inrush current will be introduced. However, after the read operation is completed, if there is no current flowing in the selector contained in the selected phase-change memory cell, it will be closed. Therefore, in order to avoid the large inrush current introduced by turning on the selector OTS again when performing a weak write operation after the read operation, at this time, before performing the weak write operation on the selected phase-change memory cell, a second current is provided to the selected phase-change memory cell, in order to ensure that the selected phase-change memory cell remains in the on state after the read is completed and before the weak write operation is performed. It should be known that the second current should be greater than the holding current of the selector contained in the selected phase-change memory cell (that is, Fig.11 In the embodiment of the present invention, the selector is in the on state only when the second current is greater than Ihold. In the actual operation, in order to save the time for judging the end of reading, the second current can be applied when the read operation is performed on the selected phase-change memory cell until the first current is applied to the selected phase-change memory cell. It should be known that both the first current and the second current are greater than Ihold, that is, the selector included in the selected phase-change memory cell is in the on state during the read operation and the weak write operation.

[0087] In some embodiments, the duration of the second current is determined by a read speed of the phase change memory, wherein the faster the read speed, the shorter the duration of the second current.

[0088] It should be noted that the role of the second current is to keep the selector of the selected phase change memory unit in the on state until a weak write operation is performed on the selected phase change memory unit. The duration of the second current is related to the read speed of the phase change memory. When the read speed is fast, the duration of the second current can be shorter; when the read speed is slow, the duration of the second current may be longer. In addition, the second current can be applied to the selected phase change memory unit at the beginning of the reading to ensure that the selector is always in the on state and will not be turned off due to no other operations after the reading is completed.

[0089] Specifically, if Fig.13 As shown, a timing diagram of the operation method provided by an embodiment of the present invention. Fig.13 In FIG. 1 , T1 to T3 represent the read operation process; T4 represents the weak write operation process. I1 represents the second current; I2 represents the first current. Other symbols are the same as those mentioned above. Fig.12 The operation method provided by the embodiment of the present invention is to perform a weak write operation after a read operation so as to compensate for the change in the threshold voltage of the phase change memory cell caused by the read disturbance.

[0090] In some embodiments, the first current and the second current are controlled by a current mirror coupled to the selected phase change memory cell.

[0091] Here, the amplitudes and pulse widths of the first current and the second current may be controlled by a current mirror coupled to a bit line of the selected phase-change memory cell.

[0092] As a way to achieve this, Fig.14 As shown, it shows a schematic diagram of a current mirror structure. Fig.14 In the present invention, a first current and a second current are provided to a selected phase change memory cell through a current mirror, and the amplitudes and pulse widths of the first current and the second current are controlled to perform a weak write operation on the selected phase change memory cell, so as to offset the read disturbance caused by a relatively large inrush current spike introduced by a read operation.

[0093] In some embodiments, the operating method further includes:

[0094] Determine whether the number of times the read operation is currently executed is less than a preset number;

[0095] If it is determined that the number of times the read operation is currently performed is not less than the preset number of times, performing a weak write operation on the selected phase change memory unit;

[0096] If it is determined that the number of the currently executed read operations is less than the preset number, the weak write operation is not performed on the selected phase change memory unit.

[0097] It should be noted that it takes time for the phase change material contained in the phase change memory unit to be heated to a state that is completely changed, and the above Figure 2In the threshold voltage distribution diagram shown, the threshold voltage in the set state or the reset state is a range, that is, the interference caused by the large current introduced by the read operation is a cumulative process, therefore, only when the number of read operations reaches the preset number, after the current read operation is completed, the weak write operation can be performed on the selected phase change memory unit, and when the number of the currently executed read operation is less than the preset number, after the current read operation is completed, the weak write operation is not performed on the selected phase change memory unit. Wherein, the preset number can be set according to an empirical value.

[0098] In some embodiments, a plurality of preset times that increase in sequence may also be set, and whenever the number of times the read operation is currently executed reaches a preset number, after the read operation is completed, a weak write operation is performed on the selected phase change memory unit; between two adjacent preset times, after the read operation is currently executed, a weak write operation is not performed on the selected phase change memory unit. This arrangement can save power consumption.

[0099] For example, assume that three preset times are set, which are 100, 200, and 300, respectively. The above-described scheme is that when the number of the currently executed read operation reaches 100, after the currently executed read operation is completed, a weak write operation is performed on the selected phase change memory unit; when the number of the currently executed read operation reaches 200, after the currently executed read operation is completed, a weak write operation is performed on the selected phase change memory unit; when the number of the currently executed read operation reaches 300, after the currently executed read operation is completed, a weak write operation is performed on the selected phase change memory unit. When the number of the currently executed read operation is less than 100, between 100 and 200, and between 200 and 300, after the currently executed read operation is completed, a weak write operation is not performed on the selected phase change memory unit.

[0100] It should be noted that the above is only an example and does not limit the present invention. How to set the preset number of times can be determined according to the actual phase change memory unit.

[0101] In some embodiments, the operating method further includes:

[0102] When the read operation is performed on the selected phase change memory cell; a first voltage is applied to the word line coupled to the selected phase change memory cell, so that the bit line coupled to the selected phase change memory cell is in a floating state, a second voltage is applied to all unselected word lines belonging to the same storage array block as the selected phase change memory, and a third voltage is applied to all unselected bit lines belonging to the same storage array block as the selected phase change memory; under the action of the first voltage, the second voltage, and the third voltage, the voltage difference applied to the bit line and the word line corresponding to the selected phase change memory cell is greater than the threshold voltage of the selector of the selected phase change memory cell, and the voltage difference applied to the bit line and the word line corresponding to all unselected phase change memory cells in the storage array block is less than a preset voltage; the preset voltage is less than the threshold voltage.

[0103] What is described here is the description of the situation where the voltage is applied to the word line and bit line coupled to the selected phase change memory unit when the read operation is performed on the selected phase change memory. The relevant description has been mentioned above and will not be repeated here. It should be noted that the first voltage, the second voltage and the third voltage described here are only for distinguishing the voltages applied to different parts and are not used to limit the present invention. The first voltage and the second voltage are both a specific form of the word line voltage mentioned above; the third voltage is a specific form of the bit line voltage mentioned above.

[0104] The operating method of the phase change memory provided by the embodiment of the present invention performs a weak write operation on the phase change memory unit after performing a read operation on the phase change memory unit to eliminate the influence of the read operation on the data stored in the phase change memory unit.

[0105] Based on the same inventive concept, an embodiment of the present invention further provides a phase change memory, comprising: a plurality of memory array blocks, each memory array block comprising a plurality of phase change memory cells;

[0106] and a peripheral circuit coupled to the plurality of phase change memory cells; wherein,

[0107] The peripheral circuit is configured to: after performing a read operation on a selected phase change memory cell among the multiple phase change memory cells, perform a weak write operation on the selected phase change memory cell, wherein the weak write operation is used to restore the area in the phase change material layer of the selected phase change memory cell that is transformed into an amorphous phase due to read interference to a crystalline phase.

[0108] In some embodiments, the peripheral circuit is further configured to: provide a first current to the selected phase change memory cell; the first current is less than a reset current; and the reset current is used to transform the entire region of the phase change material layer included in the phase change memory cell from a crystalline phase to an amorphous phase.

[0109] In some embodiments, the peripheral circuit is further configured to: before performing the weak write operation on the selected phase change memory cell, provide a second current to the selected phase change memory cell to keep the selector of the selected phase change memory cell in an on state.

[0110] In some embodiments, the peripheral circuit is further configured as follows: when performing the read operation on the selected phase change memory cell; applying a first voltage to the word line coupled to the selected phase change memory cell, so that the bit line coupled to the selected phase change memory cell is in a floating state, applying a second voltage to all unselected word lines belonging to the same storage array block as the selected phase change memory, and applying a third voltage to all unselected bit lines belonging to the same storage array block as the selected phase change memory; under the action of the first voltage, the second voltage, and the third voltage, the voltage difference between the bit line and the word line corresponding to the selected phase change memory cell is greater than the threshold voltage of the selector of the selected phase change memory cell, and the voltage difference between the bit line and the word line corresponding to all unselected phase change memory cells in the storage array block is less than a preset voltage; the preset voltage is less than the threshold voltage.

[0111] It should be noted that the phase change memory here and the aforementioned operating method belong to the same inventive concept, and the terms and operations appearing here have been described in detail above and will not be repeated here.

[0112] Based on the same inventive concept, an embodiment of the present invention further provides a memory system, comprising: one or more phase change memories as described above and a memory controller coupled to the phase change memories.

[0113] In some embodiments, the peripheral circuit is configured to: perform the read operation on the selected phase change memory in response to a received read instruction; after performing the read operation on the selected phase change memory cell among the multiple phase change memory cells, perform a weak write operation on the selected phase change memory cell in response to a received weak write instruction, wherein the weak write operation is used to restore the region in the phase change material layer of the selected phase change memory cell that has been transformed into an amorphous phase due to read interference to a crystalline phase.

[0114] In some embodiments, the peripheral circuit is further configured to: provide a first current to the selected phase change memory cell; the first current is less than a reset current; and the reset current is used to transform the entire region of the phase change material layer included in the phase change memory cell from a crystalline phase to an amorphous phase.

[0115] In some embodiments, the peripheral circuit is further configured to: before performing the weak write operation on the selected phase change memory cell, provide a second current to the selected phase change memory cell to keep the selector of the selected phase change memory cell in an on state.

[0116] In some embodiments, the peripheral circuit is further configured as follows: when performing the read operation on the selected phase change memory cell; applying a first voltage to the word line coupled to the selected phase change memory cell, so that the bit line coupled to the selected phase change memory cell is in a floating state, applying a second voltage to all unselected word lines belonging to the same storage array block as the selected phase change memory, and applying a third voltage to all unselected bit lines belonging to the same storage array block as the selected phase change memory; under the action of the first voltage, the second voltage, and the third voltage, the voltage difference between the bit line and the word line corresponding to the selected phase change memory cell is greater than the threshold voltage of the selector of the selected phase change memory cell, and the voltage difference between the bit line and the word line corresponding to all unselected phase change memory cells in the storage array block is less than a preset voltage; the preset voltage is less than the threshold voltage.

[0117] Here, the read instruction or weak write instruction is transmitted by the memory controller to the peripheral circuit through a communication interface connected to the peripheral circuit, so that the peripheral circuit responds to the received read instruction or weak write instruction and performs a read operation or a weak write operation on the selected phase change memory cell in the phase change memory.

[0118] The memory system here belongs to the same inventive concept as the aforementioned operating method and phase change memory. The terms and operations appearing here have been described in detail above and will not be repeated here.

[0119] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A method for operating a phase change memory, characterized in that: The phase change memory comprises: a plurality of memory array blocks, each memory array block comprises a plurality of phase change memory cells; the operation method comprises: After performing a read operation on a phase change memory cell selected from the plurality of phase change memory cells, performing a weak write operation on the selected phase change memory cell, wherein the weak write operation is used to restore a region in the phase change material layer of the selected phase change memory cell that is transformed into an amorphous phase due to read disturbance to a crystalline phase; The operation method further includes: Determine whether the number of times the read operation is currently executed is less than a preset number; If it is determined that the number of times the read operation is currently performed is not less than the preset number of times, performing a weak write operation on the selected phase change memory unit; If it is determined that the number of the currently executed read operations is less than the preset number, the weak write operation is not performed on the selected phase change memory cell.

2. The operating method according to claim 1, characterized in that: The weak write operation includes: A first current is provided to the selected phase-change memory cell; the first current is smaller than a reset current; and the reset current is used to transform the entire region of the phase-change material layer included in the phase-change memory cell from a crystalline phase to an amorphous phase.

3. The operating method according to claim 2, characterized in that: Before performing the weak write operation on the selected phase change memory cell, the operation method further includes: A second current is provided to the selected phase-change memory cell, so that the selector of the selected phase-change memory cell is continuously in the on state.

4. The operating method according to claim 2, characterized in that: The more times the read operation is currently performed, the greater the first current provided to the selected phase-change memory cell.

5. The operating method according to claim 1, characterized in that: The phase change memory comprises a memory array and a peripheral circuit coupled to the memory array; the memory array comprises a plurality of phase change memory cells; The peripheral circuit is configured to control operations on the plurality of phase change memory cells; The operation method further includes: A first current provided to the selected phase change memory cell is determined according to a distance between the selected phase change memory cell and the peripheral circuit, wherein the farther the selected phase change memory cell is from the peripheral circuit, the smaller the first current provided to the selected phase change memory cell is; and the closer the selected phase change memory cell is to the peripheral circuit, the larger the first current provided to the selected phase change memory cell is.

6. The operating method according to claim 2, characterized in that: The setting degree of the selected phase change memory cell by the first current is not greater than the setting degree of the selected phase change memory cell by the setting current; wherein the setting degree is used to measure the degree to which a region in a phase change material layer of a phase change memory cell is transformed from an amorphous phase to a crystalline phase under the action of a certain current.

7. The operating method according to claim 3, characterized in that: The first current and the second current are controlled by a current mirror coupled to the selected phase-change memory cell.

8. The operating method according to claim 3, characterized in that: The duration of the second current is determined by a read speed of the phase change memory, wherein the faster the read speed is, the shorter the duration of the second current is.

9. The operating method according to claim 1, characterized in that: The operation method also includes: When the read operation is performed on the selected phase change memory cell; a first voltage is applied to the word line coupled to the selected phase change memory cell, so that the bit line coupled to the selected phase change memory cell is in a floating state, a second voltage is applied to all unselected word lines belonging to the same storage array block as the selected phase change memory, and a third voltage is applied to all unselected bit lines belonging to the same storage array block as the selected phase change memory; under the action of the first voltage, the second voltage, and the third voltage, the voltage difference applied to the bit line and the word line corresponding to the selected phase change memory cell is greater than the threshold voltage of the selector of the selected phase change memory cell, and the voltage difference applied to the bit line and the word line corresponding to all unselected phase change memory cells in the storage array block is less than a preset voltage; the preset voltage is less than the threshold voltage.

10. A phase change memory, characterized in that: include: a plurality of memory array blocks, each memory array block comprising a plurality of phase change memory cells; and a peripheral circuit coupled to the plurality of phase change memory cells; wherein, The peripheral circuit is configured to: after performing a read operation on a selected phase change memory cell among the plurality of phase change memory cells, perform a weak write operation on the selected phase change memory cell, wherein the weak write operation is used to restore a region in the phase change material layer of the selected phase change memory cell that is transformed into an amorphous phase due to read disturbance to a crystalline phase; Wherein, the peripheral circuit is further configured to: determine whether the number of times the read operation is currently executed is less than a preset number; if it is determined that the number of times the read operation is currently executed is not less than the preset number, perform a weak write operation on the selected phase change memory unit; if it is determined that the number of times the read operation is currently executed is less than the preset number, do not perform a weak write operation on the selected phase change memory unit.

11. The phase change memory according to claim 10, characterized in that: The peripheral circuit is further configured to: provide a first current to the selected phase change memory cell; the first current is smaller than a reset current; the reset current is used to transform the entire region of the phase change material layer included in the phase change memory cell from a crystalline phase to an amorphous phase.

12. The phase change memory according to claim 11, characterized in that: The peripheral circuit is further configured to: before performing the weak write operation on the selected phase change memory cell, provide a second current to the selected phase change memory cell so that the selector of the selected phase change memory cell is continuously in the on state.

13. The phase change memory according to claim 12, characterized in that: The peripheral circuit is also configured as follows: when performing the read operation on the selected phase change memory cell; applying a first voltage to the word line coupled to the selected phase change memory cell, so that the bit line coupled to the selected phase change memory cell is in a floating state, applying a second voltage to all unselected word lines belonging to the same storage array block as the selected phase change memory, and applying a third voltage to all unselected bit lines belonging to the same storage array block as the selected phase change memory; under the action of the first voltage, the second voltage, and the third voltage, the voltage difference between the bit line and the word line corresponding to the selected phase change memory cell is greater than the threshold voltage of the selector of the selected phase change memory cell, and the voltage difference between the bit line and the word line corresponding to all unselected phase change memory cells in the storage array block is less than a preset voltage; the preset voltage is less than the threshold voltage.

14. A memory system, characterized in that: include: The phase change memory as claimed in one or more claims 10 to 13 and a memory controller coupled to the phase change memory.

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