Method for detecting and repairing failed cells of a memory chip

Abstract

The application discloses a failure unit detection and repair method of a memory chip, comprising the following steps: detecting the memory chip; if there is a failure unit, obtaining the failure row address line / failure column address line of the detected first failure unit; setting the failure row address line / failure column address line so that it can be identified as a valid row address line / valid column address line; detecting the memory chip after the setting process; determining whether there is still other failure unit; if yes, obtaining the column address line / row address line where the first failure unit is located, replacing the failure column address line / failure row address line with a column address redundant line / row address redundant line, and then turning to the detection of the memory chip; otherwise, replacing the failure row address line / failure column address line with a row address redundant line / column address redundant line. The method of the application is more efficient in the detection and repair of the failure unit, has higher accuracy, consumes less time, and reduces the process time cost.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a method for detecting and repairing failed units of a memory chip. BACKGROUND

[0002] Generally, a wafer test machine is used to repair failed units. The wafer test machine is provided with an MRA (Memory Redundancy Analyzer) in order to replace failed units with valid units. The MRA is provided with a large-capacity DRAM or SRAM storage module. In contrast, in order to check valid / failed units after packaging and repair the failed units, although a DRAM memory can be tested, a detailed redundancy analysis cannot be performed as flexibly as the wafer test machine using the MRA in a package test machine or various servers or personal computers used by end users, and application devices such as mobile phones. In the prior art, when the test machine detects a failed unit, only the row address line where the failed unit is located is replaced with a row address redundancy line, but if the failed units are located on the same column address line, only replacing the row address line where the failed unit is located with a row address redundancy line cannot replace all the failed units at one time, and subsequent detection and replacement operations are required. Therefore, the prior art has low accuracy in detecting and repairing failed units, and is time-consuming and inefficient. SUMMARY

[0003] The purpose of the present disclosure is to provide a method for detecting and repairing failed units of a memory chip. To have a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not a general review, nor is it intended to determine key / important components or delineate the scope of protection of these embodiments. Its only purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0004] According to an aspect of an embodiment of the present disclosure, a method for detecting and repairing failed units of a memory chip is provided, comprising:

[0005] detecting the memory chip to obtain a first detection result; the memory chip has a plurality of row address redundancy lines and a plurality of column address redundancy lines;

[0006] if it is determined according to the first detection result that there is a failed unit, for the detected first failed unit, obtaining a failed row address line / failed column address line according to a rectangular coordinate system previously established on the memory chip; the failed row address line / failed column address line is the row address line / column address line where the first failed unit is located;

[0007] The invalid row address line / invalid column address line is set so that the set invalid row address line / invalid column address line can be identified as a valid row address line / valid column address line;

[0008] The memory chip after the setting processing is detected to obtain a second detection result;

[0009] It is determined according to the second detection result whether there is still another invalid unit;

[0010] If yes, the invalid column address line / invalid row address line is obtained, the invalid column address line / invalid row address line is replaced by the column address redundancy line / row address redundancy line, and the memory chip is detected again;

[0011] If no, the invalid row address line / invalid column address line is replaced by the row address redundancy line / column address redundancy line.

[0012] One of the aspects of the embodiments of the present disclosure can include the following beneficial effects:

[0013] The invalid unit detection and repair method of the memory chip provided by the embodiments of the present disclosure sets the invalid row address line / invalid column address line so that it can be identified as a valid row address line / valid column address line, and then the chip is detected again, if there is still another invalid unit, the invalid column address line / invalid row address line is replaced by a column address redundancy line / row address redundancy line, and then the chip is detected again, if there is no other invalid unit, the invalid row address line / invalid column address line is replaced by a row address redundancy line / column address redundancy line, so that the detection and repair efficiency of the invalid unit is higher, the accuracy is higher, the time consumption is less, and the process time cost is reduced.

[0014] Other features and advantages of the present disclosure will be described in the following description, and some will become apparent from the description, or can be learned from the description, or can be determined without doubt from the description, or can be understood by implementing the embodiments of the present disclosure. The purpose and other advantages of the present disclosure can be achieved and obtained by the structure specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments described in the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without creating any creative labor.

[0016] Figure 1A flowchart of a method for detecting and repairing faulty cells in a memory chip according to one embodiment of this application is shown;

[0017] Figure 2 This application illustrates a memory chip with faulty cells in one embodiment;

[0018] Figure 3 A memory chip with a faulty cell is shown in another embodiment of this application;

[0019] Figure 4 A memory chip with a faulty cell is shown in another embodiment of this application;

[0020] Figure 5 A flowchart of a method for detecting and repairing faulty cells in a memory chip according to another embodiment of this application is shown. Detailed Implementation

[0021] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0022] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0023] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various objects, but these objects are not limited by these terms. These terms are only used to distinguish one object from another.

[0024] Determining whether to repair using row or column address redundancy lines is a crucial step in wafer testing or packaging testing. When redundancy analysis is not readily available, redundancy lines are used to more effectively determine whether a failed address is a row or column address. Whether it's a packaging tester, server, personal computer, or mobile phone, all products are designed with DRAM failure cells that can be repaired. All application products, including packaging testers, unconditionally repair failure cells only in the row address direction. If a failure in the column address direction results in multiple bits, the row address is insufficient for adequate repair, and the chip will be permanently failed. If column address repair is also necessary, the column address redundancy prepared for the failed column address is used first to repair the failed cell. Then, the remaining failure cells are effectively repaired using redundant row addresses in the row address direction. After the wafer tester repairs the failure cell, the packaging tester repairs it in the row address direction upon detecting the failure cell.

[0025] like Figure 1 As shown, the first embodiment of this application provides a method for detecting and repairing faulty cells in a memory chip, including:

[0026] S10. Test the memory chip and obtain the first test result.

[0027] Multiple memory chips can be simultaneously tested using a testing machine according to various specified modes. The memory chips are rectangular and have several row and column address redundancy lines. During testing, hundreds of memory chips can be tested simultaneously using a packaging testing machine, saving production and time costs. To detect failures caused by various reasons, multiple memory chips can be tested using various preset specified modes.

[0028] S20. Based on the first test result, if the tester cannot detect any failed units on the entire memory chip, the test ends.

[0029] Otherwise, for the first failed cell detected by the test machine, the failed row address line is obtained according to the Cartesian coordinate system pre-established on the memory chip; the failed row address line is the row address line where the first failed cell is located, that is, the row address line where the row address of the first failed cell is located. The row address of the first failed cell is stored. The row address is also called the X address, and the column address is also called the Y address. The row address line is also called the X address line, that is, the address line perpendicular to the X-axis; the column address line is also called the Y address line, that is, the address line perpendicular to the Y-axis. The two coordinate axes of the pre-established Cartesian coordinate system are parallel to the two sides of the memory chip, respectively. Failed cells may randomly occur in the row address direction or the column address direction.

[0030] The first failure unit refers to one of all the failure units detected. The term "first" is not intended to be limiting; it is only used to distinguish the first failure unit from other failure units.

[0031] S30. Set the invalid row address line so that the set invalid row address line can be recognized as a valid row address line by the test machine.

[0032] Specifically, the array of electronically programmable fuses unique to the failed row address lines can be simulated as broken, thus simulating the failed row address lines as valid row address lines in the testing machine. This ensures that the failed row address lines can be recognized as valid row address lines by the testing machine during subsequent testing. An electronically programmable fuse (E-FUSE) is a non-volatile memory cell that allows information to be programmed and stored on a chip.

[0033] S40. The memory chip after the settings process in step S20 is tested by a testing machine to obtain the test results.

[0034] Specifically, the memory chip after the settings process in step S20 is tested by a tester according to a variety of specified modes to obtain a second test result.

[0035] S50. Determine whether there are other failed units based on the second detection result.

[0036] S60. If other failed units still exist, obtain the column address line where the first failed unit is located, replace the column address line where the first failed unit is located with the column address redundancy line, and proceed to S10.

[0037] The column address line where the first failed cell is located is also called the failed column address line, which is the column address line where the column address of the first failed cell is located. Row address redundancy lines or column address redundancy lines are additional cell combinations prepared to replace the row address line or column address line where the failed cell is located.

[0038] S70. If there are no other failed units, it can be determined that all failed units on the memory chip are located on the above-mentioned failed row address lines, and the failed row address lines are replaced by row address redundancy lines.

[0039] In some implementations, to ensure higher detection and repair accuracy, after completing S70, the method further includes: S80, proceeding to S10. Proceeding to S10 to perform another detection on the memory chip can improve detection accuracy and avoid missing failed cells.

[0040] In some embodiments, before obtaining the failed row address line according to a pre-established Cartesian coordinate system on the memory chip, the method for detecting and repairing failed cells in the memory chip further includes: S20', establishing a Cartesian coordinate system on the memory chip to determine the coordinates of the failed cells; the Cartesian coordinate system includes an X-axis and a Y-axis, which are parallel to two sides of the memory chip, respectively. The cell coordinates include a row address and a column address. The row address is the cell's coordinate on the X-axis, also called the X address; the column address is the cell's coordinate on the Y-axis, also called the Y address. All cells on the same X address line have the same X coordinate, and all cells on the same Y address line have the same Y coordinate.

[0041] Specifically, establishing a Cartesian coordinate system on the memory chip includes: using the vertex of one corner of the memory chip as the origin, and using the two sides containing the origin as the horizontal and vertical axes, respectively. For example, the lower left corner of the memory chip can be used as the origin, the straight line containing the left side of the memory chip as the Y-axis, and the straight line containing the lower side of the memory chip as the X-axis.

[0042] In some embodiments, before setting the failed row address line, the method further includes storing the row address of the first failed unit; replacing the failed row address line with a row address redundancy line includes: selecting a row address redundancy line, finding the failed row address line according to the stored row address of the first failed unit, and replacing the failed row address line with the selected row address redundancy line.

[0043] In some implementations, column address redundancy lines or row address redundancy lines can be used to break the corresponding array electronic programmable fuses, thereby restoring failed cells to valid cells. For example, if a failed cell is known to exist at row address n, this row address can be designed so that the tester can identify this row address (all cells with the same X coordinate) as valid. After performing a preset mode test, if the test result is valid, it means that all failed cells have the same row address, and only cells at that row address need to be replaced. However, if the row address is designed so that the tester can identify it as valid, and after performing a preset mode test, the result still shows the existence of a failed cell, it means that other failed cells are located at the same column address. Therefore, in this case, replacing the column address is more efficient. Replacing the row address would require multiple steps.

[0044] like Figure 2In the illustrated implementation, the lower left corner of the memory chip is taken as the origin (0,0), the straight line containing the left side of the memory chip is taken as the Y-axis, and the straight line containing the lower side of the memory chip is taken as the X-axis. The memory chip 170 includes a main region 175, a row address redundancy line 172, and a column address redundancy line 173. The column address redundancy line 173 is located directly below the main region 175, and its length in the X-direction is the same as that of the main region 175. The row address redundancy line 172 is located to the left of the main region 175, and its length in the Y-direction is the same as that of the main region 175. There are multiple failed units on the main region 175, namely failed unit 171, failed unit 176, failed unit 177, and failed unit 178. Failed units 171, 176, 177, and 178 are located on the same row address line 174, so the row address line 174 is also called the failed row address line 174.

[0045] The memory chip 170 is tested using a testing machine. For the first failed cell detected by the testing machine, such as failed cell 171, the failed row address line 174 is obtained according to a pre-established Cartesian coordinate system on the memory chip 170. The failed row address line 174 is set so that it can be recognized as a valid row address line by the testing machine. The testing machine tests the memory chip after the setting process according to a specified mode to obtain the test results. Based on the test results, it is determined whether there are any other failed cells. Figure 2 All failed cells (failed cells 171, 176, 177, and 178) are located on the same row address line 174. Row address line 174 is replaced using a row address redundancy line to obtain the repaired memory chip 170. To ensure detection and repair accuracy and avoid missing any failed cells, after replacing row address line 174 with the row address redundancy line, the process can be repeated using a testing machine until the testing machine detects no failed cells on the entire memory chip.

[0046] like Figure 3In the illustrated embodiment, the memory chip 180 includes a main region 185, a row address redundancy line 182, and a column address redundancy line 183. The column address redundancy line 183 is located directly below the main region 185, and its length in the X direction is the same as that of the main region 185. The row address redundancy line 182 is located to the left of the main region 185, and its length in the Y direction is the same as that of the main region 185. Multiple faulty cells exist on the main region 185, namely faulty cell 181, faulty cell 186, faulty cell 187, and faulty cell 188. Faulty cells 181, 186, 187, and 188 are located on the same column address line 184, therefore, column address line 184 is also called faulty column address line 184.

[0047] The memory chip 180 is tested using a testing machine. For the first failed cell detected by the testing machine, such as failed cell 181, the failed column address line 184 is obtained according to a pre-established Cartesian coordinate system on the memory chip 180. The failed column address line 184 is configured so that it can be recognized as a valid column address line by the testing machine. The testing machine tests the configured memory chip according to a specified mode to obtain the test results. Based on the test results, it is determined whether there are any other failed cells. Figure 3 All failed cells (failed cells 181, 186, 187, and 188) are located on the same column address line 184. Column address line 184 is replaced using a column address redundancy line to obtain a repaired memory chip 180. To ensure detection and repair accuracy and avoid missing any failed cells, after replacing column address line 184 with the column address redundancy line, the process can be repeated using a testing machine until the testing machine detects no failed cells on the entire memory chip.

[0048] like Figure 4In the illustrated embodiment, the memory chip 170 includes a main region 175, a row address redundancy line 172, and a column address redundancy line 173. The column address redundancy line 173 is located directly below the main region 175, and its length in the X direction is the same as that of the main region 175. The row address redundancy line 172 is located to the left of the main region 175, and its length in the Y direction is the same as that of the main region 175. Multiple faulty units exist on the main region 175, namely faulty unit 171, faulty unit 176, faulty unit 177, faulty unit 178, faulty unit 181, faulty unit 186, faulty unit 187, and faulty unit 188. Faulty units 171, 176, 177, and 178 are located on the same row address line 174, and faulty units 181, 186, 187, and 188 are located on the same column address line 184.

[0049] The memory chip is tested using a testing machine. For the first failed cell detected by the testing machine, such as failed cell 181, the failed column address line 184 is obtained according to a pre-established Cartesian coordinate system on the memory chip 170. The failed column address line 184 is configured so that it can be recognized as a valid column address line by the testing machine. The testing machine tests the configured memory chip according to a specified mode to obtain the test results. Based on the test results, it is determined whether there are any other failed cells. Figure 4 In addition to the failed cell on the failed column address line 184, there are other failed cells (i.e., failed cells located on the failed row address line 174). Obtain the row address line where the failed cell 181 is located, replace the row address line where the failed cell 181 is located with the row address redundancy line, and then switch to the test machine to test the memory chip until the test machine can no longer detect any failed cells on the entire memory chip.

[0050] The method in this embodiment makes the detection and repair of failed units more efficient and accurate, less time-consuming, and reduces process time costs.

[0051] like Figure 5 As shown, a second embodiment of this application provides a method for detecting and repairing faulty cells in a memory chip, including:

[0052] S1. Test the memory chip and obtain the first test result.

[0053] S2. Based on the first test result, if the tester does not detect any faulty cells on the entire memory chip, the test ends.

[0054] Otherwise, for the first failed cell detected by the test machine, the failed column address line is obtained according to a pre-established Cartesian coordinate system on the memory chip; the failed column address line is the column address line where the first failed cell is located, that is, the column address line where the column address of the first failed cell is located. The two coordinate axes of the pre-established Cartesian coordinate system are parallel to the two sides of the memory chip.

[0055] Unlike the first embodiment, in this embodiment, for the first failure unit, the corresponding failure column address line is obtained.

[0056] S3. Set the failed column address lines so that the set failed column address lines can be recognized as valid column address lines by the test machine.

[0057] Specifically, the array electronic programmable fuse unique to the failed column address line can be simulated as broken, thereby simulating the failed column address line as a valid column address line in the tester, so that the failed column address line can be recognized as a valid column address line by the tester in subsequent testing.

[0058] S4. The memory chip after the settings and processing in step S2 is tested by a testing machine to obtain the second test result.

[0059] Specifically, the memory chip after the settings in step S2 is tested by a testing machine according to various specified modes to obtain a second test result.

[0060] S5. Determine whether there are other failed units based on the second test result.

[0061] S6. If other failed units still exist, obtain the row address line where the first failed unit is located, replace the row address line where the first failed unit is located with the row address redundancy line, and return to S1. The row address line where the first failed unit is located is the failed row address line.

[0062] S7. If there are no other failed units, then all failed units on the memory chip are determined to be located on the above-mentioned failed column address lines, and the failed column address lines are replaced with column address redundancy lines.

[0063] In some implementations, to ensure higher detection and repair accuracy, after completing S7, the method further includes: S8, switching to S1. Switching to S1 to perform another detection on the memory chip can improve detection accuracy and avoid missing failed cells.

[0064] In some embodiments, before obtaining the failure column address line according to a pre-established Cartesian coordinate system on the memory chip, the failure cell detection and repair method of the memory chip further includes: S2', establishing a Cartesian coordinate system on the memory chip to determine the coordinates of the failure cell; the Cartesian coordinate system includes an X-axis and a Y-axis, the X-axis and Y-axis being parallel to two sides of the memory chip respectively.

[0065] In some embodiments, before setting the failed column address line, the method further includes storing the column address of the first failed unit; replacing the failed column address line with a column address redundancy line includes: selecting a column address redundancy line, finding the failed column address line according to the stored column address of the first failed unit, and replacing the failed column address line with the selected column address redundancy line.

[0066] The memory chip failure cell detection and repair method provided in this disclosure sets failure row address lines / failure column address lines so that they can be identified as valid row address lines / valid column address lines. Then, the chip is detected. If other failure cells still exist, a column address redundancy line / row address redundancy line is used to replace the failure column address line / failure row address line. The chip is then detected again. If no other failure cells exist, a row address redundancy line / column address redundancy line is used to replace the failure row address line / failure column address line. This makes the failure cell detection and repair more efficient and accurate, less time-consuming, and reduces process time costs.

[0067] Although each implementation method has been described separately in the above description, this does not mean that the measures in each implementation method cannot be used in combination advantageously.

[0068] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for detecting and repairing failed units of a memory chip, the method comprising: The method comprises the following steps: detecting the memory chip to obtain a first detection result; the memory chip has a plurality of row address redundancy lines and a plurality of column address redundancy lines; if it is determined according to the first detection result that there is a failed unit, then for the detected first failed unit, the failed row address line or the failed column address line is obtained according to a rectangular coordinate system previously established on the memory chip; the failed row address line or the failed column address line is the row address line or the column address line where the first failed unit is located; the failed row address line or the failed column address line is set so that the failed row address line or the failed column address line after being set can be identified as a valid row address line or a valid column address line; detecting the memory chip after the setting to obtain a second detection result; determining whether there is still another failed unit according to the second detection result; if yes, then the failed column address line or the failed row address line is obtained, the failed column address line or the failed row address line is replaced by one of the column address redundancy lines or the row address redundancy lines, and the detection of the memory chip is performed again; if no, then the failed row address line or the failed column address line is replaced by one of the row address redundancy lines or the column address redundancy lines.

2. The method of claim 1, wherein, The method further comprises: if it is determined according to the first detection result that no failed unit is detected on the whole memory chip, then the detection is ended.

3. The method of claim 2, wherein, After the failed row address line or the failed column address line is replaced by one of the row address redundancy lines or the column address redundancy lines, the method further comprises: returning to the detection of the memory chip.

4. The method of claim 1, wherein, Before the failed row address line or the failed column address line is obtained according to the rectangular coordinate system previously established on the memory chip, the method further comprises: establishing a rectangular coordinate system with a vertex of one corner of the memory chip as an origin and two sides where the origin is located as a horizontal axis and a vertical axis respectively.

5. The method of claim 1, wherein, The detection of the memory chip comprises: simultaneously detecting a plurality of memory chips by a testing machine.

6. The method of claim 1, wherein, The detection of the memory chip comprises: simultaneously detecting a plurality of memory chips by a testing machine in a plurality of specified modes.

7. The method according to claim 5 or 6, characterized in that, The setting of the failed row address line or the failed column address line so that the failed row address line or the failed column address line after being set can be identified as a valid row address line or a valid column address line by a testing machine comprises: setting an array electronic programmable fuse unique to the failed row address line or the failed column address line to a broken state, and simulating the failed row address line or the failed column address line as a valid row address line or a valid column address line in the testing machine, so that in subsequent detection, the failed row address line or the failed column address line can be identified as a valid row address line or a valid column address line by the testing machine.

8. The method of claim 5, wherein, The detection of the memory chip after the setting comprises: detecting the memory chip after the setting by the testing machine in a plurality of specified modes.

9. The method of claim 1, wherein, Before the failed row address line or the failed column address line is set, the method further comprises: storing the row address or the column address of the first failed unit.

10. The method of claim 9, wherein, The replacing the failed row address line or the failed column address line by the row address redundant line or the column address redundant line comprises: selecting a row address redundant line or a column address redundant line, finding the failed row address line or the failed column address line according to the stored row address or column address of the first failed unit, and replacing the failed row address line or the failed column address line by the selected row address redundant line or column address redundant line.

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