A flexible graphene field effect transistor and preparation method thereof

Abstract

The present invention relates to the technical field of flexible transistor processing, and specifically to a method for preparing a flexible graphene field effect transistor, comprising coating a thin film on a silicon substrate, and forming an aluminum oxide dielectric layer on the thin film to obtain a substrate; preparing a first electrode on the aluminum oxide dielectric layer; forming a gate dielectric layer on the substrate obtained above, the gate dielectric layer covers the first electrode, and processing a second electrode on the gate dielectric layer, the first electrode and the second electrode are not connected to each other; forming a graphene layer on the substrate by a stamp method, and patterning the graphene to expose the second electrode; the graphene is used to connect the first electrode and the second electrode to obtain a graphene device; the graphene device obtained above is peeled off from the silicon substrate, thereby obtaining a graphene field effect transistor with a flexible substrate. The flexible graphene field effect transistor and the preparation method can improve the density of the transistor under unit thickness, and the preparation process is simple and the cost is low.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor manufacturing, and in particular to a flexible graphene field effect transistor and a preparation method thereof. Background Art

[0002] Graphene is a single-layer planar two-dimensional crystalline material formed by carbon atoms arranged in a hexagonal honeycomb. Its atomic layer thickness is only 0.34nm, making it the thinnest crystalline material known to date. Graphene's unique two-dimensional crystal structure determines its unique physical properties, including: single-layer atomic thickness, ultra-high carrier mobility, thermal conductivity, high strength and toughness. Today, with the continuous development of flexible electronic devices, graphene, as a two-dimensional material with excellent electrical and mechanical properties, has become an ideal material for the preparation of flexible electronic devices.

[0003] Graphene field effect transistor electronic devices based on flexible materials have attracted great attention from researchers due to their excellent performance. At present, most researchers use PEN films and water-soluble molecular films, and the water-soluble molecules are one or more of polyvinyl alcohol, polyacrylic acid and glucose; most flexible substrates are relatively thick, and few transistors can be integrated within the unit thickness. Summary of the invention

[0004] In order to overcome one of the deficiencies of the prior art, an object of the present invention is to provide a flexible graphene field effect transistor and a preparation method thereof, which can increase the density of the transistor per unit thickness.

[0005] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0006] A method for preparing a flexible graphene field effect transistor, comprising:

[0007] S100: coating a thin film on the silicon substrate and forming an aluminum oxide dielectric layer on the thin film to obtain a substrate;

[0008] S200: preparing a first electrode on the aluminum oxide dielectric layer;

[0009] S300: forming a gate dielectric layer on the substrate obtained in step S200, wherein the gate dielectric layer covers the first electrode, and processing a second electrode on the gate dielectric layer, wherein the first electrode and the second electrode are not connected to each other;

[0010] S400: transferring a graphene layer on a substrate by a stamp method, and patterning the graphene to expose a second electrode; the graphene is used to connect the first electrode and the second electrode to obtain a graphene device;

[0011] S500: peeling the graphene device obtained in step S400 from the substrate silicon, thereby obtaining a graphene field effect transistor with a flexible substrate.

[0012] Furthermore, the S400 more specifically includes the following steps:

[0013] S410: spin coating a PMMA solution on one side of the graphene on the copper foil to obtain a combination of PMMA layer / graphene / copper foil in the order of PMMA layer / graphene;

[0014] S420: Adhere and press the assembly 1 on a glass slide by PDMS glue on one side of the PMMA layer, and remove the copper foil to obtain an assembly 2 in the order of glass slide / PDMS layer / PMMA layer / graphene;

[0015] S430: rolling the second assembly located on the graphene side onto the substrate obtained in step S300 on one side of the first electrode, with the second assembly covering the first electrode and the second electrode; the heating temperature of the substrate obtained in step S300 is 160-180° C., and the rolling time is 0.5-4 min; removing the glass slide and the PDMS layer on the second assembly;

[0016] S440: Remove the PMMA layer with acetone, then clean it with isopropyl alcohol, and then rinse it with deionized water; Al2O3

[0017] S450: applying glue on the graphene and performing photolithography to obtain graphene patterned channels, developing, and then using plasma to knock off excess graphene to obtain a graphene device.

[0018] Further, step S420 more specifically includes the following steps:

[0019] S421: coating PDMS glue on one side of the assembly located on the PMMA layer;

[0020] S422: Adhere the glass slide to the PDMS glue and press it;

[0021] S423: Place the assembly obtained in the above step S422 into APS100 etching solution to etch away the copper foil, wash with deionized water and blow dry to obtain assembly 2 of glass slide / PDMS layer / PMMA layer / graphene in the order of the above.

[0022] Furthermore, in step S410, the copper foil graphene is obtained by growing graphene on copper foil by a CVD method.

[0023] Furthermore, the specific operation steps of step 300 include:

[0024] Forming an aluminum oxide gate dielectric layer on the side of the substrate located at the first electrode by using an ALD atomic layer deposition coating method;

[0025] Performing a mask photolithography experiment on the aluminum oxide gate dielectric layer to obtain a patterned channel of the second electrode;

[0026] The second electrode is evaporated on the substrate by thermal evaporation to form an Au / Cr metal layer, and the thermally evaporated Au / Cr layer forms the second electrode in the patterned channel of the second electrode; then after the second electrode is formed, the part with the photoresist is removed using an NMP solution to reveal the first electrode, and the first electrode and the second electrode are not connected to each other.

[0027] Furthermore, the temperature of the NMP solution when removing the portion with the photoresist is 80-90° C., and the removal time is 8-12 minutes.

[0028] Furthermore, the specific operation of the mask lithography experiment is: spin coating LOR5A glue on the aluminum oxide gate dielectric layer, then spin coating AZ5214 glue, and then photolithography exposure and development to obtain the desired pattern.

[0029] Furthermore, the specific operations of step S200 are:

[0030] Spin-coat LOR5A glue on the alumina dielectric layer, then spin-coat AZ5214 glue, then perform photolithography exposure and development to obtain the desired pattern;

[0031] A magnetron sputtering machine is used to sputter the side of the substrate with the pattern to form a Ti / Al metal layer;

[0032] The portion with the photoresist is removed by using an NMP solution to obtain a first electrode.

[0033] Furthermore, the film is a PI film, and the thickness of the film is 10-25 μm.

[0034] A graphene field effect transistor on a flexible substrate is prepared by adopting the preparation method of the flexible graphene field effect transistor.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] A method for preparing a flexible graphene field effect transistor of the present invention utilizes PI film as a substrate material, which can greatly improve flexibility, so that the transistor formed later has greater flexibility, and the PI film can greatly improve the working ability of the entire device under high temperature conditions, and ensure the stability of the work. Using graphene to connect different electrodes can effectively reduce the thickness of the connection, so that the thickness of the entire substrate is reduced, and the effect of high transistor density is achieved under the condition of unit thickness. In this application, aluminum oxide is used as a dielectric layer, which can more easily control the operation of the channel through the gate voltage. Its high dielectric constant also effectively improves the mobility of holes and electron carriers, and improves the conductivity of the device. In addition, the role of graphene not covering the second electrode is to cover the graphene on the first electrode, thereby connecting the second electrode, thereby realizing the production of a flexible graphene field effect transistor GFET device.

[0037] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic diagram of a flow chart of an embodiment of the present invention;

[0039] FIG2( a) is a cross-sectional view of the structure of a substrate in an embodiment of the present invention;

[0040] FIG2( b ) is a cross-sectional view of a structure in which a first electrode is formed on a substrate in an embodiment of the present invention;

[0041] FIG2( c ) is a cross-sectional view of a structure in which a second electrode is formed on a substrate in an embodiment of the present invention;

[0042] FIG2( d ) is a cross-sectional view of a structure in which graphene is formed on a substrate in an embodiment of the present invention;

[0043] FIG2( e ) is a cross-sectional view of the structure of a graphene field effect transistor in an embodiment of the present invention;

[0044] Figure 3 is a flow chart of the principle of transferring graphene to a substrate in an embodiment of the present invention;

[0045] Figure 4 Schematic diagram of the structure of the graphene field effect transistor in an embodiment of the present invention.

[0046] Description of the accompanying drawings: substrate silicon 1, thin film 2, aluminum oxide dielectric layer 3, first electrode 4, aluminum oxide gate dielectric layer 5, second electrode 6, graphene layer 7, photoresist layer 8, Ti / Al metal layer 9, Au / Cr metal layer 10 DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0048] See also Figures 1 to 3 The present application provides a method for preparing a flexible graphene field effect transistor, comprising:

[0049] S100: coating a thin film 2 on a silicon substrate 1, and forming an aluminum oxide dielectric layer 3 on the thin film 2 to obtain a substrate;

[0050] S200: preparing a first electrode 4 on the aluminum oxide dielectric layer 3;

[0051] S300: forming an aluminum oxide gate dielectric layer 5 on the substrate obtained in step S200, the aluminum oxide gate dielectric layer 5 covers the first electrode 4, and processing a second electrode 6 on the aluminum oxide gate dielectric layer 5, the first electrode 4 and the second electrode 6 are not connected to each other;

[0052] S400: transferring a graphene layer 7 on a substrate by a stamp method, and patterning the graphene layer 7 to expose the second electrode 6; the graphene layer 7 is used to connect the first electrode 4 and the second electrode 6 to obtain a graphene device;

[0053] S500: peeling the graphene device obtained in step S400 from the silicon substrate 1, thereby obtaining a graphene field effect transistor with a flexible substrate.

[0054] See also Figure 2(a) to Figure 2(e) In the above step S100, the film 2 serves as the substrate of the entire structure, and the film 2 is a PI film, and the thickness of the film 2 is 10-25 μm. Such a design can effectively reduce the thickness of the transistor substrate, and then multiple devices can be integrated in the Z direction, and the high density of transistors can be achieved under the condition of unit thickness. In addition, the PI film can withstand a high temperature of 400°C, and such performance gives the entire transistor the possibility of stable operation at high temperatures. In addition, the PI film has a certain flexibility, and such performance makes the entire transistor flexible, which is convenient for different usage scenarios. In this application, silicon is used as a substrate, which is convenient for the molding of the PI film, while providing corresponding performance, such as rigidity, so as to facilitate the molding of the aluminum oxide dielectric layer 3 on the PI film in the later steps.

[0055] It should be noted that in the present application, the aluminum oxide dielectric layer 3 is covered with a layer of aluminum by ALD atomic layer deposition, and then left for one day for oxidation to obtain the aluminum oxide dielectric layer 3. The thickness of the aluminum oxide dielectric layer 3 in the present application is 50-150 nm.

[0056] Referring to FIG. 2( b ), further in one embodiment, in order to more easily explain step S200, the specific operation of step S200 is:

[0057] Spin-coat LOR5A glue on the alumina dielectric layer 3, and then spin-coat AZ5214 glue to obtain a photoresist layer 8, and then perform photolithography exposure and development to obtain a desired pattern;

[0058] A magnetron sputtering machine is used to sputter the side of the substrate with the pattern to form a Ti / Al metal layer 9;

[0059] The portion with the photoresist layer 8 is removed using an NMP solution to obtain the first electrode 4 .

[0060] The first electrode 4 is a titanium-aluminum electrode, which is divided into a titanium layer and an aluminum layer, and the thickness ratio of the titanium layer to the aluminum layer is 1:30-50.

[0061] It should be supplemented that the pattern obtained by photolithography exposure and development on the aluminum oxide dielectric layer 3 is actually the pattern of the first electrode 4 .

[0062] Referring to FIG. 2( c ), in an improved embodiment of the present application, in order to more easily explain step S300 , the specific operation steps of step S300 include:

[0063] S310: forming an aluminum oxide gate dielectric layer 5 on one side of the substrate located at the first electrode 4 by using an ALD atomic layer deposition coating method;

[0064] S320: performing a mask photolithography experiment on the aluminum oxide gate dielectric layer 5 to obtain a patterned channel of the second electrode 6;

[0065] S330: The second electrode 6 is evaporated on the substrate by a thermal evaporation method to form a Au / Cr metal layer 10, and the thermally evaporated Au / Cr metal layer 10 forms the second electrode 6 in the patterned channel of the second electrode 6; then after the second electrode 6 is formed, the portion with the photoresist layer 8 is removed by using an NMP solution to reveal the first electrode 4, and the first electrode 4 and the second electrode 6 are not connected to each other.

[0066] Among them, ALD atomic layer deposition coating is a more common method, which is not described in detail in this application. In the above-mentioned step S300, covering the gate dielectric layer 5 on the first electrode 4 can prevent the subsequently formed graphene layer 7 from directly contacting the photoresist layer 8 remaining after the photolithography process of the first electrode 4, and the high-quality conductivity of the graphene layer 7 can be guaranteed by covering. The above-mentioned thermal evaporation processing technology is a conventional processing technology, and this application will not be described in detail here. In addition, the main purpose of selecting the aluminum oxide gate dielectric layer 5 is the same as the function of the above-mentioned aluminum oxide dielectric layer 3, which is not described in detail in this application. The thickness of the aluminum oxide gate dielectric layer 5 is selected to be 20-40nm, which is smaller than the thickness of the above-mentioned aluminum oxide dielectric layer 3. The main purpose of such a design is to facilitate reducing the distance between the first electrode 4 and the second electrode 6, that is, the thickness of the graphene layer 7, and thus can reduce the thickness of the transistor as a whole.

[0067] It should be noted that the second electrode 6 is actually an Au / Cr electrode, which is divided into a gold layer and a chromium layer, and the thickness ratio of the gold layer to the chromium layer is 1:10-12. Gold and chromium have good electrical conductivity as electrodes and are excellent materials for the second electrode 6. In addition, in actual processing, the thickness of the second electrode 6 is greater than or equal to the thickness of the first electrode 4, which is convenient for later welding.

[0068] In one embodiment of the present application, the temperature of the NMP solution when removing the portion with the photoresist layer 8 is 80-90°C, and the removal time is 8-12 minutes, wherein the preferred heating temperature is 85°C and the removal time is 10 minutes, so that the photoresist layer 8 adhered to the above-mentioned aluminum oxide gate dielectric layer 5 can be quickly and cleanly removed.

[0069] In one embodiment of the present application, the mask lithography experiment is specifically operated as follows: spin coating LOR5A glue on the aluminum oxide gate dielectric layer 5, then spin coating AZ5214 glue, and then photolithography exposure and development to obtain the desired pattern. In the above step S320, the desired pattern is the graphic pattern of the second electrode 6.

[0070] See further Figure 2(d) and Figure 3 , the S400 more specifically includes the following steps:

[0071] S410: spin-coating a PMMA solution on one side of the graphene layer 7 on the copper foil graphene layer to obtain a combination of PMMA layer / graphene layer 7 / copper foil in the order of PMMA layer / graphene layer 7;

[0072] S420: Adhere and press the assembly 1 on a glass slide by PDMS glue on one side of the PMMA layer, and remove the copper foil to obtain an assembly 2 in the order of glass slide / PDMS layer / PMMA layer / graphene layer 7;

[0073] S430: rolling the second assembly located on one side of the graphene layer 7 onto the substrate obtained in step S300 on one side of the first electrode 4, so that the second assembly covers the first electrode 4 and the second electrode 6; the heating temperature of the substrate obtained in step S300 is 160-180° C., and the rolling time is 0.5-4 min; removing the glass slide and the PDMS layer on the second assembly;

[0074] S440: Remove the PMMA layer with acetone, then wash with isopropyl alcohol, and then rinse with deionized water;

[0075] S450: applying glue on the graphene layer 7 and performing photolithography to obtain a patterned channel of the graphene layer 7, developing the patterned channel, and then using plasma to remove the excess graphene layer 7 to obtain a graphene device.

[0076] It should be noted that the above-mentioned copper foil graphene layer 7 is a conventional material, which is not described in detail in this application. In a preferred embodiment of the present application, the copper foil graphene layer 7 is obtained by growing the graphene layer 7 on the copper foil by the CVD method in step S410. It should be noted that the PMMA layer is coated on the graphene layer 7, and the copper foil graphene layer 7 is grown on the copper foil by the CVD method so that the graphene layer 7 will form the graphene layer 7 on both sides of the copper foil. For this reason, the graphene layer 7 on one side can be coated with the PMMA solution in step S410. In addition, the copper foil graphene layer 7 needs to be cut as required after being generated, so that the graphene layer 7 is rolled onto the substrate in the later stage. Wherein, PMMA is a conventional material, which is not described in detail in this application. In addition, the thickness of the PMMA layer is not required in this application, and its main purpose is to adhere to the PDMS glue and fix the slide glass in the later stage. In addition, PMMA can also play a role in fixing the graphene layer 7 in actual operation, so as to facilitate rolling in step S430 and avoid damage to the graphene layer 7.

[0077] Further, in one embodiment of the present application, step S420 more specifically includes the following steps:

[0078] S421: coating PDMS glue on one side of the assembly located on the PMMA layer;

[0079] S422: Adhere the glass slide to the PDMS glue and press it;

[0080] S423: Place the assembly obtained in the above step S422 into APS100 etching solution to etch away the copper foil, wash with deionized water and blow dry to obtain assembly 2 of the order of glass slide / PDMS layer / PMMA layer / graphene layer 7.

[0081] Among them, the design of the above-mentioned assembly 2 uses a glass slide as a substrate, which is convenient for the subsequent rolling process.

[0082] More specifically, in step S430, the heating temperature of the substrate is preferably 170°C, and the rolling time is 2 minutes. Among them, at about 170°C, the adhesion between the PDMS layer and the PMMA layer is reduced, and at this time the glass slide is easier to separate from the PMMA layer, reducing the difficulty of separating the glass slide. In addition, the main purpose of the glass slide in this application is to facilitate the external roller press to roll the PMMA layer / graphene layer 7 onto the above-mentioned substrate; the glass slide provides a stable rigid structure, thereby ensuring the quality of rolling. As an important step in transferring the graphene layer 7 by the stamp method, it is directly related to the subsequent rolling quality, the adhesion effect of the graphene layer 7 and the PI film 2, and the coverage effect of the graphene layer 7 on the first electrode 4.

[0083] In addition, in the present application, the graphene layer 7 is coated with glue and photolithography is performed to obtain a patterned channel of the graphene layer 7. The patterned channel of the graphene layer 7 is actually the pattern of the first electrode 4. The photoresist layer 8 on the first electrode 4, that is, the channel graphene layer 7, is not washed away and is intentionally retained by the photolithography to protect the graphene layer 7. At the same time, in step S450, the plasma plasma removes the excess graphene layer 7, which is the graphene layer 7 covering the second electrode 6, so that the graphene layer 7 can completely cover the first electrode 4.

[0084] It should be noted that to remove the PMMA layer using acetone, the entire carrier needs to be placed in the acetone solution for two hours. The PMMA remaining on the graphene layer 7 can be effectively cleaned by washing with isopropyl alcohol. The main purpose of rinsing with deionized water is to eliminate isopropyl alcohol and ensure the purity of the graphene layer 7 and the substrate. In addition, after washing with deionized water, air drying is required.

[0085] The preparation method of the flexible graphene field effect transistor of the present invention uses the PI film 2 as the substrate material, which can greatly improve the flexibility, so that the transistor formed later has greater flexibility. The PI film 2 can greatly improve the working ability of the entire device under high temperature conditions and ensure the stability of the work. The use of the graphene layer 7 to connect different electrodes can effectively reduce the thickness of the connection, so that the thickness of the entire substrate is reduced, and the effect of high transistor density is achieved under the condition of unit thickness. In this application, aluminum oxide is used as the dielectric layer, which can more easily control the channel operation through the gate voltage. Its high dielectric constant also effectively improves the mobility of holes and electron carriers, and improves the conductivity of the device. In addition, the role of the graphene layer 7 not covering the second electrode 6 is to cover the graphene layer 7 on the first electrode 4, thereby connecting the second electrode 6, thereby realizing the production of the flexible graphene field effect transistor GFET device.

[0086] See also Figure 4 The present invention also provides a graphene field effect transistor on a flexible substrate, which is prepared by the method for preparing the flexible graphene field effect transistor. In order to facilitate understanding of the method for preparing the flexible graphene field effect transistor, Figure 4 In the figure, reference numerals ac are the second electrode 6 , which is a gold-chromium layer, and reference numeral d is the first electrode 4 , which is covered with a graphene layer 7 ; reference numerals e, f, g, and h are all graphene layers 7 .

[0087] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A method for preparing a flexible graphene field effect transistor, characterized in that: include: S100: coating a thin film on the silicon substrate and forming an aluminum oxide dielectric layer on the thin film to obtain a substrate; The film is a PI film, and the thickness of the film is 10-25 μm; S200: preparing a first electrode on the aluminum oxide dielectric layer; S300: forming a gate dielectric layer on the substrate obtained in step S200, wherein the gate dielectric layer covers the first electrode, and processing a second electrode on the gate dielectric layer, wherein the first electrode and the second electrode are not connected to each other; S400: transferring a graphene layer on a substrate by a stamp method, and patterning the graphene to expose a second electrode; the graphene is used to connect the first electrode and the second electrode to obtain a graphene device; S5 00: peeling the graphene device obtained in step S400 from the silicon substrate, thereby obtaining a graphene field effect transistor with a flexible substrate; The S400 specifically includes the following steps: S410: spin coating a PMMA solution on one side of the graphene on the copper foil to obtain a combination of PMMA layer / graphene / copper foil in the order of PMMA layer / graphene; S420: Adhere and press the assembly 1 on a glass slide by PDMS glue on one side of the PMMA layer, and remove the copper foil to obtain an assembly 2 in the order of glass slide / PDMS layer / PMMA layer / graphene; S430: rolling the second assembly located on the graphene side onto the substrate obtained in step S300 on one side of the first electrode, with the second assembly covering the first electrode and the second electrode; the heating temperature of the substrate obtained in step S300 is 160-180° C., and the rolling time is 0.5-4 min; removing the glass slide and the PDMS layer on the second assembly; S440: Remove the PMMA layer with acetone, then wash with isopropyl alcohol, and then rinse with deionized water; S450: applying glue on the graphene and performing photolithography to obtain graphene patterned channels, developing the graphene, and then using plasma to knock off excess graphene to obtain a graphene device.

2. The method for preparing a flexible graphene field effect transistor according to claim 1, characterized in that: Step S420 more specifically includes the following steps: Coating PDMS glue on one side of the assembly located on the PMMA layer; Adhere the glass slide to the PDMS glue and press it firmly; The above-obtained assembly was placed in APS100 etching solution to etch away the copper foil, and then washed with deionized water and blown dry to obtain an assembly II having the sequence of glass slide / PDMS layer / PMMA layer / graphene.

3. The method for preparing a flexible graphene field effect transistor according to claim 1, characterized in that: In step S410, the copper foil graphene is obtained by growing graphene on copper foil by a CVD method.

4. The method for preparing a flexible graphene field effect transistor according to claim 1, characterized in that: The specific operation steps of step 300 include: Forming an aluminum oxide gate dielectric layer on the side of the substrate located at the first electrode by using an ALD atomic layer deposition coating method; Performing a mask photolithography experiment on the aluminum oxide gate dielectric layer to obtain a patterned channel of the second electrode; The second electrode is evaporated on the substrate by thermal evaporation to form an Au / Cr metal layer, and the thermally evaporated Au / Cr layer forms the second electrode in the patterned channel of the second electrode; then after the second electrode is formed, the part with the photoresist is removed using an NMP solution to reveal the first electrode, and the first electrode and the second electrode are not connected to each other.

5. The method for preparing a flexible graphene field effect transistor according to claim 4, characterized in that: The temperature of the NMP solution when removing the part with the photoresist is 80-90° C., and the removal time is 8-12 minutes.

6. The method for preparing a flexible graphene field effect transistor according to claim 4, characterized in that: The specific operation of the mask lithography experiment is: spin-coating LOR5A glue on the aluminum oxide gate dielectric layer, then spin-coating AZ5214 glue, and then photolithography exposure and development to obtain the desired pattern.

7. The method for preparing a flexible graphene field effect transistor according to claim 1, characterized in that: The specific operations of step S200 are: Spin-coat LOR5A glue on the alumina dielectric layer, then spin-coat AZ5214 glue, then perform photolithography exposure and development to obtain the desired pattern; A magnetron sputtering machine is used to sputter the side of the substrate with the pattern to form a Ti / Al metal layer; The portion with the photoresist is removed by using an NMP solution to obtain a first electrode.

8. A graphene field effect transistor on a flexible substrate, characterized in that: The flexible graphene field effect transistor is prepared by the preparation method of any one of claims 1 to 7.

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