Semiconductor device and method of forming the same

Abstract

A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a floor of the trench that extends through the second dielectric layer, and forming a second opening in a floor of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method also includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with a conductive material to form a conductive via. Embodiments of the present application provide semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, as the geometry (e.g., the smallest component (or line) that can be created using manufacturing processes) shrinks, the functional density (e.g., the number of interconnect devices per unit chip area) typically increases. This scaling-up process generally provides numerous benefits through increased yield efficiency and reduced associated costs.

[0003] As devices shrink, manufacturers have begun using new and different materials and / or combinations of materials to facilitate this reduction. The combination of size reduction and new, different materials also presents challenges that were not present in previous generations with larger geometries. Summary of the Invention

[0004] According to an embodiment, a method includes: forming a first etch stop layer (ESL) over a conductive component; forming a first dielectric layer on the first ESL; forming a second ESL on the first dielectric layer; forming a second dielectric layer on the second ESL; forming a trench in the second dielectric layer; forming a first opening in the bottom surface of the trench extending through the second dielectric layer; forming a second opening in the bottom surface of the first opening, the second opening extending through the first dielectric layer and the first ESL, the second opening exposing a top surface of the conductive component, the second opening having a first width; widening the first opening to a second width, the second width being greater than the first width; and filling the trench with a conductive material to form a conductor, and filling the second opening and the first opening with a conductive material to form a conductive via.

[0005] According to another embodiment, a method includes: forming a first opening through a first dielectric layer, the first dielectric layer being located on a first etch stop layer (ESL), the first ESL being located on a second dielectric layer, the second dielectric layer being located on a second ESL, and the second ESL being located on a first conductive component; forming a second opening through the first ESL, the second opening extending from the bottom of the first opening; widening the first opening by etching the sidewalls of the first dielectric layer; extending the second opening to pass through the second dielectric layer; extending the first opening to pass through the first ESL; extending the second opening to pass through the second ESL; and filling the first opening and the second opening with a conductive material to form a conductive via, the conductive via being coupled to the first conductive component.

[0006] According to another embodiment, a structure includes: a first conductive component located in a first dielectric layer; a second dielectric layer located above the first dielectric layer; a first etch stop layer (ESL) located on the second dielectric layer; a third dielectric layer located on the first ESL; a conductive via including: a top extending through the third dielectric layer and the first ESL, the bottom surface of the top covering the top surface of the second dielectric layer, the top having a first width measured across the bottom surface of the top; and a bottom extending through the second dielectric layer, the bottom surface of the bottom resting on the top surface of the first conductive component, the bottom having a second width measured across the top surface of the bottom, the second width being less than the first width; and a conductor located on the conductive via, the sidewalls of the conductor being covered by the third dielectric layer. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0008] Figure 1A Cross-sectional views of the semiconductor substrate and interconnect structure of an integrated circuit according to some embodiments are shown.

[0009] Figure 1B A perspective view of the interconnect structure at an intermediate stage of manufacturing, according to some embodiments, is shown.

[0010] Figures 2A to 8C A cross-sectional view of the interconnect structure at an intermediate stage of manufacturing, according to some embodiments, is shown.

[0011] Figure 9A and Figure 9B A perspective view of the interconnect structure at an intermediate stage of manufacturing, according to some embodiments, is shown.

[0012] Figures 9C to 9E A cross-sectional view of the interconnect structure at an intermediate stage of manufacturing, according to some embodiments, is shown.

[0013] Figures 10 to 12 A cross-sectional view of the interconnect structure at an intermediate stage of manufacturing, according to some embodiments, is shown. Detailed Implementation

[0014] The following disclosure provides various embodiments or examples to achieve different features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. These are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for brevity and clarity, but does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0016] This disclosure includes embodiments of interconnect structures, such as those with conductive vias having a two-level structure, and methods for forming the same. In advanced technology nodes, via resistance can increase as the bottom width of the via decreases, for example, below 20 nm. The two-level via structure has partial vias with increased widths to increase via volume, thereby reducing via resistance while maintaining a small contact area to minimize bridging. The two-level via structure can also achieve larger via facets, which improves the metal filling of the vias for better connectivity between conductive layers.

[0017] According to some embodiments, Figure 1A A cross-sectional view of a semiconductor structure 100 is shown, which includes a substrate 50 in which various electronic devices can be formed, and a portion of a multi-level interconnect system (e.g., layers 100A and 100B) formed above the substrate 50. Figure 1B As shown Figure 1A The image shows a three-dimensional view of region 101. This will typically be discussed in more detail below. Figure 1A A FinFET device 60 is shown formed on a substrate 50, with multiple interconnect layers formed thereon.

[0018] generally, Figure 1AThe substrate 50 shown may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., Ga...). x Al 1- x As, Ga x Al 1-x N、In x Ga 1-x Semiconductor materials may be assimilated, oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0019] Figure 1A The FinFET device 60 shown is a three-dimensional MOSFET structure formed in a fin-like strip called a fin. Figure 1A The cross-section shown is taken along the longitudinal axis of the fin in a direction parallel to the current direction between the source and drain regions 54. The fin 58 can be formed by patterning the substrate using photolithography and etching techniques. For example, spacer image transfer (SIT) patterning techniques can be used. In this method, a sacrificial layer is formed over the substrate and patterned using suitable photolithography and etching processes to form mandrels. Spacers are formed alongside the mandrels using a self-aligned process. The sacrificial layer is then removed by a suitable selective etching process. Each remaining spacer can then be used as a hard mask to pattern the corresponding fin 58 by etching trenches into the substrate 50 using, for example, reactive ion etching (RIE). Figure 1A A single fin 58 is shown, but the substrate 50 may include any number of fins.

[0020] Figure 1AA shallow trench isolation (STI) region 62 formed along the opposite sidewall of fin 58 is shown. The STI region 62 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trench around the fin, followed by trenching the top surface of the dielectric material. The dielectric material of the STI region 62 can be deposited using high-density plasma chemical vapor deposition (HDP-CVD), low-pressure CVD (LPCVD), subatmospheric pressure CVD (SACVD), flowable CVD (FCVD), spin coating, or combinations thereof. After deposition, an annealing or curing process can be performed. In some cases, the STI region 62 may include a liner (not shown), such as a thermal oxide liner grown through a silicon oxide surface. The trenching process can use, for example, a planarization process (e.g., chemical mechanical polishing (CMP)), followed by a selective etching process (e.g., wet etching or dry etching, or a combination thereof) that can trench the top surface of the dielectric material in the STI region 62, such that the upper part of fin 58 protrudes from the surrounding insulating STI region 62. In some cases, the patterned hard mask used to form fin 58 can also be removed by a planarization process.

[0021] In some embodiments, Figure 1A The gate structure 68 of the FinFET device 60 shown is a high-k metal gate (HKMG) gate structure, which can be formed using a post-gate process flow (sometimes referred to as a substitute gate process flow). In the post-gate process flow, a sacrificial dummy gate structure (not shown) is formed after the STI region 62 is formed. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, etc.) may be deposited. Next, a dummy gate material (e.g., amorphous silicon, polycrystalline silicon, etc.) may be deposited over the dummy gate dielectric and then planarized (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, etc.) may be formed over the dummy gate material. The dummy gate structure is then formed by patterning the hard mask and transferring the pattern to the dummy gate dielectric and dummy gate material using suitable photolithography and etching techniques. The dummy gate structure may extend along multiple sides of the protruding fins and between the fins above the surface of the STI region 62. As described in more detail below, the pseudo-gate structure can be replaced by a high-k metal gate (HKMG) gate structure 68, such as Figure 1A As shown. Figure 1A The HKMG gate structure 68 shown on the right (seen on top of fin 58) is an example of an active HKMG gate structure, which extends, for example, along the sidewall and top of the portion of fin 58 that protrudes above STI region 62. Figure 1AThe HKMG gate structure 68 on the left is an example gate structure extending above the STI region 62 (such as between adjacent fins). The material used to form the pseudo gate structure and hard mask can be deposited using any suitable method, such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or by thermal oxidation of the semiconductor surface or a combination thereof.

[0022] Figure 1A The source and drain regions 54 and spacer 72 of the FinFET 60 shown are, for example, formed to be self-aligned with the dummy gate structure. The spacer 72 can be formed by deposition and anisotropic etching of a spacer dielectric layer performed after dummy gate patterning is complete. The spacer dielectric layer may include one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or combinations thereof. The anisotropic etching process removes the spacer dielectric layer from the top of the dummy gate structure, leaving a portion extending laterally along the sidewalls of the dummy gate structure onto the surface of the fin (e.g., ...). Figure 1A (as shown on the right) or the surface of the STI dielectric (such as...) Figure 1A Spacer 72 (shown on the left).

[0023] The source and drain regions 54 are semiconductor regions that contact the semiconductor fins 58. In some embodiments, the source and drain regions 54 may include heavily doped regions and relatively lightly doped drain extension regions or LDD regions. Typically, the heavily doped regions are spaced apart from the dummy gate structure using spacers 72, while the LDD regions may be formed prior to the formation of spacers 72, thus extending below spacers 72, and in some embodiments, further extending into the semiconductor portion below the dummy gate structure. The LDD regions may be formed, for example, by implanting dopants (e.g., As, P, B, In, etc.) using an ion implantation process.

[0024] The source and drain regions 54 may include epitaxially grown regions. For example, after forming the LDD regions, spacers 72 may be formed, followed by forming trenches by first etching the fins, and then depositing crystalline semiconductor material in the trenches using a selective epitaxial growth (SEG) process. Heavily doped source and drain regions may be formed self-aligned with the spacers 72. This selective epitaxial growth process may fill the trenches and typically extend beyond the original surface of the fins to form a raised source-drain structure, such as... Figure 1A As shown. Crystalline semiconductor materials can be elements (e.g., Si or Ge, etc.) or alloys (e.g., Si...). 1-x C x or Si 1-x Ge x(etc.). SEG processes can utilize any suitable epitaxial growth method, such as vapor phase / solid phase / liquid phase epitaxy (VPE, SPE, LPE) or metal-organic CVD (MOCVD) or molecular beam epitaxy (MBE), etc. Ion implantation processes can be performed in situ during SEG or after SEG, or through combinations thereof, to deliver high doses (e.g., from about 10...). 14 cm -2 Up to 10 16 cm -2 The type of dopant is introduced into the heavily doped source and drain regions 54.

[0025] Interlayer dielectric (ILD) layer 76 (see) Figure 1A The dummy gate is deposited above the structure. In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (e.g., silicon nitride, silicon carbide, or a combination thereof) can be deposited prior to the deposition of the ILD material. A planarization process (e.g., CMP) can be performed to remove excess ILD material and any remaining hard mask material from above the dummy gate to form a top surface, wherein the top surface of the dummy gate material is exposed and can be substantially coplanar with the top surface of the ILD layer 76. The dummy gate structure can then be formed by first removing it using one or more etching techniques. Figure 1A The HKMG gate structure 68 shown creates grooves between the corresponding spacers 72.

[0026] Next, an alternative gate dielectric layer 66 comprising one or more dielectrics is deposited, followed by an alternative conductive gate layer 64 comprising one or more conductive materials to completely fill the trench. The gate dielectric layer 66 comprises, for example, a high-k dielectric material, such as oxides and / or silicates of metals (e.g., oxides and / or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), silicon nitride, silicon oxide, etc., or combinations thereof, or multiples thereof. In some embodiments, the conductive gate layer 64 may be a multilayer metal gate stack comprising a barrier layer, a work function layer, and a gate fill layer continuously formed on top of the gate dielectric layer 66. Example materials for the barrier layer include TiN, TaN, Ti, Ta, etc., or multiple combinations thereof. For p-type FETs, the work function layer may include TiN, TaN, Ru, Mo, Al; for n-type FETs, it may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr. Other suitable work function materials, combinations thereof, or multiples thereof may be used. The gate fill layer for the remaining portion of the filling trench may comprise a metal, such as Cu, Al, W, Co, Ru, or combinations thereof, or multiple layers thereof. The material used to form the gate structure can be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), chemical plating, etc. Excess portions of the gate structure layers 64 and 66 can be removed from the top surface of the ILD layer 76 using, for example, a CMP process. Figure 1A As shown, the resulting structure can be a substantially coplanar surface, including the exposed top surface of the ILD layer 76, the spacer 72, and the remainder of the HKMG gate layers 66 and 64 embedded between the respective spacers 72.

[0027] like Figure 1A As shown, ILD layer 78 can be deposited over ILD layer 76. In some embodiments, the insulating material forming ILD layers 76 and 78 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), porous or dense low dielectric constant (low k) dielectrics such as fluorosilicate glass (FSG), silicon carbide (SiOCH), carbon-doped oxide (CDO), flowable oxides or porous oxides (e.g., dry gel / aerogel), etc., or combinations thereof. Any suitable method can be used to deposit the dielectric material for forming ILD layers 76 and 78, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof.

[0028] like Figure 1AAs shown, electrodes of electronic devices formed in or on substrate 50 can be electrically connected to conductive components of the first interconnect layer 100A using conductive connectors (e.g., contact 74) formed through an intermediate dielectric layer. Figure 1A In the example shown, contact 74 is electrically connected to the source and drain regions 54 of the FinFET 60. The gate electrode contact 74 is typically formed above the STI region 62. A separate gate electrode 64 (in...) Figure 1A (Seen on the left) This contact is illustrated. The contact can be formed using photolithography. For example, a patterned mask can be formed over ILD layer 78 and used to etch openings extending through ILD layer 78 to expose a portion of the gate electrode above STI region 62, and to etch openings extending further over fin 58 through ILD layer 76 and below ILD layer 76 of the CESL (not shown) liner to expose a portion of source and drain regions 54. In some embodiments, an anisotropic dry etching process can be used, wherein etching is performed in two consecutive steps. The etchant used in the first step of the etching process has a higher etching rate for the materials of ILD layers 76 and 78 relative to the etching rate of the materials used in the gate electrode 64 and CESL, which can liner the top surface of the heavily doped regions of source and drain regions 54. Once the first step of the etching process exposes the CESL, a second step of the etching process can be performed, wherein the etchant can be switched to selectively remove the CESL.

[0029] In some embodiments, a conductive liner may be formed in the openings in ILD layers 76 and 78. The openings are then filled with a conductive filler material. The liner includes a barrier metal to reduce the diffusion of conductive material from contact 74 outwards into the surrounding dielectric material. In some embodiments, the liner may include two barrier metal layers. A first barrier metal contacts the semiconductor material in the source and drain regions 54 and may subsequently chemically react with the heavily doped semiconductor in the source and drain regions 54 to form a low-resistance ohmic contact, after which unreacted metal may be removed. For example, if the heavily doped semiconductor in the source and drain regions 54 is silicon or a silicon-germanium alloy semiconductor, the first barrier metal may include Ti, Ni, Pt, Co, other suitable metals, or alloys thereof. A second barrier metal layer of the conductive liner may additionally include other metals (e.g., TiN, TaN, Ta, or other suitable metals or alloys thereof). Conductive filler material (e.g., W, Al, Cu, Ru, Ni, Co, alloys thereof, combinations thereof, etc.) can be deposited over the conductive substrate using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, etc., or any combination thereof) to fill the contact openings. Next, all excess conductive material can be removed from the surface of the ILD layer 78 using a planarization process (e.g., CMP). The resulting conductive plugs extend into the ILD layers 76 and 78 and form contact 74, enabling physical and electrical connection to electronic devices (such as…). Figure 1A The electrodes of the tri-gate FinFET 60 shown are illustrated. In this example, the same processing steps are used to simultaneously form contacts for the electrodes above the STI region 62 and the electrodes on the fin 58. However, in other embodiments, these two types of contacts can be formed separately.

[0030] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructured (e.g., nanosheets, nanowires, all-around gates, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by stacks of alternating layers of patterned channel layers and sacrificial layers. The formation of the dummy gate stack and source / drain regions is similar to that described in the embodiments above. After removing the dummy gate stack, the sacrificial layer in the channel region can be partially or completely removed. The alternative gate structure is formed in a similar manner to the embodiments above, and the alternative gate structure can partially or completely fill the opening left by removing the sacrificial layer, and the alternative gate structure can partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and the contacts of the alternative gate structure and source / drain regions can be formed in a manner similar to that described in the embodiments above. Nanostructured devices can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety. See U.S. Patent Publication No. 2016 / 0365414, in one embodiment, the formation of the nanostructured device is described below. Forming a fin comprising a superlattice, the superlattice comprising alternating first and second layers; after forming the fin, selectively etching the first layer, and after selectively etching the first layer, forming a gate dielectric on the second layer; and forming a gate electrode on the gate dielectric, the first and second layers extending between a source region and a drain region. In some embodiments, the selective etching is anisotropic etching. In some embodiments, the selective etching is isotropic etching. In some embodiments, the first layer is compressively strained and the second layer is tensile strained. In some embodiments, the first layer is tensile strained and the second layer is compressively strained. In some embodiments, the method of forming a semiconductor structure further includes: forming a dummy gate stack on the superlattice; forming a dielectric around the dummy gate stack; and removing the dummy gate stack, after which selective etching is performed. In some embodiments, forming the gate dielectric on the second layer includes forming the gate dielectric at least partially between a first lateral surface and a second lateral surface of the first layer. In some embodiments, selective etching of the first layer includes selectively etching the sidewalls of the first layer on a first side of the first layer to offset inward from the sidewalls of the second layer on the first side. In some embodiments, the uppermost first layer of the first layer is interposed between the gate dielectric and the uppermost second layer of the second layer. In another embodiment, the formation of a nanostructure device is described.A fin is formed extending upward from a semiconductor substrate, wherein the fin includes: a first layer; a second layer on the first layer, wherein the first and second layers include different strain types; and a third layer on the second layer, wherein the third layer and the first layer include the same strain type; selectively etching the fin by etching the second layer at a rate different from that of the first and third layers; forming a gate dielectric over the sidewalls of the first, second, and third layers of the fin and extending continuously along the sidewalls of the first, second, and third layers of the fin; and forming a conductive gate over the gate dielectric. In some embodiments, selectively etching the fin includes selectively etching the second layer at a faster rate than that of the first and third layers. In some embodiments, selectively etching the fin includes selectively etching the second layer at a slower rate than that of the first and third layers. In some embodiments, the third layer is the uppermost semiconductor layer of the fin. In some embodiments, selectively etching the fin includes offsetting the sidewalls of the second layer from the sidewalls of the first and third layers, wherein the sidewalls of the second layer and the sidewalls of the first and third layers are disposed on the same side of the fin. In some embodiments, forming the gate dielectric includes forming the gate dielectric at least partially between the first and third layers. In some embodiments, the method of forming a semiconductor device further includes forming a dummy gate structure above and extending along the sidewalls of the channel region of the fin; replacing a first source / drain region of the fin adjacent to the dummy gate structure with an epitaxial source / drain region; forming a dielectric layer above and along the sidewalls of the epitaxial source / drain region; and removing the dummy gate structure to expose the channel region, wherein selectively etching the fin includes selectively etching the channel region of the fin after removing the dummy gate structure. In yet another embodiment, the formation of a nanostructure device is described. A superlattice extending upward from a substrate is formed, wherein the superlattice comprises alternating first and second layers with different strain types; a dummy gate structure is formed covering a first region of the superlattice, wherein a second region of the superlattice is exposed; the second region of the superlattice is replaced with a source / drain region; the dummy gate structure is removed to expose the first region of the superlattice; after removing the dummy gate structure, the first layer of the superlattice is selectively etched at a higher rate than the second layer of the superlattice; a gate dielectric is deposited over and along the sidewalls of the first region of the superlattice; and a conductive gate is formed over the gate dielectric, wherein the conductive gate is not completely separated from adjacent layers of the second layer in the first region. In some embodiments, the first layer is relaxed, tensile-strained, or compressive-strained, and the second layer is relaxed, tensile-strained, or compressive-strained. In some embodiments, selectively etching the first layer of the superlattice comprises removing the first layer of the superlattice. In some embodiments, depositing the gate dielectric comprises depositing at least a portion of the gate dielectric between consecutive second layers.

[0031] like Figure 1A As shown, according to the back-end process (BEOL) scheme adopted in integrated circuit design, multiple interconnect layers can be formed, vertically stacked above the contacts 74 formed in ILD layers 76 and 78. Figure 1A In the illustrated BEOL scheme, the various interconnect layers have similar components. However, it should be understood that other embodiments may use alternative integration schemes where the various interconnect layers may use different components. For example, the contact 74 shown as a vertical connector may extend to form a conductor for lateral current transmission.

[0032] Interconnect layers (e.g., interconnect layers 100A-100N) include conductive vias and lines embedded in the inter-metal dielectric (IMD) layer. In addition to providing insulation between various conductive elements, the IMD layer may include one or more dielectric etch stop layers to control the etching process that forms openings in the IMD layer. Typically, vias vertically conduct current and are used to electrically connect two conductive components located in vertically adjacent layers, while lines laterally conduct current and are used to distribute electrical signals and power within a single layer. Figure 1A In the illustrated BEOL configuration, conductive via 104A connects contact 74 to wire 108A, and in subsequent layers, the via connects lines on the layer below the via to lines above the via (e.g., a pair of lines 108A and 108B can be connected via via 104B). Other embodiments may employ different configurations. For example, via 104A may be omitted from layer 100A, and contact 74 may be configured to connect directly to wire 108A.

[0033] Still referencing Figure 1A The first interconnect layer 100A can be formed using, for example, a dual damascene process. First, a dielectric stack for forming the IMD layer 110A can be deposited using one or more dielectric materials listed in the description of the first and ILD layers 76 and 78. In some embodiments, the IMD layer 110A includes an etch stop layer (not shown) located at the bottom of the dielectric stack. The etch stop layer includes one or more insulating layers (e.g., SiO, SiOC, SiCN, SiON, SiN, CN, AlOx, AlN, AlYOx, ZrOx, YOx, combinations thereof, etc.) having an etch rate different from that of the materials above. The technique used to deposit the dielectric stack for the IMD can be the same as the technique used to form the ILD layers 76 and 78.

[0034] Suitable photolithography and etching techniques (e.g., anisotropic RIE using fluorocarbon chemicals) can be used to pattern the IMD layer 110A to form openings for vias and lines. Openings for vias can be vertical holes extending through the IMD layer 110A to expose the top conductive surface of the contact 74, and openings for lines can be longitudinal trenches formed in the upper portion of the IMD layer. In some embodiments, the method for patterning holes and trenches in the IMD layer 110A utilizes a via-first approach, where a first photolithography and etching process forms the holes for vias, and a second photolithography and etching process forms the trenches for lines. Other embodiments may use different methods, such as a trench-first approach, a partial via-first approach, or a buried etch stop layer approach. The etching technique can utilize multiple steps. For example, a first main etching step can remove a portion of the dielectric material of the IMD layer 110A and stop at an etch stop dielectric layer. The etchant can then be switched to remove the etch stop layer dielectric material. Parameters for various etching steps (e.g., chemical composition, flow rate and gas pressure, reactor power, etc.) can be adjusted to produce a tapered sidewall profile with a desired inner cone angle.

[0035] A plurality of conductive materials can be deposited to fill the holes and trenches of the conductive vias 104A and lines 108A forming the first interconnect layer 100A. The openings can be first lined with a conductive diffusion barrier material and then completely filled with a conductive filler material deposited above the conductive diffusion barrier liner. In some embodiments, a thin conductive seed layer can be deposited above the conductive diffusion barrier liner to help initiate the ECP deposition step of completely filling the openings with conductive filler material.

[0036] The conductive diffusion barrier liner in via 104A and line 108A may comprise one or more layers of TaN, Ta, TiN, Ti, Co, etc., or combinations thereof. The conductive filler layer in via 104A and line 108A may comprise a metal, such as W, Cu, Co, Ru, CuMn, Mo, Al, etc., or combinations thereof, or multiple layers thereof. The conductive material used to form the conductive via 104A and line 108A can be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), chemical plating, etc. In some embodiments, the conductive seed layer may have the same conductive material as the conductive filler layer and be deposited using a suitable deposition technique (e.g., CVD, PECVD, ALD, PEALD, or PVD, etc.).

[0037] Any excess conductive material above the IMD layer 110A outside the opening can be removed by a planarization process (e.g., CMP) to form a top surface of a dielectric region that is substantially coplanar with the conductive region of line 108A, including the IMD layer 110A. The planarization step completes the fabrication of the first interconnect layer 100A, which includes conductive vias 104A and wires 108A embedded in the IMD layer 110A, such as... Figure 1A As shown.

[0038] Figure 1A The interconnect layer vertically located above the first interconnect layer 100A is the second interconnect layer 100B. In some embodiments, the structures of the various interconnect layers (e.g., the first interconnect layer 100A and the second interconnect layer 100B) can be similar. Figure 1A In the example shown, the second interconnect layer 100B includes a conductive via 104B and a wire 108B embedded in an insulating film IMD 110B having a flat top surface. The materials and processing techniques described above in the context of the first interconnect layer 100A can be used to form the second interconnect layer 100B and subsequent interconnect layers.

[0039] Subsequent interconnect layers can be formed on top of the first and second interconnect layers 100A and 100B, up to the Nth interconnect layer 100N. In this example, the Nth interconnect layer 100N can be formed using the same materials and methods used to form the first and second interconnect layers 100A and 100B. Figure 1A The ellipsis in the text indicates one or more additional interconnect layers that can be used for electrical connection between the second interconnect layer 100B and the Nth interconnect layer 100N.

[0040] The example electronic device (FinFET 60) is provided for illustrative purposes only to further explain the application of the disclosed embodiments and is not intended to limit the disclosed embodiments in any way.

[0041] Figure 1B Show Figure 1A A perspective view of region 101, showing the top portion of the Nth interconnect layer 100N. According to some embodiments, in... Figure 1B In the diagram, the Nth interconnect layer 100N has been shown to have a via 104N+1 formed above it (see below). Figure 9B -D) interconnect layers, as discussed in more detail below. Conductors 108N and IMD 110N are shown for illustrative purposes only; it will be understood that conductors 108N and IMD 110N can be placed at any metallization layer suitable for a particular design, such as the first, second, and / or fifth metallization layers. Additionally, the subsequently formed (N+1) interconnect layer 100N+1 (see below, Figure 9AThe structure of -E) can be placed on any metallization layer suitable for a particular design. In some embodiments, the (N+1)th interconnect layer 100N+1 is the first interconnect layer and can be formed directly on the contact 74 and ILD 78 to replace the wires 108N and IMD 110N, respectively.

[0042] Figure 1B The reference cross sections used in the following figures are also shown. Cross section A-A' is perpendicular to the longitudinal axis of conductor 108N, cross section B-B' is perpendicular to cross section AA and along the longitudinal axis of conductor 108N, and cross section C-C' is parallel to cross section B-B' and parallel to conductor 108N and located outside of it.

[0043] Figures 2A to 12 These are cross-sectional and perspective views of an intermediate stage in the manufacturing of an interconnect structure, according to some embodiments. Figure 2A , Figure 2C , Figure 2D , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 6D , Figure 7A , Figure 8A , Figure 9C , Figure 10 , Figure 11 as well as Figure 12 Along Figure 1B The cross section A-A' shown is illustrated. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B as well as Figure 9D Along Figure 1B The cross section B-B' is shown. Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C as well as Figure 9E Along Figure 1B The cross section C-C' is shown. Figure 9A and Figure 9B This is a perspective view showing an intermediate stage in the fabrication of the interconnect structure.

[0044] Figure 2A and Figure 2B The formation of a dielectric stack 112 is shown, which includes an etch stop layer (ESL) and a dielectric layer located above the Nth interconnect layer 100N. The dielectric stack 112 is used for conductive vias and wires subsequently formed in the interconnect layer formed on the Nth interconnect layer 100N. According to... Figure 2A and Figure 2B In some embodiments, the dielectric stack 112 includes an ESL 120 on the Nth interconnect layer 100N, a dielectric layer 130 on the ESL 120, an ESL 140 on the dielectric layer 130, a dielectric layer 150 on the ESL 140, and another dielectric layer 160 on the dielectric layer 150.

[0045] refer to Figure 2A and Figure 2B The ESL 120 is formed on the Nth interconnect layer 100N. In some embodiments, the ESL 120 is used to control subsequent etching processes to form openings for vias (see below). Figures 5A-6B ESL 120 comprises one or more insulating layers, such as, for example, AlOx, AlN, AlYOx, ZrOx, YOX, combinations thereof, etc., having an etch rate different from that of the underlying IMD 110N and the subsequently formed material above. ESL 120 can be formed using PECVD, ALD, CVD, etc.

[0046] In some embodiments, the ESL 120 has a thickness T1 ranging from 5 angstroms to 25 angstroms. A thickness T1 of less than 5 angstroms for the ESL 120 may be disadvantageous because it may not be thick enough to control subsequent etching. A thickness T1 of more than 25 angstroms for the ESL 120 may be disadvantageous because it may be too thick to be removed without over-etching adjacent dielectric layers.

[0047] Next, a dielectric layer 130 is formed on the ESL 120. The dielectric layer 130 can be used to control subsequent etching processes to form openings for vias (see below). Figure 5A and Figure 5B This serves to provide structural and electrical isolation for conductive structures within or near the layer. The dielectric layer 130 includes one or more insulating layers, such as, for example, SiO, SiOC, SiCN, SiON, SiN, etc. According to some embodiments, the dielectric layer 130 is formed using PECVD, FCVD, spin coating, etc.

[0048] In some embodiments, the dielectric layer 130 has a thickness T2 in the range of 20 angstroms to 100 angstroms. A thickness T2 of less than 20 angstroms for the dielectric layer 130 may be disadvantageous because it may result in vias with undesirable small volumes, which increases via resistance and degrades device performance. A thickness T2 of more than 100 angstroms for the dielectric layer 130 may be disadvantageous because it may result in vias with undesirable large heights, which increases via resistance, degrades device performance, and / or increases overall device size.

[0049] ESL 140 is then formed on dielectric layer 130. In some embodiments, ESL 140 is used to control subsequent etching processes to form openings for vias (see below). Figures 3A-6B ESL 140 can be formed using similar methods and materials as described above for ESL 120. ESL 140 can have an etch rate different from that of the underlying dielectric layer 130 and the subsequently formed material above.

[0050] In some embodiments, the ESL 140 has a thickness T3 ranging from 5 angstroms to 30 angstroms. A thickness T3 of less than 5 angstroms for the ESL 140 may be disadvantageous because it may not be thick enough to control subsequent etching. A thickness T3 of more than 30 angstroms for the ESL 140 may be disadvantageous because it may be too thick to be removed without over-etching adjacent dielectric layers.

[0051] Still referencing Figure 2A and Figure 2B A dielectric layer 150 can be formed on the ESL 140. The dielectric layer 150 can be used to control subsequent etching processes to form openings for vias (see below). Figures 3A to 5B Dielectric layer 150 can be formed using methods and materials similar to those described above for dielectric layer 130, and / or for providing structural and electrical isolation for conductive structures within or near the layer.

[0052] In some embodiments, dielectric layer 150 has a thickness T4 in the range of 20 angstroms to 100 angstroms. A thickness T4 of dielectric layer 150 less than 20 angstroms may be disadvantageous because it may result in vias with undesirable small volumes, which increases via resistance and degrades device performance. A thickness T4 of dielectric layer 150 greater than 100 angstroms may be disadvantageous because it may result in vias with undesirable large heights, which increases via resistance and degrades device performance.

[0053] Next, a dielectric layer 160 is formed on dielectric layer 150. Dielectric layer 160 can be used to form the body of an intermetallic dielectric (IMD), surrounding the conductive vias and wires of the interconnect layer subsequently formed on the Nth interconnect layer 100N (see below). Figure 9A-C). In some embodiments, the insulating material used to form dielectric layer 160 may include a porous or dense low dielectric constant (low k) dielectric, such as, for example, silicon carbide (SiOCH), fluorosilicate glass (FSG), carbon-doped oxide (CDO), flowable oxide or porous oxide (e.g., dry gel / aerogel), silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., or combinations thereof. Any suitable method may be used to deposit the dielectric material used to form ILD layers 76 and 78, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof.

[0054] Further reference Figure 2A and Figure 2B A mask layer 170 can be formed on the dielectric layer 160. The mask layer 170 can be used to control subsequent etching processes to form openings for vias (see below). Figures 3A to 6B The mask layer 170 may include, for example, silicon nitride, silicon carbide, etc. The mask layer 170 may be deposited using any suitable method, such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), etc., or by thermal oxidation of a semiconductor surface or a combination thereof.

[0055] Figure 2C and Figure 2D The dielectric stacks 112' and 112' are shown according to some embodiments. They can be used with respect to... Figure 2A and Figure 2B The dielectric stack 112 is formed using similar methods and materials, but the dielectric layer 160 is formed directly on the ESL 140.

[0056] It can be used with about Figure 2A and Figure 2B The dielectric stack 112 is formed using similar methods and materials to the described dielectric stack 112', but an additional dielectric layer 124 is formed between ESL 120 and dielectric layer 130. Dielectric layer 124 can be used to control subsequent etching processes to form openings for vias (see below). Figures 3A to 5B This serves as both a structural and electrical isolation layer for providing conductive structures within or near the layer. Dielectric layer 124 can be formed using methods and materials similar to those described above for dielectric layer 130. In some embodiments, dielectric layer 124 comprises a material having an etch rate different from that of the material of dielectric layer 130.

[0057] exist Figure 3A , Figure 3B and Figure 3C relay Figure 2A and Figure 2B Then, the opening 200 for the subsequently formed wire (see below, Figure 9A -C) and the opening 201 for the subsequently formed conductive via (see below, Figure 9A -C) is formed through the mask layer 170, dielectric layer 160 and dielectric layer 150. Figure 3A The section A-A' passing through opening 200 is shown (see above). Figure 1B ), Figure 3B Show section B-B' perpendicular to section A-A' through openings 200 and 201 (see above) Figure 1B ), Figure 3B The section passing through opening 200 and not intersecting with opening 201 is shown as section C-C', which is parallel to section B-B' (see above). Figure 1B The hard mask layer 170 can be patterned using appropriate photolithography and etching techniques, and the pattern can be transferred to dielectric layers 16 and 150. The opening 201 for the conductive via can be a vertical hole extending through dielectric layers 160 and 150 to expose the top surface of the ESL 140, and the opening 200 for the conductor can be a longitudinal trench formed in the upper portion of dielectric layer 160.

[0058] In some embodiments, the method for patterning openings 200 and 201 through hard mask layer 170, dielectric layer 160, and dielectric layer 150 utilizes a via-first approach, wherein a first photolithography and etching process forms the opening 201 for the via, and a second photolithography and etching process forms the opening 200 for the line. Other embodiments may use different methods, such as a trench-first approach, a partial via-first approach, or a buried etch stop layer approach. Parameters of various etching steps (e.g., chemical composition, flow rate and gas pressure, reactor power, etc.) can be adjusted to produce a tapered sidewall profile with a desired inner cone angle. In some embodiments, the etching process is dry etching, such as using Ar, C4F8, CF4, C4F6, CH2F2, CH4, N2, O2, CO, CO2, H2, etc., or combinations thereof as the etch gas in the RIE. Etching can be performed at temperatures ranging from 60°C to 200°C for durations ranging from 5 seconds to 1200 seconds. However, any suitable process can be used to form openings 200 and 201.

[0059] exist Figure 4A , Figure 4B and Figure 4C In this process, a portion of ESL 140 is removed to form an additional opening 210 below opening 201, which exposes the top surface of dielectric layer 130. Removing a portion of ESL 140 is advantageous for the subsequent widening of opening 201 of the subsequently formed conductive via (see below). Figures 5A-6C A portion of ESL 140 can be removed using a wet cleaning process. The wet cleaning process can exhibit higher etch selectivity for the materials of ESL 140 than for the materials of dielectric layers 130, 150, and 160, thereby removing a portion of ESL 140 without significantly etching dielectric layers 130, 150, and 160. In some embodiments, wet cleaning includes solvents such as, for example, H₂SO₄, HCl, H₂O₂, etc., or aqueous solutions with a pH greater than 7.0, including, for example, NaOH, KOH, NH₄OH, etc., or combinations thereof. Wet cleaning can be performed at temperatures ranging from 30°C to 100°C for durations ranging from 5 s to 1200 s. However, any suitable process can be used to form opening 210.

[0060] exist Figure 5A , Figure 5B and Figure 5C In this process, opening 202 is formed by widening opening 201 into the sidewalls of dielectric layers 150 and 160, and opening 212 is formed by extending opening 210 through dielectric layer 130 to expose the top surface of ESL 120. Forming openings 202 and 212 can facilitate increasing the volume of subsequently formed conductive vias (see below). Figure 9A -C), which can reduce via resistance and improve device performance.

[0061] Openings 202 and 212 can be formed using linear removal methods (LRM), such as atomic layer etching (ALE) which etches the sidewalls of dielectric layers 150 and 160 instead of the top surface of dielectric layer 160. The ALE can be a cyclic etching process comprising 2 to 25 cycles. Each cycle of the ALE involves selectively depositing a dielectric material, such as a polymer, on the top surface of dielectric layer 160, followed by an etching process, such as isotropic etching. Because the polymer deposited on the top surface of dielectric layer 160 reduces the etch rate of the top surface of dielectric layer 160, each cycle of the ALE can remove more material from the sidewalls of dielectric layers 150 and 160 than from the top surface of dielectric layer 160. Therefore, the lateral etch rate of the sidewalls of dielectric layers 150 and 160 is greater than the etch rate of the top surface of dielectric layer 160.

[0062] In some embodiments, LRM is a dry etching process, such as a RIE using Ar, C4F8, CF4, C4F6, CH2F2, CH4, N2, O2, CO, CO2, H2, or combinations thereof as the etching gas. Etching can be performed at temperatures ranging from 60°C to 200°C. Each etching cycle can be performed for a duration ranging from 5 seconds to 1200 seconds. However, any suitable process can be used to form openings 202 and 212.

[0063] Forming an opening 202 with increased width can facilitate a larger via facet, which can improve subsequent metal filling of the conductive via (see below). Figure 8A -C). The increased width of the opening 202 allows for a two-level structure for the subsequently formed conductive vias, which is advantageous for increasing via volume to reduce via resistance while maintaining a small contact area to reduce bridging between adjacent conductive vias. In some embodiments, the opening 202 may extend over multiple adjacent conductors 108N (see below, Figure 6D ).

[0064] exist Figure 6A , Figure 6B and Figure 6C In this process, a portion of ESL 140 is removed to expand opening 202 into opening 204 exposing the top surface of dielectric layer 130, and a portion of ESL 120 is removed to expand opening 212 into opening 214 exposing the top surface of conductor 108N. The corresponding portions of ESL 120 and 140 can be removed using a wet cleaning process. The wet cleaning process can have higher etch selectivity for the materials of ESL 120 and ESL 140 than for the materials of dielectric layers 130, 150, and 160, thereby removing portions of ESL 120 and 140 without significantly etching dielectric layers 130, 150, and 160. In some embodiments, the same methods as described above are used... Figure 4A -C describes wet cleaning processes and chemicals similar to those used to perform wet cleaning. However, any suitable process can be used to form openings in 204 and 214.

[0065] The opening 214 can have a bottom width Wl in the range of 8 nm to 20 nm, which is beneficial for increasing the subsequent formation of vias (see below). Figure 9A A smaller bottom width (W1) can be advantageous, as it can reduce via resistance and improve device performance. A bottom width W1 less than 8 nm may be disadvantageous because it can result in a via profile that is too narrow in the top view, which can negatively impact via metal filling and lead to poor interlayer connectivity. A bottom width W1 greater than 20 nm may be disadvantageous because it can result in a via profile that is too wide in the top view, which can lead to bridging with adjacent conductive vias or wires.

[0066] The opening 214 can have a top width W2 in the range of 10 nm to 25 nm, which is beneficial for increasing the width of the subsequently formed via (see below). Figure 9AA smaller top width (W2) can be advantageous, as it can reduce via resistance and improve device performance. A top width W2 of less than 10 nm may be disadvantageous because it can result in a via profile that is too narrow in the top view, which can negatively impact via metal filling and lead to poor interlayer connectivity. A top width W2 greater than 25 nm may be disadvantageous because it can result in a via profile that is too wide in the top view, which can lead to bridging with adjacent conductive vias or wires.

[0067] The opening 204 can have a bottom width W3 in the range of 14 nm to 40 nm, which is beneficial for increasing the width of the subsequently formed via (see below). Figure 9A A smaller bottom width (W3) can be advantageous, as it can reduce via resistance and improve device performance. A bottom width W3 of less than 14 nm may be disadvantageous because it can result in a via profile that is too narrow in the top view, which can negatively impact via metal filling and lead to poor interlayer connectivity. A bottom width W3 greater than 40 nm may be disadvantageous because it can result in a via profile that is too wide in the top view, which can lead to bridging with adjacent conductive vias or wires.

[0068] The opening 204 can have a top width W4 in the range of 25 nm to 80 nm, which is beneficial for increasing the width of the subsequently formed via (see below). Figure 9A A smaller top width (W4) can be advantageous, as it can reduce via resistance and improve device performance. A top width (W4) of less than 25 nm can be disadvantageous, as it may negatively affect the metal filling of the via and lead to poor interlayer connectivity. A top width (W4) greater than 80 nm can be disadvantageous, as it may result in the via profile being too wide in the top view, which could lead to bridging with adjacent conductive vias or wires.

[0069] When the bottom width W1 is less than approximately 20 nm, the bottom width W3 can be greater than or equal to approximately 1.2 times the bottom width W1. The top width W4 can be greater than or equal to approximately 1.8 times the bottom width W3. The bottom width W3 can be greater than or equal to approximately 1.4 times the top width W2. The top width W2 can be greater than or equal to approximately 1.25 times the bottom width W1.

[0070] In some embodiments, after the opening 204 is formed, the portion of the dielectric layer 160 in section A-A' adjacent to the opening 204 has a thickness T5 in the range of 250 angstroms to 500 angstroms. This can facilitate control over the height of the subsequently formed via to achieve a larger volume (see below). Figure 9A-C). A dielectric layer thickness T5 of less than 250 angstroms 160 may be disadvantageous because it can result in vias with undesirable small volumes, which increases via resistance and degrades device performance. A dielectric layer thickness T5 of more than 500 angstroms 160 may be disadvantageous because it can result in vias with undesirable large heights, which increases via resistance and degrades device performance.

[0071] Figure 6D An opening 204 is shown, according to some embodiments, extending above one or more conductors 108N adjacent to the conductors 108N exposed by the opening 214. The opening 204 extending above the multiple conductors 108N can facilitate increasing the volume of the subsequently formed via, thereby reducing the via resistance and improving the metal filling of the opening 214.

[0072] exist Figure 7A , 7B In 7C, a conductive diffusion barrier liner 220 is formed above the structure to line the sidewalls and bottom surfaces of openings 200, 204, and 214. The conductive diffusion barrier liner 220 can reduce the amount of conductive material subsequently formed in openings 200, 204, and 214 (see below). Figures 8A-8C The conductive diffusion barrier liner 220 diffuses outward into the surrounding dielectric material. The conductive diffusion barrier liner 220 may comprise one or more layers of TaN, Ta, TiN, Ti, Co, or combinations thereof. The conductive diffusion barrier liner 220 can be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), chemical plating, etc.

[0073] exist Figure 8A , Figure 8B and Figure 8C In this process, a conductive filler material 250 is formed over a conductive diffusion barrier liner 220 to completely fill openings 200, 204, and 214. In some embodiments, a thin conductive seed layer may be deposited over the conductive diffusion barrier liner 220 to aid in initiating the ECP deposition step, wherein the conductive filler material 250 completely fills the openings. The conductive filler material 250 may comprise a metal, such as W, Cu, Co, Ru, CuMn, Mo, Al, or combinations thereof or multiples thereof. The conductive filler material 250 may be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), electroless plating, etc. In some embodiments, the conductive seed layer may have the same conductive material as the conductive filler material 250 and be deposited using a suitable deposition technique (e.g., CVD, PECVD, ALD, PEALD, or PVD, etc.).

[0074] The increased width of openings 204 and 214 can facilitate an improved filling process for the conductive filler material 250. This is advantageous because it provides better connectivity between interconnect layers.

[0075] Figures 9A to 9E The (N+1)th interconnect layer 100N+1 is shown, which includes a conductive via 104N+1 and a conductor 108N+1 in the IMD layer 110N+1. Figure 9A A 3D view of region 101 is shown. Figure 9B Another perspective view of region 101 cut along section A-A' is shown. Figure 9A The section A-A' shown indicates Figure 9C ,along Figure 9A The section shown is section B-B'. Figure 9D ,along Figure 9A The cross section C-C' shown indicates Figure 9E The IMD layer 110N+1 includes, for example, ESL 120 and 140 and dielectric layers 130, 150 and 160. The conductor 108N+1 includes portions of a conductive diffusion barrier liner 220 and conductive filler material 250 filling openings 200. The conductive via 104N+1 includes a conductive diffusion barrier liner 220 and conductive filler material 250 filling openings 204 and 214 (see above). Figure 6A -C).

[0076] A planarization process (e.g., CMP) can be performed to remove any excess conductive material and the hard mask layer 170 above the IMD layer 110N+1 (see above). Figure 8B The remaining portion of -C) forms the top surface of the dielectric region of the IMD layer 110N+1, which is substantially coplanar with the conductive region of the conductor 108N+1. The planarization step completes the fabrication of the (N+1)th interconnect layer 100N, which includes the conductive via 104N+1 embedded in the IMD layer 110N+1 and the conductor 108N+1.

[0077] The two-stage structure of the conductive via 104N+1 provides increased via volume, which reduces via resistance while maintaining a small contact area with the underlying conductor 108N. This reduces bridging defects between adjacent conductive vias. Larger via facets, such as increased widths W1, W2, W3, and W4, are beneficial by improving the metal fill of the conductive via 104N+1, which provides better connectivity between interconnect layers.

[0078] Figure 10 The following is illustrated according to some embodiments. Figure 6DSubsequent embodiments also illustrate conductive vias 104N+1 extending above one or more conductors 108N (adjacent to the conductors 108N on the bottom surface of the contact conductive via 104N+1). Extending the conductive via 104N+1 above multiple conductors 108N can advantageously increase the volume of the conductive via 104N+1, which can reduce via resistance and improve the metal filling of the conductive via 104N+1.

[0079] Figure 11 and Figure 12 Show respectively Figure 2C and Figure 2D The following are examples. Figure 11 The diagram shows an IMD layer 110N+1' comprising ESL 120 and 140 and dielectric layers 130 and 160, and... Figure 12 The diagram shows an IMD layer 110N+1' comprising ESL 120 and 140 and dielectric layers 124, 130, 150, and 160. The IMD layer 110N+1' can be used with respect to... Figures 3A to 9E The IMD layer 110N+1 is formed using a similar method, but the dielectric layer 160 is directly located on the ESL 140. The IMD layer 110N+1 can be used with respect to... Figures 3A to 9E The IMD layer 110N+1 is formed in a similar manner, but the dielectric layer 124 is located between the ESL 120 and the dielectric layer 130.

[0080] The embodiments can offer advantages. The via structures disclosed above can provide a smaller contact area to reduce bridging. The increased width of the via structure can provide a larger via volume, which can reduce via resistance and improve device performance of advanced technology nodes with smaller via bottom widths. The metal filling of the vias can be improved by larger via facets to provide better interlayer connectivity.

[0081] According to an embodiment, a method includes: forming a first etch stop layer (ESL) over a conductive component; forming a first dielectric layer on the first ESL; forming a second ESL on the first dielectric layer; forming a second dielectric layer on the second ESL; forming a trench in the second dielectric layer; forming a first opening extending through the second dielectric layer in the bottom surface of the trench; forming a second opening in the bottom surface of the first opening, the second opening extending through the first dielectric layer and the first ESL, the second opening exposing a top surface of the conductive component, the second opening having a first width; widening the first opening to a second width, the second width being greater than the first width; and filling the trench with a conductive material to form a conductor, and filling the second opening and the first opening with a conductive material to form a conductive via. In an embodiment, widening the first opening includes further etching the second dielectric layer, wherein a sidewall portion of the second dielectric layer is removed at a faster rate than the top of the second dielectric layer. In an embodiment, forming the second opening includes: etching through the first dielectric layer to expose a portion of the first ESL while further etching the second dielectric layer; and removing that portion of the first ESL. In one embodiment, depositing the second dielectric layer includes: depositing a first dielectric material on a second ESL and depositing a second dielectric material on the first dielectric material, wherein the second dielectric material is different from the first dielectric material. In one embodiment, the first dielectric material is deposited to a thickness in the range of 20 angstroms to 100 angstroms. In one embodiment, the method further includes: forming a trench in the second dielectric material, a first opening extending into the bottom surface of the trench; and filling the trench with a conductive material. In one embodiment, the second dielectric material has a thickness in the range of 250 angstroms to 500 angstroms, measured between the top surface of the first dielectric material and the bottom surface of the trench.

[0082] According to another embodiment, a method includes: forming a first opening through a first dielectric layer, the first dielectric layer being on a first etch stop layer (ESL), the first ESL being on a second dielectric layer, the second dielectric layer being on a second ESL, and the second ESL being on a first conductive member; forming a second opening through the first ESL, the second opening extending from the bottom of the first opening; widening the first opening by etching the sidewalls of the first dielectric layer; extending the second opening through the second dielectric layer; extending the first opening through the first ESL; extending the second opening through the second ESL; and filling the first and second openings with a conductive material to form a conductive via coupled to the first conductive member. In an embodiment, the first opening is widened such that it extends above the second conductive member, and the second conductive member is adjacent to the first conductive member below the second ESL. In an embodiment, the first ESL is formed to a thickness in the range of 5 angstroms to 30 angstroms. In an embodiment, the second dielectric layer is formed to a thickness in the range of 20 angstroms to 100 angstroms. In an embodiment, the second ESL is formed to a thickness in the range of 5 angstroms to 25 angstroms.

[0083] According to another embodiment, a structure includes: a first conductive component located in a first dielectric layer; a second dielectric layer located above the first dielectric layer; a first etch stop layer (ESL) located on the second dielectric layer; a third dielectric layer located on the first ESL; a conductive via including: a top extending through the third dielectric layer and the first ESL, the bottom surface of the top covering the top surface of the second dielectric layer, the top having a first width measured across the bottom surface of the top; and a bottom extending through the second dielectric layer, the bottom surface of the bottom resting on the top surface of the first conductive component, the bottom having a second width measured across the top surface of the bottom, the second width being less than the first width; and a conductor located on the conductive via, the sidewalls of the conductor being covered by the third dielectric layer. In this embodiment, the structure further includes a second conductive component located in the first dielectric layer, wherein the conductive via extends above the second conductive component. In this embodiment, the structure further includes a second ESL located between the first and second dielectric layers. In one embodiment, the structure further includes a fourth dielectric layer located between the second ESL and the second dielectric layer, wherein the second dielectric layer is a first dielectric material, the fourth dielectric layer is a second dielectric material, and the first dielectric material is different from the second dielectric material. In one embodiment, the first width is greater than or equal to 1.4 times the second width. In one embodiment, the top has a third width measured across the top surface, which is greater than or equal to 1.8 times the first width. In one embodiment, the bottom has a fourth width measured across the bottom surface, where the first width is greater than or equal to 1.2 times the fourth width. In one embodiment, the bottom has a fourth width measured across the bottom surface, where the second width is greater than or equal to 1.25 times the fourth width.

[0084] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: A first etch stop layer (ESL) is formed over the conductive components; A first dielectric layer is formed on the first etch stop layer; A second etch stop layer is formed on the first dielectric layer; A second dielectric layer is formed on the second etch stop layer; Trenches are formed in the second dielectric layer; A first opening extending through the second dielectric layer is formed in the bottom surface of the trench; A second opening is formed in the bottom surface of the first opening, the second opening extends through the first dielectric layer and the first etch stop layer, the second opening exposes the top surface of the conductive component, and the second opening has a first width; The first opening is widened to a second width, where the second width is greater than the first width; as well as The trench is filled with a conductive material to form a wire, and the second opening and the first opening are filled with the conductive material to form a conductive via.

2. The method of forming a semiconductor device of claim 1, wherein, Widening the first opening includes further etching the second dielectric layer, wherein sidewall portions of the second dielectric layer are removed at a faster rate than the top of the second dielectric layer.

3. The method of forming a semiconductor device of claim 2, wherein, Forming the second opening includes: While further etching the second dielectric layer, etching is also performed through the first dielectric layer to expose a portion of the first etch stop layer; and Remove the portion of the first etch stop layer.

4. The method of forming a semiconductor device of claim 1, wherein, Depositing the second dielectric layer includes: A first dielectric material is deposited on the second etch stop layer; and A second dielectric material is deposited on the first dielectric material, wherein the second dielectric material is different from the first dielectric material.

5. The method of forming a semiconductor device of claim 4, wherein, The first dielectric material is deposited to a thickness ranging from 20 angstroms to 100 angstroms.

6. The method for forming a semiconductor device according to claim 5, further comprising: A trench is formed in the second dielectric material, and the first opening extends into the bottom surface of the trench; and The trench is filled with the conductive material.

7. The method of forming a semiconductor device of claim 6, wherein, The second dielectric material has a thickness in the range of 250 angstroms to 500 angstroms, measured between the top surface of the first dielectric material and the bottom surface of the trench.

8. A method of forming a semiconductor device, comprising: A first opening is formed through the first dielectric layer, which is located on the first etch stop layer (ESL), the first etch stop layer is located on the second dielectric layer, the second dielectric layer is located on the second etch stop layer, and the second etch stop layer is located on the first conductive component; A second opening is formed through the first etch stop layer, the second opening extending from the bottom of the first opening; The first opening is widened by etching the sidewalls of the first dielectric layer; Extend the second opening to pass through the second dielectric layer; Extend the first opening to pass through the first etch stop layer; Extend the second opening to pass through the second etch stop layer; as well as The first opening and the second opening are filled with conductive material to form a conductive via, which is coupled to the first conductive component.

9. The method of forming a semiconductor device of claim 8, wherein, The first opening is widened so that it extends above the second conductive component, which is adjacent to the first conductive component below the second etch stop layer.

10. The method of forming a semiconductor device of claim 8, wherein, The first etch stop layer is formed to a thickness ranging from 5 angstroms to 30 angstroms.

11. The method of forming a semiconductor device of claim 8, wherein, The second dielectric layer is formed to a thickness in the range of 20 angstroms to 100 angstroms.

12. The method of forming a semiconductor device of claim 8, wherein, The second etch stop layer is formed to a thickness ranging from 5 angstroms to 25 angstroms.

13. A semiconductor device, comprising: The first conductive component is located in the first dielectric layer; The second dielectric layer is located above the first dielectric layer; A first etch stop layer (ESL) is located on the second dielectric layer; The third dielectric layer is located on the first etch stop layer; A conductive via includes: a top extending through the third dielectric layer and the first etch stop layer, the bottom surface of the top covering the top surface of the second dielectric layer, the top having a first width measured across the bottom surface of the top; and a bottom extending through the second dielectric layer, the bottom surface resting on the top surface of the first conductive member, the bottom having a second width measured across the top surface of the bottom, the second width being smaller than the first width; and A conductor is located above the top surface of the top of the conductive via, and the conductor crosses the top surface of the top and extends beyond the edge of the top, the sidewalls of the conductor being covered by the third dielectric layer.

14. The semiconductor device of claim 13, further comprising a second conductive feature in the first dielectric layer, wherein, The conductive via extends above the second conductive component.

15. The semiconductor device of claim 13, further comprising a second etch stop layer located between the first dielectric layer and the second dielectric layer.

16. The semiconductor device of claim 15, further comprising a fourth dielectric layer between the second etch stop layer and the second dielectric layer, wherein, The second dielectric layer is made of a first dielectric material, the fourth dielectric layer is made of a second dielectric material, and the first dielectric material is different from the second dielectric material.

17. The semiconductor device of claim 13, wherein, The first width is greater than or equal to 1.4 times the second width.

18. The semiconductor device according to claim 13, wherein, The top has a third width measured across the top surface of the top, the third width being greater than or equal to 1.8 times the first width.

19. The semiconductor device according to claim 13, wherein, The bottom has a fourth width measured across the bottom surface of the bottom, and the first width is greater than or equal to 1.2 times the fourth width.

20. The semiconductor device according to claim 13, wherein, The bottom has a fourth width measured across the bottom surface of the bottom, and the second width is greater than or equal to 1.25 times the fourth width.

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