Semiconductor device plug forming method and semiconductor device thereof

Abstract

The present invention discloses a method for forming a plug in a semiconductor device and a semiconductor device thereof. In the proposed method, the semiconductor device includes a deep trench structure and a storage node disposed within the deep trench structure. The method comprises: (a) filling the deep trench structure with a single layer of film to cover the storage node; and (b) etching back the single layer of film to form the plug located within the deep trench structure and around the storage node, wherein the single layer of film forms a single liner layer.

Description

Technical Field

[0001] The present invention relates to a method for forming a plug of a semiconductor device and a semiconductor device thereof, and in particular to an embedded dynamic random access memory (eDRAM) having a plug capable of preventing a word line (WL) from shorting with a deep trench (DT) structure. Background Art

[0002] The prior art discloses a variety of different eDRAMs with DT structures. As the size of semiconductor devices changes, more and more eDRAM devices are formed per unit area of semiconductor chips. Since each eDRAM requires a capacitor to store charge, the available device area of each capacitor decreases with each generation. When eDRAM uses DT capacitors, the minimum capacitance requirement poses a major challenge. How to improve the efficiency of DT capacitors in eDRAM deserves further research and improvement. For example, how to prevent word lines (WL) from shorting to the DT structure of the DT capacitor contained in eDRAM is an important aspect of development in this field. US6849889 discloses a conductive plug formed for a storage node, but it is not proposed for isolation purposes. US8927365 discloses the use of an ONO stack to prevent WL from shorting to a fin-type cell. However, it does not disclose preventing WL from shorting to the DT structure, and its thin film stack structure is complex. US7705386 discloses the use of shallow trench isolation (STI) concepts to prevent gate shorting to the DT structure, but it is not suitable for advanced technologies.

[0003] In view of the shortcomings of the prior art, the applicant has finally conceived a method for forming a semiconductor device plug and a semiconductor device thereof through diligent and persistent experiments and research. Summary of the Invention

[0004] Therefore, the present invention provides a method for forming a semiconductor device plug and a semiconductor device thereof, wherein the plug is used to prevent a WL within the semiconductor device from shorting to a DT structure also within the semiconductor device. By utilizing a chemical mechanical polishing (CMP) hard stop liner process, the proposed method achieves relatively good batch-to-batch and intra-wafer uniformity. Furthermore, because the plug is formed from a single liner layer, the resulting topological profile within the plug area is relatively good.

[0005] According to a first aspect of the present invention, a method for forming a plug in a semiconductor device is provided, wherein the semiconductor device includes a deep trench (DT) structure and a storage node configured in the DT structure, the method comprising: (a) filling the DT structure with a single-layer film and covering the storage node; and (b) etching back the single-layer film to form the plug located in the DT structure and around the storage node, wherein the single-layer film forms a single liner layer.

[0006] According to a second aspect of the present invention, a method for manufacturing a semiconductor device includes: (a) forming a deep trench (DT) structure; (b) constructing a storage node having a top end in the DT structure; (c) forming a gap structure between the top end and the DT structure; and (d) filling the gap structure with a single-layer dielectric material film and etching back the single-layer dielectric material film to form a plug including a single dielectric material.

[0007] According to a third aspect of the present invention, a semiconductor device includes: a deep trench (DT) structure; a storage node configured in the DT structure and having a top; a gap structure formed between the top and the DT structure; and a plug including a single dielectric material and filled in the gap structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Other objects, advantages and effects of the present invention will be described below in conjunction with preferred embodiments and with reference to the accompanying drawings, wherein:

[0009] 1( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 1( a )- 1 of a manufacturing process according to a first preferred embodiment of the present invention.

[0010] 1( b ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 1( b )- 1 of a manufacturing process according to a first preferred embodiment of the present invention.

[0011] 1( c ) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 1 ( c )- 1 of a manufacturing process according to a first preferred embodiment of the present invention.

[0012] 2( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 2 ( a ) - 1 of a manufacturing process according to a first preferred embodiment of the present invention.

[0013] FIG2(b) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 2(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0014] 3( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 3 ( a ) - 1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0015] FIG3(b) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 3(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0016] 4( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 4 ( a ) - 1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0017] FIG4(b) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 4(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0018] FIG. 5( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 5 ( a ) - 1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0019] FIG5(b) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 5(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0020] FIG6(a) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 6(a)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0021] FIG6(b) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 6(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0022] FIG. 7( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 7 ( a ) - 1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0023] FIG7(b) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 7(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0024] FIG7(c) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 7(c)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0025] FIG7(d) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 7(d)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0026] FIG. 7( e ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 7 ( e ) - 1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0027] FIG7(f) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 7(f)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0028] FIG8(a) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 8(a)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0029] FIG8( b ) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 8( b )- 1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0030] FIG. 9( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 9 ( a ) - 1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0031] FIG9(b) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 9(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0032] FIG9(c) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 9(c)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0033] FIG9(d) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 9(d)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0034] FIG9(e) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 9(e)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0035] FIG9(f) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 9(f)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0036] FIG9(g) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 9(g)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0037] FIG9(h) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 9(h)-1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0038] FIG. 10( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 10 ( a ) - 1 of the manufacturing process according to the first preferred embodiment of the present invention.

[0039] FIG10( b ) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 10 ( b )- 1 of the manufacturing process according to the first preferred embodiment of the present invention. DETAILED DESCRIPTION

[0040] Here, the present invention will be described in more detail with reference to the following embodiments. It should be noted that the following description of the preferred embodiments of the present invention is for illustration and description purposes only and is not intended to be exhaustive or limited to the disclosed forms.

[0041] FIG1(a) shows a cross-sectional view of a semiconductor device including an eDRAM having a dynamic random access memory (DRAM), corresponding to step 1(a)-1 of a manufacturing process according to a first preferred embodiment of the present invention. In step 1(a)-1, it includes: (i) providing a DRAM 11 included in the eDRAM 1 (see FIG1(c)) of the semiconductor device and having a substrate 114, a buried oxide (BOX) 113 disposed on the substrate 114, a deep trench (DT) structure 112 having a void structure 1121 and etched through the BOX 113 and into the substrate 114, and a storage node 111 disposed in the DT structure 112.

[0042] FIG1(b) shows a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 1(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 1(b)-1 includes: (i) forming a single-layer dielectric material film to fill the DT structure 112 and cover the storage node 111, wherein the single-layer dielectric material film is a silicon nitride (SiN) liner layer 10.

[0043] 1( c ) is a cross-sectional view of a semiconductor device including an eDRAM having a static random access memory (SRAM), corresponding to step 1( c )- 1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 1(c)-1, it includes: (i) providing an SRAM 12 contained in an eDRAM 1 and having a substrate 114, a buried oxide (BOX) 113 configured on the substrate 114, a silicon-on-insulator (SOI) wafer 1211 configured on the BOX 113, and a fin unit 121 configured on the SOI 1211; (ii) providing an SOI wafer 122 having the substrate 114, the BOX 113, and the SOI 1211, wherein the eDRAM 1 includes the DRAM 11 and the SRAM 12; and (iii) forming a single-layer SiN liner layer 10 on the BOX 113 and the fin unit 121, wherein the SOI 1211 contained in the DRAM 11 (located on the BOX 113 in FIG. 1(a) , not shown) and the SOI 1211 contained in the SRAM 12 have the same crystal orientation.

[0044] FIG2(a) shows a cross-sectional view of a semiconductor device including an eDRAM including a DRAM, corresponding to step 2(a)-1 of a manufacturing process according to a first preferred embodiment of the present invention. Step 2(a)-1 includes: (i) depositing a high aspect ratio process (HARP) film or layer 101 on a SiN liner layer 10 included in a DRAM 11.

[0045] FIG2( b ) shows a cross-sectional view of a semiconductor device including an eDRAM with SRAM, corresponding to step 2( b )-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 2( b )-1 includes: (i) depositing a HARP film or layer 101 on the SiN liner layer 10 included in the SRAM 12.

[0046] FIG3(a) shows a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 3(a)-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 3(a)-1 includes: (i) polishing a HARP film or layer 101 within the DRAM 11 by chemical mechanical polishing (CMP); and (ii) stopping the CMP process on the SiN liner layer 10 within the DRAM 11 to form a post-CMP HARP film or layer 102.

[0047] FIG3( b ) shows a cross-sectional view of a semiconductor device including an eDRAM with SRAM, corresponding to step 3( b )-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 3( b )-1 includes: (i) polishing the HARP film or layer 101 within the SRAM 12 by chemical mechanical polishing (CMP); and stopping the CMP process on the SiN liner layer 10 within the SRAM 12 to form a post-CMP HARP film or layer 102.

[0048] FIG4(a) shows a cross-sectional view of a semiconductor device including an eDRAM with DRAM, corresponding to step 4(a)-1 of the manufacturing process according to the first preferred embodiment of the present invention. FIG4(b) shows a cross-sectional view of a semiconductor device including an eDRAM with SRAM, corresponding to step 4(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention. Steps 4(a)-1 for the DRAM and 4(b)-1 for the SRAM, respectively, include: (i) partially recessing the HARP film or HARP layer 101 within the DRAM 11 / SRAM 12 by wet etching or dry etching to form a partial HARP recess 13, wherein the dry etching method is reactive ion etching (RIE).

[0049] Figure 5(a) shows a cross-sectional view of a semiconductor device including an eDRAM with DRAM, corresponding to step 5(a)-1 of the manufacturing process according to the first preferred embodiment of the present invention. Figure 5(b) shows a cross-sectional view of a semiconductor device including an eDRAM with SRAM, corresponding to step 5(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 5(a)-1 for the DRAM and step 5(b)-1 for the SRAM, respectively, a non-selective wet etching process is performed to remove a portion of the HARP recess 13 in both DRAM 11 and SRAM 12, and to recess the SiN liner layer 10 by 10 to 15 nm to form a recessed SiN liner layer 14.

[0050] FIG6(a) shows a cross-sectional view of a semiconductor device including an eDRAM including a DRAM, corresponding to step 6(a)-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 6(a)-1 includes: (i) forming a plug mask 110 on the recessed silicon nitride liner layer 14 in the DRAM 11 to subsequently remove the recessed SiN liner layer 14 in the SRAM 12.

[0051] FIG6( b ) is a cross-sectional view of a semiconductor device including an eDRAM with SRAM, corresponding to step 6( b )-1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 6( b )-1 , it includes: (i) the recessed SiN liner layer 14 in the SRAM 12 region is not covered by the plug mask 110.

[0052] Figure 7(a) to Figure 7(f) 1 is a diagram illustrating a first embodiment of a manufacturing process related to removing a recessed SiN liner layer in a DRAM and SRAM according to a first preferred embodiment of the present invention.

[0053] FIG7( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 7( a )-1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 7( a )-1 , it includes: (i) when removing a majority of the recessed SiN liner layer 14 deposited on the fin cell 121 in the SRAM 12 by dry etching, the recessed SiN liner layer 14 in the DRAM 11 is protected from etching by a plug mask 110 .

[0054] FIG7( b ) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 7( b )-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 7( b )-1 includes: (i) removing a majority of the recessed SiN liner layer 14 deposited on the fin cell 121 within the SRAM 12 by dry etching, leaving a SiN liner layer 15 thereon.

[0055] FIG7( c ) shows a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 7( c )-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 7( c )-1 includes: (i) removing the plug mask 110 included in the DRAM 11 by a photoresist stripping process.

[0056] FIG7( d ) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 7( d )-1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 7( d )-1 , it includes: (i) during the removal of the plug mask 110 , the remaining SiN liner layer 15 and the fin unit 121 within the SRAM 12 are not etched.

[0057] FIG7(e) shows a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 7(e)-1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 7(e)-1, it includes: (i) removing the recessed SiN liner layer 14 on top of both the BOX 113 and the storage node 111 included in the DRAM 11 by wet etching to a desired depth within the DT structure to form a plug 115 (see FIG10(a)).

[0058] FIG7( f ) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 7( f )-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 7( f )-1 includes: (i) removing the remaining SiN liner layer 15 on the surface of the fin unit 121 in the SRAM 12 by wet etching.

[0059] Figure 8(a) to Figure 8(b) FIG. 2 shows a second embodiment of a manufacturing process related to removing a recessed SiN liner layer in an SRAM according to the first preferred embodiment of the present invention.

[0060] FIG8(a) shows a cross-sectional view of a semiconductor device including an eDRAM with DRAM, corresponding to step 8(a)-1 of the manufacturing process according to the first preferred embodiment of the present invention. FIG8(b) shows a cross-sectional view of a semiconductor device including an eDRAM with SRAM, corresponding to step 8(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention. Steps 8(a)-1 for the DRAM and 8(b)-1 for the SRAM, respectively, include: (i) after step 6(a)-1, during the removal of the recessed SiN liner layer 14 within the SRAM 12, the recessed SiN liner layer 14 within the DRAM 11 is not etched; and (ii) after step 6(b)-1, the recessed SiN liner layer 14 within the SRAM 12 is removed using a wet etch method using a mixture of fluorosilicic acid and silicic acid. The wet etch process temperature is typically below 100°C, and the nitride-to-oxide etch selectivity is typically approximately 200:1 to approximately 2000:1.

[0061] Figure 9(a) to Figure 9(h) FIG. 3 is a diagram illustrating a third embodiment of a manufacturing process for removing a recessed SiN liner layer in an SRAM according to the first preferred embodiment of the present invention.

[0062] FIG9(a) shows a cross-sectional view of a semiconductor device including an eDRAM with DRAM, corresponding to step 9(a)-1 of the manufacturing process according to the first preferred embodiment of the present invention. FIG9(b) shows a cross-sectional view of a semiconductor device including an eDRAM with SRAM, corresponding to step 9(b)-1 of the manufacturing process according to the first preferred embodiment of the present invention. Steps 9(a)-1 for the DRAM and 9(b)-1 for the SRAM respectively include: (i) forming an amorphous silicon (a-Si) hard mask 16 on top of the recessed SiN liner layer 14 within the DRAM 11 (see FIG5(a)), and forming a plug mask 110 on top of the a-Si hard mask 16 therein (see FIG9(a)); and (ii) forming an a-Si hard mask 16 on top of the recessed SiN liner layer 14 within the SRAM 12 (see FIG5(b)).

[0063] FIG9( c ) shows a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 9( c )-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 9( c )-1 includes: (i) removing the plug mask 110 on top of the a-Si hard mask 16 in the DRAM 11 by a photoresist stripping process.

[0064] FIG9( d ) is a cross-sectional view of a semiconductor device including an eDRAM with SRAM, corresponding to step 9( d )-1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 9( d )-1 , it includes: (i) in the process of removing the plug mask 110 on the top of the a-Si hard mask 16 in the DRAM 11 , the a-Si hard mask 16 on the top of the recessed SiN liner layer 14 in the SRAM 12 is selectively removed by wet etching, wherein the a-Si hard mask 16 is removed by high-temperature NH 4 OH.

[0065] FIG9(e) shows a cross-sectional view of a semiconductor device including an eDRAM with DRAM, corresponding to step 9(e)-1 of the manufacturing process according to the first preferred embodiment of the present invention. FIG9(f) shows a cross-sectional view of a semiconductor device including an eDRAM with SRAM, corresponding to step 9(f)-1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 9(e)-1 for the DRAM and step 9(f)-1 for the SRAM, respectively, the steps include: (i) maintaining the a-Si hard mask 16 (as shown in FIG9(c)) on top of the recessed SiN liner layer 14 in the DRAM 11; and (ii) removing the recessed SiN liner layer 14 (as shown in FIG5(b)) on top of the fin cell 121 in the SRAM 12 by wet etching, wherein the recessed SiN liner layer 14 is removed using high-temperature H3PO4.

[0066] FIG9( g) shows a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 9( g)-1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 9( g)-1, it includes: (i) removing the a-Si hard mask 16 on top of the recessed SiN liner layer 14 in the DRAM 11 by wet etching, wherein the a-Si hard mask 16 in the DRAM 11 is removed by high-temperature NH4OH.

[0067] FIG9(h) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 9(h)-1 of the manufacturing process according to the first preferred embodiment of the present invention. In step 9(h)-1, it includes: (i) during the removal of the a-Si hard mask 16, the fin cell 121 in the SRAM 12 is not etched.

[0068] FIG10( a ) is a cross-sectional view of a semiconductor device including an eDRAM having a DRAM, corresponding to step 10( a )-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 10( a )-1 includes: (i) step 7( e )-1 (as shown in FIG7( e )); or (i) step 8( a )-1; (ii) step 7( c )-1; and (iii) step 7( e )-1; or (i) step 9( g )-1 (as shown in FIG9( g )); and (ii) step 7( e )-1.

[0069] According to a second preferred embodiment of the present invention, a method for forming a plug 115 of a semiconductor device 1 is provided, wherein the semiconductor device 1 includes a deep trench (DT) structure 112 and a storage node 111 configured in the DT structure 112, the method comprising: (a) filling the DT structure 112 with a single layer of film and covering the storage node 111 (see the above step 1(b)-1); and (b) etching back the single layer of film to form the plug 115 located in the DT structure 112 and around the storage node 111, wherein the single layer of film forms a single liner layer, and the single liner layer is a silicon nitride liner layer (see the combination of the above steps 2(a)-1, 3(a)-1, 4(a)-1, 5(a)-1, 6(a)-1, 7(c)-1 and 7(e)-1). Step (a) further includes: step (a1): filling the DT structure 112 with a silicon nitride liner layer (see the above step 1(b)-1); and step (a2): forming a high aspect ratio process (HARP) layer 101 on the silicon nitride liner layer 10 (see the above step 2(a)-1). Step (b) further includes: step (b1): polishing the HARP layer 101 by chemical mechanical polishing (CMP), and stopping the CMP on the silicon nitride liner layer 10 (see the above step 3(a)-1); step (b2): partially recessing the HARP layer 101 by wet etching or dry etching (see the above step 4(a)-1); step (b3): recessing the HARP layer 101 and the silicon nitride liner layer 10 by non-selective wet etching (see the above steps 5(a)-1 and 5(b)-1); and step (b4): recessing the silicon nitride liner layer 10 to a desired depth within the DT structure 112 by an etching process to complete the plug 115 (see the above steps 7(e)-1 or 10(a)-1).

[0070] According to a third preferred embodiment of the present disclosure, a method for manufacturing a semiconductor device 1 includes: (a) forming a deep trench (DT) structure 112; (b) setting a storage node 111 having a top 1111 in the DT structure 112; forming a gap structure 1121 between the top 1111 and the DT structure 112 (see the above-mentioned step 1(a)-1); and (d) filling a single-layer dielectric material film in the gap structure 1121, and etching back the single-layer dielectric material film to form a plug 115 including a single dielectric material (for example, see the combination of the above-mentioned steps 2(a)-1, 3(a)-1, 4(a)-1, 5(a)-1, 6(a)-1, 7(c)-1 and 7(e)-1). Step (d) further includes: Step (d1): etching back the single-layer dielectric material film until the desired depth within the gap structure 1121 is reached to form a single liner layer, wherein the semiconductor device 1 is an embedded dynamic random access memory (eDRAM) 1, and the single liner layer includes a single dielectric material, surrounds the storage node 111, and forms a plug 115 (see the above step 7(e)-1 or step 10(a)-1), and the plug 115 is used to prevent the WL (not shown) from shorting to the DT structure 112.

[0071] According to a fourth preferred embodiment of the present invention, a semiconductor device 1 includes: a deep trench (DT) structure 112; a storage node 111 disposed within the DT structure 112 and having a top 1111; a void structure 1121 formed between the top 1111 and the DT structure 112; and a plug 115 comprising a single dielectric material and filling the void structure 1121 (see step 10(a)-1 above). The semiconductor device 1 is an embedded dynamic random access memory (eDRAM) 1 including a dynamic random access memory (DRAM) 11 and a static random access memory (SRAM) 12 (see step 1(c)-1 above). The plug 115 is a liner layer used to prevent a WL (not shown) from shorting to the DT structure 112. The DT structure 112 has a first top surface 1122, and the void structure 1121 has a second top surface 11211, with the first top surface 1122 and the second top surface 11211 being flush. The plug 115 has a third top surface 1151 , which is lower than the first top surface 1122 (see step 10 ( a ) - 1 above).

[0072] FIG10( b ) is a cross-sectional view of a semiconductor device including an eDRAM having an SRAM, corresponding to step 10( b )-1 of the manufacturing process according to the first preferred embodiment of the present invention. Step 10( b )-1 includes: (i) step 7( f )-1; or step 8( b )-1; or step 9( h).

[0073] Based on the foregoing description, the present invention discloses a method for forming a plug in a semiconductor device and a semiconductor device thereof, wherein the plug is used to prevent a WL within the semiconductor device from shorting to a DT structure also within the semiconductor device. Due to the use of a CMP hard stop liner process, the proposed method achieves relatively good batch-to-batch and intra-wafer uniformity. Furthermore, because the plug is formed from a single liner layer, exhibiting non-obviousness and novelty, the resulting topological profile within the plug region is relatively good.

[0074] Although the present invention has been described above by means of what are presently considered to be the most practical and preferred embodiments, it should be understood that the present invention is not necessarily limited to the disclosed embodiments. It is therefore intended to cover various modifications and similar structures included within the spirit and scope of the appended claims, and that the spirit and scope should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Claims

1. A method for forming a plug for a semiconductor device, wherein: The semiconductor device includes a deep trench structure and a storage node configured in the deep trench structure, and the method includes: Step (a) filling a single layer of film in the deep trench structure and covering the storage node; and Step (b) etching back the single-layer film to form a plug located in the deep trench structure and around the storage node, wherein the single-layer film forms a single liner layer. The deep trench structure has a first top surface, and a top surface of the plug closest to the first top surface is lower than the first top surface. The top surface of the plug, the sidewall of the storage node and the sidewall of the deep trench structure define a groove structure of the semiconductor device, and the groove structure surrounds the storage node.

2. The method according to claim 1, characterized in that The semiconductor device is an embedded dynamic random access memory, which includes an insulator silicon wafer and a buried oxide below the insulator silicon wafer. The plug is formed within the buried oxide below the insulator silicon wafer.

3. The method according to claim 2, characterized in that The semiconductor device further includes a substrate, and the step (a) further includes a step (a0): providing an insulator silicon wafer, wherein the insulator silicon wafer includes the substrate, the buried oxide, and the insulator silicon wafer.

4. The method according to claim 2, characterized in that The embedded dynamic random access memory further includes a dynamic random access memory and a static random access memory. The insulator silicon wafer included in the dynamic random access memory and the insulator silicon wafer included in the static random access memory have the same crystal orientation.

5. The method according to claim 2, characterized in that The embedded dynamic random access memory further includes a word line, and the plug is used to prevent the word line from being short-circuited with the deep trench structure.

6. The method according to claim 1, characterized in that The single liner layer is a silicon nitride liner layer.

7. The method according to claim 6, characterized in that The step (a) includes step (a1): filling the deep trench structure with the silicon nitride liner layer.

8. The method according to claim 7, characterized in that The step (a) further includes a step (a2): forming a high aspect ratio process layer on the silicon nitride liner layer.

9. The method according to claim 8, characterized in that The step (b) further comprises a step (b1): polishing the high aspect ratio process layer by chemical mechanical polishing, and making the chemical mechanical polishing stop on the silicon nitride liner layer.

10. The method according to claim 9, characterized in that The step (b) further includes a step (b2): making the high aspect ratio process layer partially concave by wet etching or dry etching.

11. The method according to claim 10, characterized in that The step (b) further includes a step (b3): recessing the high aspect ratio process layer and the silicon nitride liner layer by non-selective wet etching.

12. The method according to claim 11, characterized in that The step (b) further includes a step (b4): recessing the silicon nitride liner layer to a preset depth within the deep trench structure through an etching process to complete the plug.

13. The method according to claim 12, characterized in that The etching process is wet etching, and the silicon nitride / silicon oxide etching selectivity ratio of the silicon nitride liner layer is greater than 100:

1.

14. A method for manufacturing a semiconductor device, characterized in that: include: Step (a) forming a deep trench structure; Step (b) disposing a storage node having a top end in the deep trench structure; Step (c) forming a gap structure between the top and the deep trench structure; as well as Step (d) is to fill the void structure with a single-layer dielectric material film, and to etch back the single-layer dielectric material film to form a plug comprising a single dielectric material. The deep trench structure has a first top surface, the gap structure has a second top surface, the first top surface and the second top surface are flush with each other, and a top surface of the plug closest to the first top surface is lower than the first top surface. The top surface of the plug, the sidewall of the storage node and the sidewall of the deep trench structure define a groove structure of the semiconductor device, and the groove structure surrounds the storage node.

15. The method according to claim 14, characterized in that The semiconductor device is an embedded dynamic random access memory, and the step (d) further includes a step (d1): etching back the single-layer dielectric material film to a desired depth within the gap structure to form a single liner layer, wherein the single liner layer includes the single dielectric material, surrounds the storage node, and forms the plug, which is used to prevent the word line from short-circuiting with the deep trench structure.

16. A semiconductor device, characterized in that: include: Deep trench structure; a storage node disposed in the deep trench structure and having a top end; a gap structure formed between the top end and the deep trench structure; as well as a plug comprising a single dielectric material and filling the void structure, The deep trench structure has a first top surface, the gap structure has a second top surface, the first top surface and the second top surface are flush with each other, and a top surface of the plug closest to the first top surface is lower than the first top surface. The top surface of the plug, the sidewall of the storage node and the sidewall of the deep trench structure define a groove structure of the semiconductor device, and the groove structure surrounds the storage node.

17. The semiconductor device according to claim 16, wherein: It also includes a word line, wherein the semiconductor device is an embedded dynamic random access memory including a dynamic random access memory and a static random access memory, and the plug is a liner layer, which is used to prevent the word line from short-circuiting with the deep trench structure.

18. The semiconductor device according to claim 17, wherein: The liner layer is a silicon nitride liner layer, and the silicon nitride / silicon oxide etching selectivity ratio of the silicon nitride liner layer is greater than 100:1.

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