Semiconductor memory element and method of making the same

Abstract

A semiconductor memory element and a method of fabricating the same are disclosed. The semiconductor memory element includes a substrate, a dielectric layer on the substrate, a contact plug in the dielectric layer, wherein an upper portion of the contact plug protrudes from a top surface of the dielectric layer, wherein the upper portion of the contact plug serves as a first electrode, a buffer layer on the dielectric layer and beside the contact plug, a resistance switching layer beside the buffer layer, and a second electrode beside the resistance switching layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a resistive random access memory element and a method of fabricating the same. BACKGROUND

[0002] Resistive random access memory (RRAM) is a general name for reprogrammable devices that can be set in a low or high resistance state. RRAM is typically composed of a dielectric layer disposed between two electrodes. Some types of RRAM conduct by forming different filaments in localized regions of the dielectric. Other types of RRAM can conduct by changing the properties of the entire dielectric region.

[0003] RRAM stores information by using the variable resistance properties of a dielectric layer between two electrodes. This dielectric layer, which acts as a resistive layer, is normally insulating, but can be made conductive by the formation of a filament or conductive path after the application of a sufficiently high voltage (i.e., by a formation process). The formation of the conductive path can come from different mechanisms, including defects, metal migration, etc. Once formed, the filament can still be reset (i.e., broken, resulting in high resistance) or set (i.e., reformed, resulting in low resistance) by the application of appropriate voltages.

[0004] Current RRAM structures are typically single transistor single resistance vertical configurations, which are limited in size by the need for large currents. In addition, current RRAM structures require the fabrication of a bottom electrode, a resistance switching layer, and a top electrode in the memory region, thus there is an additional thickness of metal interlayer dielectric in the memory region relative to the peripheral circuit region, and there is a problem of low dielectric constant layer gap filling. SUMMARY

[0005] The main purpose of the present application is to provide a semiconductor memory element and a method of fabricating the same to solve the above-mentioned problems and shortcomings of the prior art.

[0006] According to one aspect of the present application, a semiconductor memory element is provided, comprising a substrate; a dielectric layer on the substrate; a contact plug in the dielectric layer, wherein an upper portion of the contact plug protrudes from a top surface of the dielectric layer, wherein the upper portion of the contact plug serves as a first electrode; a buffer layer on the dielectric layer and beside the contact plug; a resistance switching layer beside the buffer layer; and a second electrode beside the resistance switching layer.

[0007] According to an embodiment of the present application, the contact plug is electrically connected to a drain doped region of a transistor on the substrate, wherein the transistor comprises a gate, a source doped region, and the drain doped region.

[0008] According to an embodiment of the present application, the second electrode is electrically connected to a bit line extending along a first direction, and the source doped region is electrically connected to a source line in the substrate, wherein the source line extends along a second direction.

[0009] According to an embodiment of the present application, the first direction is orthogonal to the second direction.

[0010] According to an embodiment of the present application, a top surface of the upper portion of the contact plug is coplanar with a top surface of the buffer layer, a top surface of the resistance switching layer, and a top surface of the second electrode.

[0011] According to an embodiment of the present application, the buffer layer is a spacer buffer layer around the upper portion of the contact plug.

[0012] According to an embodiment of the present application, the resistance switching layer has a vertical portion on the buffer layer and a horizontal portion on the dielectric layer.

[0013] According to an embodiment of the present application, the contact plug comprises tungsten.

[0014] According to an embodiment of the present application, the buffer layer comprises a metal or a conductive transition metal oxide.

[0015] According to an embodiment of the present application, the metal comprises aluminum, titanium, tantalum, gold, silver, platinum, tungsten, nickel, iridium, or copper.

[0016] According to an embodiment of the present application, the conductive transition metal oxide comprises nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, strontium titanate, niobium oxide, or yttrium oxide.

[0017] According to an embodiment of the present application, the resistance switching layer comprises nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, strontium titanate, niobium oxide, or yttrium oxide.

[0018] According to an embodiment of the present application, the second electrode comprises titanium nitride or tantalum nitride.

[0019] Another aspect of the present application discloses a memory layout, comprising a transistor comprising a source doped region and a drain doped region; a contact plug on the drain doped region, wherein the contact plug serves as a first electrode; a buffer layer around the contact plug; a resistance switching layer around the buffer layer; and a second electrode beside the resistance switching layer.

[0020] According to an embodiment of the present application, the buffer layer is a spacer buffer layer around an upper portion of the contact plug.

[0021] According to an embodiment of the present invention, the second electrode is electrically connected to a bit line extending along a first direction, and the source doped region is electrically connected to a source line, wherein the source line extends along a second direction.

[0022] According to an embodiment of the present invention, the first direction is orthogonal to the second direction.

[0023] Another aspect of the present invention discloses a method for forming a semiconductor memory element. A substrate is provided; a dielectric layer is formed on the substrate; a contact plug is formed in the dielectric layer, wherein an upper portion of the contact plug protrudes from a top surface of the dielectric layer, wherein the upper portion of the contact plug serves as a first electrode; a buffer layer is formed on the dielectric layer and adjacent to the upper portion of the contact plug; a resistance switching layer is formed adjacent to the buffer layer; and a second electrode is formed adjacent to the resistance switching layer.

[0024] According to an embodiment of the present invention, the contact plug comprises tungsten.

[0025] According to an embodiment of the present invention, the buffer layer comprises a metal or a conductive transition metal oxide. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the memory layout shown in an embodiment of the present invention;

[0027] Figure 2 For along Figure 1 A schematic cross-sectional view shown by tangent I-I' in the diagram;

[0028] Figures 3 to 9 This is a schematic diagram illustrating a method for forming a semiconductor memory element according to an embodiment of the present invention.

[0029] Symbol Explanation

[0030] 100 base

[0031] 101 gate

[0032] 102 Source Doped Region

[0033] 103 Drain doped region

[0034] 210 Buffer Layer

[0035] 210S spacer buffer layer

[0036] 220 Resistor Switching Layer

[0037] 220L Resistor Switching Layer

[0038] 220h Horizontal section

[0039] 220V vertical section

[0040] 230 Second Electrode

[0041] 230L Second Electrode Layer

[0042] BL_odd odd column lines

[0043] BL_even even column line

[0044] BLE extension

[0045] CT, CTD, CTG contact plugs

[0046] CR storage array area

[0047] D1 First Direction

[0048] D2 Second Direction

[0049] IL1, IL2, IL3, IL4 dielectric layers

[0050] LR logic circuit area

[0051] M memory layout

[0052] MC memory unit

[0053] M1, M2, M3 metal layers

[0054] PR photoresist pattern

[0055] R1, R2, R3 concave areas

[0056] S0, S1, S2, S3, S4, S5 Top surface

[0057] SH Step Difference

[0058] SI insulation structure

[0059] SL1, SL2 source lines

[0060] T transistor

[0061] V1 and V2 vias

[0062] WL1 and WL2 character lines

[0063] WP top Detailed Implementation

[0064] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0065] Of course, other embodiments can be utilized or any structural, logical, and electrical changes can be made without departing from the scope of the embodiments described herein. Accordingly, the detailed description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of embodiments comprised therein.

[0066] In the following detailed description, different metal layers in a metal interconnect structure are denoted by Mn, where n is a positive integer, for example, M1 represents a first metal layer in a metal interconnect structure, M2 represents a second metal layer in a metal interconnect structure, and so on, and different vias in a metal interconnect structure are denoted by Vn, for example, V1 represents a via connecting M1 to M2, V2 represents a via connecting M2 to M3, and so on.

[0067] A high-density semiconductor memory device structure and layout, in particular a high-density resistive random access memory device structure and layout, is disclosed, which is characterized in that a protruding upper portion of a contact plug electrically connected to a drain doped region of a transistor serves as a first electrode of a memory storage structure, and a resistive-switching layer and a second electrode are disposed in a recessed area beside the protruding upper portion of the contact plug, such that the first electrode, the resistive-switching layer and the second electrode form a horizontal configuration.

[0068] Referring to Figure 1 and Figure 2 wherein Figure 1 is a schematic diagram of a single-transistor dual-resistor (1T2R) memory layout according to an embodiment of the present application, Figure 2 is a schematic diagram of a cross-section along the tangent line I-I' in Figure 1 As shown in Figure 1 and Figure 2 , a memory layout M is composed of a plurality of 1T2R memory cells MC. According to an embodiment of the present application, the memory layout M comprises a plurality of contact plugs CT arranged in a checkerboard pattern, including a plurality of contact plugs CTD electrically connected to drain doped regions 103 of transistors T, and a plurality of contact plugs CTG interleaved with the contact plugs CTD. According to an embodiment of the present application, the transistors T comprise a gate 101, a source doped region 102 and a drain doped region 103. According to an embodiment of the present application, the contact plugs CTD electrically connected to the drain doped regions 103 serve as a first electrode of a memory storage structure.

[0069] According to an embodiment of the present application, the memory layout M further comprises a plurality of odd column bit lines BL_odd (only three are shown in the figure) and a plurality of even column bit lines BL_even (only two are shown in the figure) extending along a first direction Dl. According to an embodiment of the present application, the odd column bit lines BL_odd and the even column bit lines BL_even can be disposed in different metal interconnect layers. For example, according to an embodiment of the present application, the odd column bit lines BL_odd can be disposed in the M3 metal layer, while the even column bit lines BL_even can be disposed in the M2 metal layer. According to an embodiment of the present application, the odd column bit lines BL_odd and the even column bit lines BL_even can be electrically connected to the second electrodes 230 of the memory storage structures, respectively.

[0070] According to an embodiment of the present application, the memory layout M further comprises a plurality of word lines WLl and WL2 (only two are shown in the figure) extending along a second direction D2, and a plurality of source lines SLl and SL2 (only two are shown in the figure) extending along the second direction D2 and electrically connected to the source doped regions 102 of the transistors T. According to an embodiment of the present application, the word lines WLl and WL2 can be polysilicon word lines, but are not limited thereto. According to an embodiment of the present application, the source lines SLl and SL2 can be heavily doped regions, such as N+ doped regions, disposed in the substrate 100. According to an embodiment of the present application, the first direction Dl is orthogonal to the second direction D2.

[0071] According to an embodiment of the present application, the memory layout M further comprises a buffer layer 210 surrounding the protruding upper portion WP of each contact plug CT. According to an embodiment of the present application, the memory layout M further comprises a resistance switching layer 220 surrounding the buffer layer 210. According to an embodiment of the present application, the second electrode 230 is located next to the resistance switching layer 220. According to an embodiment of the present application, the second electrode 230 comprises titanium nitride or tantalum nitride.

[0072] From Figure 2 As can be seen, the memory cell MC comprises a substrate 100, such as a silicon substrate. The source doped region 102 and the drain doped region 103 of the transistor T are disposed in the substrate 100. In addition, there can be insulating structures SI in the substrate 100 for isolating adjacent transistor elements. The memory cell MC further comprises a dielectric layer ILl, such as a silicon oxide layer, located on the substrate 100. According to an embodiment of the present application, the contact plug CT is located in the dielectric layer ILl, and an upper portion WP of the contact plug CT protrudes from a top surface SI of the dielectric layer ILl. As previously described, the upper portion WP of the contact plug CT serves as the first electrode of the memory storage structure. According to an embodiment of the present application, the contact plug CT can comprise tungsten, but is not limited thereto.

[0073] According to embodiments of the present application, the buffer layer 210 is located on the dielectric layer IL1 and beside the contact plug CT, surrounding the upper portion WP of the contact plug CT. According to embodiments of the present application, the buffer layer 210 is a spacer buffer layer. According to embodiments of the present application, the buffer layer 210 can comprise a metal or a conductive transition metal oxide. According to embodiments of the present application, the metal can comprise aluminum, titanium, tantalum, gold, silver, platinum, tungsten, nickel, iridium, or copper, but not limited thereto. According to embodiments of the present application, the conductive transition metal oxide can comprise nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, strontium titanate, niobium oxide, or yttrium oxide, but not limited thereto.

[0074] According to embodiments of the present application, a top surface S2 of the upper portion WP of the contact plug CT is coplanar with a top surface S3 of the buffer layer 210, a top surface S4 of the resistance switching layer 220, and a top surface S5 of the second electrode 230. According to embodiments of the present application, the resistance switching layer 220 has a vertical portion 220v located on the buffer layer 210 and a horizontal portion 220h located on the dielectric layer IL1. According to embodiments of the present application, the vertical portion 220v directly contacts the buffer layer 210, and the horizontal portion 220h directly contacts the dielectric layer IL1.

[0075] According to embodiments of the present application, a dielectric layer IL2, such as a low dielectric constant material layer, can be further provided on the dielectric layer IL1, but not limited thereto. According to embodiments of the present application, an M1 metal layer can be formed in the dielectric layer IL2. According to embodiments of the present application, the M1 metal layer is a plurality of metal pads respectively provided on the corresponding second electrode 230. According to embodiments of the present application, a dielectric layer IL3, such as a low dielectric constant material layer, can be further provided on the dielectric layer IL2, but not limited thereto. According to embodiments of the present application, an M2 metal layer and a V1 via can be formed in the dielectric layer IL3. According to embodiments of the present application, a dielectric layer IL4, such as a low dielectric constant material layer, can be further provided on the dielectric layer IL3, but not limited thereto. According to embodiments of the present application, an M3 metal layer and a V2 via can be formed in the dielectric layer IL4. According to embodiments of the present application, the second electrode 203 located directly above the gate 101 of the transistor T is electrically connected to the odd column bit line BL_odd located in the M3 metal layer via the M1 metal layer, the V1 via, the M2 metal layer, and the V2 via. According to embodiments of the present application, the second electrode 230 located between the drain doped regions 103 of the adjacent two transistors T is electrically connected to the even column bit line BL_even located in the M2 metal layer via the M1 metal layer and the V1 via.

[0076] From Figure 1As can be seen, the odd column bit line BL_odd and the even column bit line BL_even do not overlap each other, and the even column bit line BL_even needs to be electrically connected to the second electrode 230 between the drain doped regions 103 of two adjacent transistors T via an extension part BLE extending along the second direction D2. According to the embodiment of the present application, the second electrodes 230 on the same column are electrically connected to the odd column bit line BL_odd and the even column bit line BL_even extending along the first direction D1, respectively, and the source doped regions 102 of the transistors T are electrically connected to the source lines SL1 and SL2 extending along the second direction D2 in the substrate 100, respectively.

[0077] Referring to Figures 3 to 9 , a schematic diagram of a method for forming a semiconductor memory element according to an embodiment of the present application is shown, in which the same regions, layers or elements are denoted by the same reference numerals. As shown, Figure 3 , a substrate 100, for example, a silicon substrate, is provided. The substrate 100 comprises a logic circuit region LR and a memory array region CR. Transistors T are formed on the substrate 100, including a gate 101, a source doped region 102 and a drain doped region 103. There can be insulating structures SI in the substrate 100 for isolating adjacent transistor elements. A dielectric layer IL1, for example, a silicon oxide layer, but not limited to this, is further formed on the substrate 100. In the dielectric layer IL1, a plurality of contact plugs CT are formed. At this time, the top surface SO of the dielectric layer IL1 is flush with the top surface S2 of the contact plugs CT. Then, a photoresist pattern PR is formed on the dielectric layer IL1, in which the photoresist pattern PR covers the logic circuit region LR, but exposes the memory array region CR.

[0078] As shown, Figure 4 , then, an etching process, for example, a dry etching process, is performed using the photoresist pattern PR as an etching resist mask to etch away a part of the thickness of the dielectric layer IL1 in the memory array region CR, so as to form a recessed region R1. Then, the remaining photoresist pattern PR is removed. At this time, the top surface SI of the dielectric layer IL1 in the memory array region CR is lower than the top surface S2 of the contact plugs CT, and also lower than the top surface SO of the dielectric layer IL1 in the logic circuit region LR, so that a step height SH is formed at the interface between the logic circuit region LR and the memory array region CR. In the memory array region CR, the upper part WP of the contact plugs CT protrudes from the top surface SI of the dielectric layer IL1. As mentioned before, the upper part WP of the contact plugs CT serves as a first electrode. Subsequently, a cleaning process can be performed to remove possible oxides.

[0079] As shown, Figure 5As shown, a buffer layer 210L is then conformally deposited over the logic circuit region LR and the memory array region CR. According to embodiments of the present application, the buffer layer 210L can be deposited by atomic layer deposition, chemical vapor deposition, or physical vapor deposition. Since the upper portion WP of the contact plug CT protrudes above the top surface S1 of the dielectric layer IL1 in the memory array region CR, the buffer layer 210L conformally covers the upper portion WP of the contact plug CT, forming a protrusion structure in the memory array region CR. According to embodiments of the present application, the buffer layer 210L can comprise a metal or a conductive transition metal oxide. For example, the metal can comprise aluminum, titanium, tantalum, gold, silver, platinum, tungsten, nickel, iridium, or copper. The conductive transition metal oxide can comprise nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, strontium titanate, niobium oxide, or yttrium oxide.

[0080] As shown in FIG. 2B, after the buffer layer 210L is deposited, a buffer layer recessing process is then performed on the buffer layer 210L, such as dry etching or ion milling, to form a spacer buffer layer 210 on the sidewall of the upper portion WP of the contact plug CT. According to embodiments of the present application, the spacer buffer layer 210S is formed on the step height SH at the interface between the logic circuit region LR and the memory array region CR. At this time, a recessed region R2 is formed between the spacer buffer layer 210 and the top surface S1 of the dielectric layer IL1. Figure 6 As shown in FIG. 2C, after the spacer buffer layer 210 is formed, a resistance switching layer 220L is then conformally deposited over the logic circuit region LR and the memory array region CR. According to embodiments of the present application, the resistance switching layer 220L can be deposited by atomic layer deposition, chemical vapor deposition, or physical vapor deposition. According to embodiments of the present application, the resistance switching layer 220L can comprise nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, strontium titanate, niobium oxide, or yttrium oxide. According to embodiments of the present application, the resistance switching layer 220L can have a vertical portion 220v on the buffer layer 210 and a horizontal portion 220h on the dielectric layer IL1. According to embodiments of the present application, the resistance switching layer 220L is conformally deposited in the recessed region R2, forming a recessed region R3 on the surface of the resistance switching layer 220L.

[0081] Figure 7 As shown in FIG. 2D, after the resistance switching layer 220L is deposited, a resistance switching layer recessing process is then performed on the resistance switching layer 220L, such as dry etching or ion milling, to form a resistance switching layer spacer 220 on the sidewall of the upper portion WP of the contact plug CT. According to embodiments of the present application, the resistance switching layer spacer 220S is formed on the step height SH at the interface between the logic circuit region LR and the memory array region CR. At this time, a recessed region R4 is formed between the resistance switching layer spacer 220 and the top surface S1 of the dielectric layer IL1.

[0082] As shown in FIG. 2E, after the resistance switching layer spacer 220 is formed, a resistance switching layer 230L is then conformally deposited over the logic circuit region LR and the memory array region CR. According to embodiments of the present application, the resistance switching layer 230L can be deposited by atomic layer deposition, chemical vapor deposition, or physical vapor deposition. According to embodiments of the present application, the resistance switching layer 230L can comprise nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, strontium titanate, niobium oxide, or yttrium oxide. According to embodiments of the present application, the resistance switching layer 230L can have a vertical portion 230v on the resistance switching layer spacer 220 and a horizontal portion 230h on the dielectric layer IL1. According to embodiments of the present application, the resistance switching layer 230L is conformally deposited in the recessed region R4, forming a recessed region R5 on the surface of the resistance switching layer 230L. Figure 8 ​As shown, a second electrode layer 230L is then deposited on the resistor switching layer 220L of the logic circuit region LR and the memory array region CR. According to an embodiment of the invention, the second electrode layer 230L may fill the recessed region R3 on the surface of the resistor switching layer 220L. According to an embodiment of the invention, for example, the second electrode layer 230L may comprise titanium nitride or tantalum nitride. According to an embodiment of the invention, the method for depositing the second electrode layer 230L may include, but is not limited to, atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

[0083] like Figure 9 As shown, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove a portion of the thickness of the second electrode layer 230L and the resistance switching layer 220L, thus forming the memory cell MC. Subsequent fabrication steps include dielectric layer deposition and the fabrication of metal interconnect structures (including bit lines), which are well known to those skilled in the art and therefore will not be described in detail. The memory cell MC of this invention includes a substrate 100; a dielectric layer IL1 located on the substrate 100; a contact plug CT located in the dielectric layer IL1, wherein the upper part WP of the contact plug CT protrudes from the top surface S1 of the dielectric layer IL1, wherein the upper part WP of the contact plug CT serves as the first electrode; a buffer layer 210 located on the dielectric layer IL1 and adjacent to the contact plug CT; a resistance switching layer 220 located adjacent to the buffer layer 210; and a second electrode 230 located adjacent to the resistance switching layer 220.

[0084] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor memory element, characterized in that, Include: Base; The dielectric layer is located on the substrate; A contact plug is located in the dielectric layer, wherein the upper part of the contact plug protrudes from the top surface of the dielectric layer, and wherein the upper part of the contact plug serves as a first electrode; A buffer layer is located on the dielectric layer and next to the contact plug; The resistor switching layer is located next to the buffer layer; and The second electrode is located next to the resistance switching layer, wherein the top surface of the upper part of the contact plug is coplanar with the top surface of the buffer layer, the top surface of the resistance switching layer and the top surface of the second electrode, and the contact plug is cylindrical in shape.

2. The semiconductor memory device as claimed in claim 1, wherein, The contact plug is electrically connected to the drain doped region of a transistor on the substrate, wherein the transistor includes a gate, a source doped region, and the drain doped region.

3. The semiconductor memory element as claimed in claim 2, wherein, The second electrode is electrically connected to a bit line extending along a first direction, and the source doped region is electrically connected to a source line located in the substrate, wherein the source line extends along a second direction.

4. The semiconductor memory element as claimed in claim 3, wherein, The first direction is orthogonal to the second direction.

5. The semiconductor memory element as claimed in claim 1, wherein, The buffer layer is a gap wall buffer layer surrounding the upper part of the contact plug.

6. The semiconductor memory element as claimed in claim 5, wherein, The resistor switching layer has a vertical portion located on the buffer layer and a horizontal portion located on the dielectric layer.

7. The semiconductor memory element as claimed in claim 1, wherein, The contact plug contains tungsten.

8. The semiconductor memory element as claimed in claim 1, wherein, The buffer layer contains metal or conductive transition metal oxide.

9. The semiconductor memory element as claimed in claim 8, wherein, The metal may contain aluminum, titanium, tantalum, gold, silver, platinum, tungsten, nickel, iridium, or copper.

10. The semiconductor memory element of claim 8, wherein, The conductive transition metal oxide includes nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, strontium titanate, niobium oxide, or yttrium oxide.

11. The semiconductor memory element as claimed in claim 1, wherein, The resistor switching layer contains nickel oxide, tantalum oxide, titanium oxide, hafnium oxide, tungsten oxide, zirconium oxide, aluminum oxide, strontium titanate, niobium oxide, or yttrium oxide.

12. The semiconductor memory element as claimed in claim 1, wherein, The second electrode contains titanium nitride or tantalum nitride.

13. A memory layout comprising: A transistor consists of a source doped region and a drain doped region; A contact plug is located on the drain doped region, wherein the contact plug serves as the first electrode; A buffer layer surrounds the contact plug; A resistor switching layer surrounds the buffer layer; as well as The second electrode is located next to the resistance switching layer, wherein the top surface of the upper part of the contact plug is coplanar with the top surface of the buffer layer, the top surface of the resistance switching layer and the top surface of the second electrode, and the contact plug is cylindrical in shape.

14. The memory layout of claim 13, wherein, The buffer layer is a spacer wall buffer layer surrounding the upper part of the contact plug.

15. The memory layout of claim 13, wherein, The second electrode is electrically connected to a bit line extending along a first direction, and the source doped region is electrically connected to a source line extending along a second direction.

16. The memory layout of claim 15, wherein, The first direction is orthogonal to the second direction.

17. A method of forming a semiconductor memory element, comprising: Provide a base; A dielectric layer is formed on this substrate; A contact plug is formed in the dielectric layer, wherein, The upper part of the contact plug protrudes from the top surface of the dielectric layer, wherein the upper part of the contact plug serves as the first electrode; A buffer layer is formed on the dielectric layer and next to the upper part of the contact plug; A resistance switching layer is formed next to the buffer layer; and A second electrode is formed next to the resistance switching layer, wherein the top surface of the upper part of the contact plug is coplanar with the top surface of the buffer layer, the top surface of the resistance switching layer and the top surface of the second electrode, and the contact plug is cylindrical in shape.

18. The method of claim 17, wherein, The contact plug contains tungsten.

19. The method of claim 17, wherein, The buffer layer contains metal or conductive transition metal oxide.

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