Array substrate, manufacturing method thereof and display panel

Abstract

The present invention provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate comprises: a substrate; a thin-film transistor located on the substrate, the thin-film transistor comprising: a semiconductor layer located on the substrate; a drain electrode and a source electrode located on both sides of the semiconductor layer; a gate insulating layer located on the semiconductor layer; a gate electrode located on the gate insulating layer, the drain electrode, the gate electrode, and the film layer between the drain electrode and the gate electrode forming a first capacitor, and the source electrode, the gate electrode, and the film layer between the source electrode and the gate electrode forming a second capacitor. The thin-film transistor is a driving thin-film transistor, and the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor. By making the capacitance value of the second capacitor corresponding to the source electrode side larger than the capacitance value of the first capacitor corresponding to the drain electrode side, when the driving thin-film transistor is turned on, the potential loss caused by parasitic capacitance during the coupling stage before the display panel emits light can be suppressed, thereby ensuring that the intensity of the light-emitting devices at all positions on the panel is approximately the same, thereby improving the display uniformity of the panel.

Description

Technical field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display panel. [Background Technology]

[0002] Organic Light-Emitting Diode (OLED) display panels have a promising future. Compared to Liquid Crystal Display (LCD) panels, OLED display panels offer self-luminescence, wide viewing angles, fast response times, light weight, thinness, simple structure, and low cost. Based on the pixel drive method, OLED display panels can be divided into passive matrix organic light-emitting diode (PMOLED) display panels and active matrix organic light-emitting diode (AMOLED) display panels.

[0003] AMOLED display panels, a hot topic in the display industry, offer advantages over liquid crystal display (LCD) panels, including a wider color gamut, wider viewing angle, higher contrast, and faster response time. AMOLED display panels use current to drive OLED devices for light emission. However, in actual AMOLED display panels, factors such as parasitic capacitance interference between metal traces can cause different currents generated by the TFT drivers at different locations on the panel, resulting in varying luminous intensities in the OLED devices and an uneven display.

[0004] Therefore, the existing technology has defects and needs to be improved and developed. [Summary of the invention]

[0005] The invention provides an array substrate, a manufacturing method thereof and a display panel, so as to improve the display unevenness of the panel.

[0006] In order to solve the above problems, the present invention provides an array substrate, comprising: a substrate; a thin film transistor located on the substrate, the thin film transistor comprising: a semiconductor layer located on the substrate; a drain and a source located on both sides of the semiconductor layer; a gate insulating layer located on the semiconductor layer; a gate located on the gate insulating layer, the drain, the gate, and the film layer between the drain and the gate constitute a first capacitor, and the source, the gate, and the film layer between the source and the gate constitute a second capacitor; wherein the thin film transistor is a driving thin film transistor, and the capacitance value of the first capacitor is less than the capacitance value of the second capacitor.

[0007] The thin film transistor further comprises:

[0008] The semiconductor layer has a channel region, and the channel region connects the drain and the source;

[0009] The cross-sectional area of ​​a first portion of the channel region connected to the drain is smaller than the cross-sectional area of ​​a second portion of the channel region connected to the source.

[0010] The cross-sectional width of the first portion is smaller than the cross-sectional width of the second portion.

[0011] The channel region has a transition portion, which connects the first portion and the second portion. The cross-sectional shape of the transition portion includes a trapezoid or an arc shape.

[0012] The gate insulating layer includes a first sub-gate insulating layer and a second sub-gate insulating layer. The first sub-gate insulating layer is located on the side close to the drain, and the second sub-gate insulating layer is located on the side close to the source. The thickness of the first sub-gate insulating layer is greater than that of the second sub-gate insulating layer.

[0013] In order to solve the above problems, the present invention provides a method for manufacturing an array substrate, comprising: providing a substrate; forming a semiconductor material layer on the substrate, and patterning and performing a first surface treatment on the semiconductor material layer to form an active layer; performing a second surface treatment on partial areas on both sides of the active layer to form a source and a drain on both sides of the active layer, respectively, and the portion of the active layer that has not undergone the second surface treatment constitutes a semiconductor layer; forming a gate insulating layer on the semiconductor layer; forming a metal layer on the gate insulating layer, and patterning the metal layer to form a gate; wherein the semiconductor layer has a channel region, the channel region connects the drain and the source, and the cross-sectional area of ​​the first portion of the channel region connected to the drain is smaller than the cross-sectional area of ​​the second portion of the channel region connected to the source.

[0014] The semiconductor material layer is subjected to a first surface treatment through a first mask, so that the cross-sectional width of the first portion of the channel region is smaller than the cross-sectional width of the second portion of the formed channel region.

[0015] The step of forming a gate insulating layer on the semiconductor layer specifically includes:

[0016] forming a first gate insulating material layer on a side of the semiconductor layer close to the drain electrode through a third mask;

[0017] forming a second gate insulating material layer on the semiconductor layer through a fourth mask;

[0018] Among them, the first gate insulating material layer and the second gate insulating material layer formed on the side of the semiconductor layer close to the drain constitute a first sub-gate insulating layer, and the second gate insulating material layer formed on the side of the semiconductor layer close to the source constitutes a second sub-gate insulating layer.

[0019] The step of forming a gate insulating layer on the semiconductor layer specifically includes:

[0020] forming a gate insulating layer on the semiconductor layer through a half-tone mask;

[0021] The gate insulating layer includes a first sub-gate insulating layer and a second sub-gate insulating layer. The first sub-gate insulating layer is located on the side close to the drain, and the second sub-gate insulating layer is located on the side close to the source. The thickness of the first sub-gate insulating layer is greater than that of the second sub-gate insulating layer.

[0022] In order to solve the above problems, the present invention provides a display panel, which includes an array substrate as described above, a plurality of thin film transistors, and the plurality of thin film transistors are distributed in an array.

[0023] The beneficial effects of the present invention are as follows: Different from the prior art, the present invention provides an array substrate, a manufacturing method thereof, and a display panel, wherein the array substrate comprises: a substrate; a thin film transistor located on the substrate, the thin film transistor comprising: a semiconductor layer located on the substrate; a drain electrode and a source electrode located on both sides of the semiconductor layer; a gate insulating layer located on the semiconductor layer; a gate electrode located on the gate insulating layer, the drain electrode, the gate electrode, and the film layer between the drain electrode and the gate electrode forming a first capacitor, and the source electrode, the gate electrode, and the film layer between the source electrode and the gate electrode forming a second capacitor; wherein the thin film transistor is a driving thin film transistor, and the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor. By making the capacitance value of the second capacitor corresponding to the source electrode side larger than the capacitance value of the first capacitor corresponding to the drain electrode side, when the driving thin film transistor is turned on, the potential loss caused by parasitic capacitance during the coupling stage before the display panel emits light can be suppressed, thereby ensuring that the intensity of the light-emitting devices at various positions on the panel is approximately the same, thereby improving the display uniformity of the panel.

Brief Description of the Drawings

[0024] Figure 1 A schematic structural diagram of an array substrate provided in an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a driving TFT configuration structure provided by an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of another driving TFT configuration provided by an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of a process flow of an array substrate provided by an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of the structure for forming a semiconductor layer, a drain electrode, and a source electrode provided in an embodiment of the present invention. [Specific implementation method]

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It is particularly noted that the following examples are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. Similarly, the following examples are only some embodiments of the present invention and are not intended to be exhaustive. All other embodiments obtained by those of ordinary skill in the art without creative effort are intended to fall within the scope of protection of the present invention.

[0030] In addition, the terms first, second, third, etc. mentioned in the present invention can be used to describe various elements here, but these elements should not be limited to these terms. These terms are only used to distinguish these elements from each other. For example, without departing from the scope of the present invention, the first can be referred to as the second, and similarly, the second can be referred to as the first. Therefore, the terms used are used to illustrate and understand the present invention, rather than to limit the present invention. In the various drawings, units with similar structures are represented by the same reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, certain well-known parts may not be shown in the drawings.

[0031] In addition, in each drawing, similar units are denoted by the same reference numerals. When a component is described as being “connected to” another component, the two components can be understood to be directly “connected” or one component can be indirectly “connected to” the other component through an intermediate component.

[0032] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings.

[0033] like Figure 1 As shown, the present invention provides an array substrate, comprising: a substrate 110; a thin film transistor (not numbered in the figure) located on the substrate 110, the thin film transistor comprising: a semiconductor layer 120 located on the substrate 110; a drain 130 and a source 140 located on both sides of the semiconductor layer 120; a gate insulating layer 150 located on the semiconductor layer 120; a gate 160 located on the gate insulating layer 150, the drain 130, the gate 160 and the film layer between the drain 130 and the gate 160 constitute a first capacitor (not numbered in the figure), the source 140, the gate 160 and the film layer between the source 140 and the gate 160 constitute a second capacitor (not numbered in the figure); wherein the thin film transistor is a driving thin film transistor, and the capacitance value of the first capacitor is less than the capacitance value of the second capacitor.

[0034] In addition, it should be noted that Figure 1 Only structures related to the embodiments of the present invention are shown. The array substrate of the present invention may further include other components and / or structures for realizing the complete functions of the array substrate.

[0035] Specifically, the substrate 110 may be a glass substrate, or may include a glass substrate and one or more layers of thin films located on the glass substrate. The one or more layers of thin films may be conductive films and / or functional films. Furthermore, the substrate 110 may be a flexible substrate. Generally, the material of the flexible substrate may include PI (polyimide). The thin film transistor includes: a semiconductor layer 120 located on the substrate 110; a drain electrode 130 and a source electrode 140 located on both sides of the semiconductor layer 120; a gate insulating layer 150 located on the semiconductor layer 120; and a gate electrode 160 located on the gate insulating layer 150. The drain electrode 130, the gate electrode 160, and the film layer between the drain electrode 130 and the gate electrode 160 constitute a first capacitor, and the source electrode 140, the gate electrode 160, and the film layer between the source electrode 140 and the gate electrode 160 constitute a second capacitor. The thin film transistor is a driving thin film transistor. The capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor, that is, the capacitance value of the first capacitor on the source electrode 140 side is smaller than the capacitance value of the second capacitor on the drain electrode 130 side.

[0036] Specifically, the driving TFT of a traditional panel is configured as a self-aligning gate transistor. When the TFT is turned on, the capacitance Cgs on the source 140 side (the capacitance formed by the source 140 and the gate 160, as well as other film layers therebetween) is equal to the capacitance Cgd on the drain 130 side (the capacitance formed by the drain 130 and the gate 160, as well as other film layers therebetween). For OLED display panels, reducing the Cgd of the driving TFT will reduce the potential loss caused by the coupling stage before the OLED emits light, while increasing Cgs is equivalent to increasing the storage capacitance, which is beneficial for suppressing the potential loss caused by parasitic capacitance during the coupling stage. The less potential loss, the easier it is to obtain a panel with excellent display uniformity. However, the channel width of the driving TFTs currently designed are all the same, that is, Cgs = Cgd, which affects the display uniformity of the panel.

[0037] Based on this, through the display panel of the embodiment of the present invention, the capacitance value of the second capacitor corresponding to the source 140 side is greater than the capacitance value of the first capacitor corresponding to the drain 130 side. When the thin film transistor is driven to turn on, the potential loss caused by parasitic capacitance in the coupling stage before the panel emits light can be suppressed, thereby ensuring that the intensity of the light-emitting devices at various positions of the final panel is close to the same, thereby improving the display uniformity of the panel.

[0038] The thin film transistor further comprises:

[0039] The semiconductor layer 120 has a channel region A1 , and the channel region A1 connects the drain 130 and the source 140 ;

[0040] The cross-sectional area of ​​the first portion A11 of the channel region A1 connected to the drain 130 is smaller than the cross-sectional area of ​​the second portion A12 of the channel region A1 connected to the source 140 .

[0041] like Figure 2 As shown, the semiconductor layer 120 has a channel region A1, which is used for the movement of carriers in the thin film transistor. The channel region A1 connects the drain 130 and the source 140. Among them, the cross-sectional area of ​​the first part A11 of the channel region A1 connected to the drain 130 is smaller than the cross-sectional area of ​​the second part A12 of the channel region A1 connected to the source 140. According to the reference data, the formula for capacitance is C = εS / 4πkd. Among them, ε is a constant, S is the facing area of ​​the capacitor plates (such as the facing area between the source 140 and the gate 160, or the facing area between the drain 130 and the gate 160), d is the distance between the capacitor plates (such as the distance between the source 140 and the gate 160, or the distance between the drain 130 and the gate 160), and k is the electrostatic force constant. The cross-sectional area of ​​the first portion A11 of the channel region A1 connecting to the drain electrode 130 is smaller than the cross-sectional area of ​​the second portion A12 of the channel region A1 connecting to the source electrode 140. Accordingly, the capacitance of the first capacitor corresponding to the drain electrode 130 is smaller than the capacitance of the second capacitor corresponding to the source electrode 140. This reduces potential loss due to parasitic capacitance during the coupling phase before the panel emits light when the thin-film transistor is driven on, thereby ensuring that the intensity of the light-emitting devices at all locations on the panel is approximately the same, improving the display uniformity of the panel.

[0042] The cross-sectional width W1 of the first portion A11 is smaller than the cross-sectional width W2 of the second portion A12 .

[0043] Specifically, if Figure 2 As shown, the cross-sectional width W1 of the first portion A11 where the channel region A1 is connected to the drain 130 is smaller than the cross-sectional width W2 of the second portion A12 where the channel region A1 is connected to the source 140. Correspondingly, the capacitance value of the first capacitor corresponding to the drain 130 side is smaller than the capacitance value of the second capacitor corresponding to the source 140 side. When the thin film transistor is driven to turn on, the potential loss caused by parasitic capacitance in the coupling stage before the panel emits light can be suppressed, thereby ensuring that the intensity of the light-emitting devices at each position of the final panel is close to the same, thereby improving the display uniformity of the panel.

[0044] The channel region A1 has a transition portion, which connects the first portion A11 and the second portion A12 . The cross-sectional shape of the transition portion includes a trapezoid or an arc shape.

[0045] Specifically, if Figure 3As shown, the channel region A1 further includes a transition portion A13, which connects the first portion A11 and the second portion A12 and serves to transition the change in cross-sectional area between the first portion A11 and the second portion A12. It should be noted that the cross-sectional shape of the transition portion is not particularly limited, as long as it serves to connect the first portion A11 and the second portion A12 and transition the change in cross-sectional area between the first portion A11 and the second portion A12. For example, the cross-sectional shape of the transition portion may include a trapezoidal or arc-shaped shape.

[0046] Among them, the gate insulation layer 150 includes a first sub-gate insulation layer 151 and a second sub-gate insulation layer 152. The first sub-gate insulation layer 151 is located on the side close to the drain 130, and the second sub-gate insulation layer 152 is located on the side close to the source 140. The thickness of the first sub-gate insulation layer 151 is greater than the thickness of the second sub-gate insulation layer 152.

[0047] Specifically, because the thickness of the first sub-gate insulating layer 151 near the drain 130 is greater than the thickness of the second sub-gate insulating layer 152 near the source 140, the distance between the drain 130 and the gate 160 is greater than the distance between the source 140 and the gate 160. According to the capacitance formula C = εS / 4πkd, the capacitance of the first capacitor on the drain 130 side is smaller than the capacitance of the second capacitor on the source 140 side. This can suppress potential loss caused by parasitic capacitance during the coupling phase before the panel emits light when the thin film transistor is driven on, thereby ensuring that the intensity of the light-emitting devices at all locations on the panel is approximately the same, thereby improving the display uniformity of the panel.

[0048] Based on the array substrate described in the above embodiment of the present invention, the embodiment of the present invention further provides a method for manufacturing the array substrate, such as Figure 4 Shown, including:

[0049] Step S101: providing a substrate 110;

[0050] Step S102: forming a semiconductor material layer on the substrate 110, and patterning and performing a first surface treatment on the semiconductor material layer to form an active layer;

[0051] Step S103: performing a second surface treatment on a portion of both sides of the active layer, so as to form a drain electrode 130 and a source electrode 140 on both sides of the active layer, respectively. The portion of the active layer not subjected to the second surface treatment constitutes the semiconductor layer 120;

[0052] Step S104: forming a gate insulating layer 150 on the semiconductor layer 120;

[0053] Step S105: A metal layer (not shown in the figure) is formed on the gate insulating layer 150, and the metal layer is patterned to form a gate 160; wherein the semiconductor layer 120 has a channel region A1, the channel region A1 connects the drain 130 and the source 140, and the cross-sectional area of ​​the first portion A11 of the channel region A1 connected to the drain 130 is smaller than the cross-sectional area of ​​the second portion A12 of the channel region A1 connected to the source 140.

[0054] Figure 5 The structure formed from step S101 to step S103 includes: a substrate 110, a semiconductor layer 120 located on the substrate 110, and a source 140 and a drain 130 located on both sides of the semiconductor layer 120. Figure 3 The process steps of the structure shown may be: after providing a substrate 110, a semiconductor material layer may be formed on the substrate 110, and the semiconductor material layer may be patterned and subjected to a first surface treatment to form an active layer. The first surface treatment may be a doping treatment to form a channel region A1. After the active layer is formed, a second surface treatment may be performed on portions of both sides of the active layer to form a source electrode 140 and a drain electrode 130 on both sides of the active layer, respectively. The portion of the active layer not subjected to the second surface treatment constitutes the semiconductor layer 120. The second surface treatment may be a conductorization treatment. The portions of both sides of the active layer subjected to the second surface treatment respectively form the drain electrode 130 and the source electrode 140, and the other portions of the active layer not subjected to the second surface treatment form the semiconductor layer 120.

[0055] Figure 1The structure formed from steps S104 to S105 is shown, including: a substrate 110; a semiconductor layer 120 located on the substrate 110; a drain electrode 130 and a source electrode 140 located on both sides of the semiconductor layer 120; a gate insulating layer 150 located on the semiconductor layer 120; and a gate electrode 160 located on the gate insulating layer 150. The drain electrode 130, the gate electrode 160, and the film layer between the drain electrode 130 and the gate electrode 160 constitute a first capacitor, and the source electrode 140, the gate electrode 160, and the film layer between the source electrode 140 and the gate electrode 160 constitute a second capacitor. The gate insulating layer 150 includes a first sub-gate insulating layer 151 and a second sub-gate insulating layer 152. The first sub-gate insulating layer 151 is located on a side close to the drain electrode 130, and the second sub-gate insulating layer 152 is located on a side close to the source electrode 140. The thickness of the first sub-gate insulating layer 151 is greater than the thickness of the second sub-gate insulating layer 152. Because the thickness of the first sub-gate insulating layer 151 near the drain 130 is greater than the thickness of the second sub-gate insulating layer 152 near the source 140, the distance between the drain 130 and the gate 160 is greater than the distance between the source 140 and the gate 160. According to the capacitance formula C = εS / 4πkd, the capacitance of the first capacitor on the drain 130 side is smaller than the capacitance of the second capacitor on the source 140 side. This can suppress potential loss caused by parasitic capacitance during the coupling phase before the panel emits light when the thin-film transistor is driven on, thereby ensuring that the intensity of the light-emitting devices at all locations on the panel is approximately the same, thereby improving the display uniformity of the panel.

[0056] The active layer and semiconductor layer 120 may be made of materials including ITO (indium tin oxide), IZO (indium zinc oxide), or IGZO (indium gallium zinc oxide). The gate insulating layer 150 may be made of an oxide, such as silicon oxide (SiOx). The metal layer may be made of one or more of Mo (molybdenum), Al (aluminum), Cu (copper), and Ti (titanium). Furthermore, the metal layer may be made of ITO (indium tin oxide), IZO (indium zinc oxide), or IGZO (indium gallium zinc oxide).

[0057] The semiconductor material layer is subjected to a first surface treatment through a first mask, so that the cross-sectional width W1 of the first portion A11 of the channel region A1 is smaller than the cross-sectional width W2 of the second portion A12 of the channel region A1 to be formed.

[0058] Specifically, the semiconductor material layer may be subjected to a first surface treatment using a first mask. The first surface treatment may be a doping treatment, so that the cross-sectional width W1 of the first portion A11 of the channel region A1 is smaller than the cross-sectional width W2 of the second portion A12 of the channel region A1 to be formed. The first mask has a first opening, and the width of the portion of the first opening corresponding to the side close to the drain 130 is smaller than the width of the portion of the first opening corresponding to the side close to the source 140. Figure 2 As shown, the cross-sectional width W1 of the first portion A11 where the channel region A1 is connected to the drain 130 is smaller than the cross-sectional width W2 of the second portion A12 where the channel region A1 is connected to the source 140. Correspondingly, the capacitance value of the first capacitor corresponding to the drain 130 side is smaller than the capacitance value of the second capacitor corresponding to the source 140 side. When the thin film transistor is driven to turn on, the potential loss caused by parasitic capacitance in the coupling stage before the panel emits light can be suppressed, thereby ensuring that the intensity of the light-emitting devices at each position of the final panel is close to the same, thereby improving the display uniformity of the panel.

[0059] The step S104 is to form a gate insulating layer 150 on the semiconductor layer 120, which specifically includes:

[0060] Using a second mask, forming a first gate insulating material layer on a side of the semiconductor layer 120 close to the drain electrode 130 ;

[0061] forming a second gate insulating material layer on the semiconductor layer 120 through a third mask;

[0062] Among them, the first gate insulating material layer and the second gate insulating material layer formed on the side of the semiconductor layer 120 close to the drain 130 constitute a first sub-gate insulating layer 151, and the second gate insulating material layer formed on the side of the semiconductor layer 120 close to the source 140 constitute a second sub-gate insulating layer 152.

[0063] Specifically, two masks (also called photomasks) may be used to form gate insulating layers 150 of different thicknesses in different regions on the semiconductor layer 120. For example, the steps of forming the gate insulating layers 150 of different thicknesses on the semiconductor layer 120 may include forming a first gate insulating material layer on a side of the semiconductor layer 120 near the drain electrode 130 using a second mask; and forming a second gate insulating material layer on the semiconductor layer 120 using a third mask; wherein the first gate insulating material layer and the second gate insulating material layer formed on the side of the semiconductor layer 120 near the drain electrode 130 constitute a first sub-gate insulating layer 151, and the second gate insulating material layer formed on the side of the semiconductor layer 120 near the source electrode 140 constitutes a second sub-gate insulating layer 152.

[0064] Specifically, because the thickness of the first sub-gate insulating layer 151 near the drain 130 is greater than the thickness of the second sub-gate insulating layer 152 near the source 140, the distance between the drain 130 and the gate 160 is greater than the distance between the source 140 and the gate 160. According to the capacitance formula C = εS / 4πkd, the capacitance of the first capacitor on the drain 130 side is smaller than the capacitance of the second capacitor on the source 140 side. This can suppress potential loss caused by parasitic capacitance during the coupling phase before the panel emits light when the thin film transistor is driven on, thereby ensuring that the intensity of the light-emitting devices at all locations on the panel is approximately the same, thereby improving the display uniformity of the panel.

[0065] The step S104 is to form a gate insulating layer 150 on the semiconductor layer 120, which specifically includes:

[0066] Forming a gate insulating layer 150 on the semiconductor layer 120 using a half-tone mask;

[0067] Among them, the gate insulation layer 150 includes a first sub-gate insulation layer 151 and a second sub-gate insulation layer 152. The first sub-gate insulation layer 151 is located on the side close to the drain 130, and the second sub-gate insulation layer 152 is located on the side close to the source 140. The thickness of the first sub-gate insulation layer 151 is greater than the thickness of the second sub-gate insulation layer 152.

[0068] Specifically, a half-tone mask (half-tone) and a half-tone process can be used to form a photoresist layer (not shown) of varying thicknesses on the semiconductor layer 120, thereby forming the gate insulating layer 150 on the semiconductor layer 120. The gate insulating layer 150 includes a first sub-gate insulating layer 151 and a second sub-gate insulating layer 152. The first sub-gate insulating layer 151 is located on a side close to the drain electrode 130, and the second sub-gate insulating layer 152 is located on a side close to the source electrode 140. The thickness of the first sub-gate insulating layer 151 is greater than that of the second sub-gate insulating layer 152. Since the thickness of the first sub-gate insulating layer 151 near the drain 130 side is greater than the thickness of the second sub-gate insulating layer 152 near the source 140 side, correspondingly, the capacitance value of the first capacitor on the drain 130 side is smaller than the capacitance value of the second capacitor on the source 140 side. When the thin film transistor is driven to turn on, the potential loss caused by parasitic capacitance in the coupling stage before the panel emits light can be suppressed, thereby ensuring that the intensity of the light-emitting devices at various positions on the final panel is close to the same, thereby improving the display uniformity of the panel.

[0069] Furthermore, a lift-off process can be used to achieve different thicknesses within the same layer. For example, a first gate insulating material layer is deposited only on the semiconductor layer 120 near the drain electrode 130 using a mask. The mask is then removed and a second gate insulating material layer is deposited over the entire semiconductor layer 120. Shadow masking can be achieved by blocking areas where film formation is not required, thereby creating different thicknesses within the same layer.

[0070] It should be understood that the specific structure and manufacturing process of the array substrate of the embodiment of the present invention can be referred to the embodiment of the manufacturing method of the array substrate described above, and will not be described in detail here. In addition, it should be noted that the limiting conditions for forming the manufacturing method of the embodiment of the present invention can also be applied to the structure of the embodiment of the present invention.

[0071] Based on the array substrate and its manufacturing method described in the above embodiments of the present invention, the present invention also provides a display panel, which includes an array substrate as described above, a plurality of thin film transistors, and the plurality of thin film transistors are distributed in an array.

[0072] Specifically, the display panel is not particularly limited and may be an OLED panel. Furthermore, the display panel may be a Mini LED panel or a Micro LED panel. By using a display panel including an array substrate according to any of the embodiments of the present invention, when the thin film transistor is turned on, potential loss caused by parasitic capacitance during the coupling phase before the panel emits light can be suppressed, thereby ensuring that the intensity of the light-emitting devices at all positions on the panel is approximately the same, thereby improving the display uniformity of the panel.

[0073] According to the above, the present invention provides an array substrate, a manufacturing method thereof, and a display panel, wherein the array substrate comprises: a substrate; a thin film transistor located on the substrate, the thin film transistor comprising: a semiconductor layer located on the substrate; a drain electrode and a source electrode located on both sides of the semiconductor layer; a gate insulating layer located on the semiconductor layer; a gate electrode located on the gate insulating layer, wherein the drain electrode, the gate electrode, and the film layer between the drain electrode and the gate electrode constitute a first capacitor, and the source electrode, the gate electrode, and the film layer between the source electrode and the gate electrode constitute a second capacitor; wherein the thin film transistor is a driving thin film transistor, and the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor. By making the capacitance value of the second capacitor corresponding to the source electrode side larger than the capacitance value of the first capacitor corresponding to the drain electrode side, when the driving thin film transistor is turned on, the potential loss caused by parasitic capacitance during the coupling stage before the display panel emits light can be suppressed, thereby ensuring that the intensity of the light-emitting devices at each position of the panel is close to the same, thereby improving the display uniformity of the panel.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: include: substrate; a thin film transistor located on the substrate, the thin film transistor comprising: a semiconductor layer located on the substrate; a drain electrode and a source electrode located on both sides of the semiconductor layer; a gate insulating layer located on the semiconductor layer; a gate electrode located on the gate insulating layer, the drain electrode, the gate electrode, and a film layer between the drain electrode and the gate electrode forming a first capacitor, and the source electrode, the gate electrode, and a film layer between the source electrode and the gate electrode forming a second capacitor; The thin film transistor is a driving thin film transistor, the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor; the gate insulating layer includes a first sub-gate insulating layer and a second sub-gate insulating layer, the first sub-gate insulating layer is located on a side close to the drain electrode, and the second sub-gate insulating layer is located on a side close to the source electrode, the thickness of the first sub-gate insulating layer is greater than the thickness of the second sub-gate insulating layer, and both the first sub-gate insulating layer and the second sub-gate insulating layer overlap with the semiconductor layer; the source electrode, the drain electrode, and the semiconductor layer are arranged in the same layer; The semiconductor layer has a channel region, and the channel region connects the drain and the source; A cross-sectional area of ​​a first portion of the channel region connected to the drain is smaller than a cross-sectional area of ​​a second portion of the channel region connected to the source.

2. The array substrate according to claim 1, wherein: The cross-sectional width of the first portion is smaller than the cross-sectional width of the second portion.

3. The array substrate according to claim 1, wherein: The channel region has a transition portion, the transition portion connects the first portion and the second portion, and a cross-sectional shape of the transition portion includes a trapezoidal shape or an arc shape.

4. A method for manufacturing an array substrate, characterized in that: include: providing a substrate; forming a semiconductor material layer on the substrate, and patterning and performing a first surface treatment on the semiconductor material layer to form an active layer; Performing a second surface treatment on partial areas on both sides of the active layer to form a source electrode and a drain electrode on both sides of the active layer, respectively, and a portion of the active layer not subjected to the second surface treatment constitutes a semiconductor layer, and the source electrode, the drain electrode and the semiconductor layer are arranged on the same layer; forming a gate insulating layer on the semiconductor layer, the gate insulating layer comprising a first sub-gate insulating layer and a second sub-gate insulating layer, the first sub-gate insulating layer being located on a side close to the drain electrode, the second sub-gate insulating layer being located on a side close to the source electrode, the first sub-gate insulating layer being thicker than the second sub-gate insulating layer, and both the first sub-gate insulating layer and the second sub-gate insulating layer overlapping the semiconductor layer; forming a metal layer on the gate insulating layer, and patterning the metal layer to form a gate; The semiconductor layer has a channel region, the channel region connects the drain and the source, and the cross-sectional area of ​​a first portion of the channel region connected to the drain is smaller than the cross-sectional area of ​​a second portion of the channel region connected to the source.

5. The method for manufacturing an array substrate according to claim 4, wherein: The first surface treatment is performed on the semiconductor material layer through a first mask, so that the cross-sectional width of the first portion of the channel region is smaller than the cross-sectional width of the formed second portion of the channel region.

6. The method for manufacturing an array substrate according to claim 4, wherein: The step of forming a gate insulating layer on the semiconductor layer specifically includes: forming a first gate insulating material layer on a side of the semiconductor layer close to the drain electrode through a second mask; forming a second gate insulating material layer on the semiconductor layer through a third mask; The first gate insulating material layer and the second gate insulating material layer formed on the side of the semiconductor layer close to the drain constitute a first sub-gate insulating layer, and the second gate insulating material layer formed on the side of the semiconductor layer close to the source constitutes a second sub-gate insulating layer.

7. The method for manufacturing an array substrate according to claim 4, wherein: The gate insulating layer is formed on the semiconductor layer, wherein the gate insulating layer includes a first sub-gate insulating layer and a second sub-gate insulating layer. Specifically, the gate insulating layer includes: The first sub-gate insulating layer and the second sub-gate insulating layer are formed on the semiconductor layer through a half-tone mask.

8. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 3, and there are a plurality of thin film transistors, which are distributed in an array.

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