Semiconductor Device and Electronic Equipment

Abstract

The present application provides a semiconductor device and an electronic device. The semiconductor device includes: a base layer, a P-anode region, an N+ collector / source region, a plurality of first P-field rings, an oxide isolation layer, a plurality of first polysilicon field plates, an insulating isolation layer, and a first metal field plate. The depth of the first P-field ring on the base layer is greater than the depth of the P-anode region on the base layer; the orthographic projection of the first metal field plate on the base layer and the orthographic projection of the first polysilicon field plate closest to the N+ collector / source region on the base layer have an overlapping region. In this way, when a reverse bias voltage is applied to the PN junction, the extension regions of the first P-field rings with large depths can be connected, the space charge region can be more effectively expanded, the electric field peak can be reduced, thereby effectively increasing the reverse voltage and stability, so that both the voltage requirement of the terminal can be guaranteed and the fast recovery product can retain good recovery and voltage drop characteristics.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing, and more particularly, to a semiconductor device and an electronic device. Background Art

[0002] With the development of Fast Recovery Diode (FRD) devices, their breakdown voltage performance has gradually improved and the recovery time has gradually decreased. The potential hazards of the original Field Plate-Field Limiting Ring (FP-FLR) shallow junction polycrystalline field plate terminal technology in terms of stability and reliability have become increasingly serious. For example, the voltage of the FP-FLR shallow junction polycrystalline field plate is relatively stable at low voltages, but may exhibit reduced voltage reliability at high voltages, and is prone to large leakage current and soft voltage drift after aging. The design of the polycrystalline shallow junction field plate terminal has many voltage dividing rings. Especially for high-voltage products, the multi-ring terminal is easily affected by external factors such as storage and packaging, leading to early product failure. Summary of the Invention

[0003] To overcome the above deficiencies in the prior art, an object of this application is to provide a semiconductor device, which includes:

[0004] A base layer;

[0005] A P-anode region and an N+ collector / source region formed on the base layer;

[0006] A plurality of first P-field rings formed between the P-anode region and the N+ collector / source region, and the depth of the first P-field rings on the base layer is greater than the depth of the P-anode region on the base layer;

[0007] An oxide isolation layer located on the base layer;

[0008] A plurality of first polysilicon field plates located on the oxide isolation layer, and each first polysilicon field plate corresponds to one of the first P-field rings;

[0009] An insulating isolation layer located on the first polysilicon field plates;

[0010] A first metal field plate located on the insulating isolation layer, and the orthographic projection of the first metal field plate on the base layer and the orthographic projection of the first polysilicon field plate closest to the N+ collector / source region on the base layer have an overlapping area.

[0011] In a possible implementation, the depth of the first P-field rings is from 10 micrometers to 30 micrometers.

[0012] In a possible implementation, the spacing between the first P-field rings gradually increases from the first P-field ring closest to the P-anode region to the first P-field ring closest to the N+ collector / source region.

[0013] In a possible implementation, the length of the first polysilicon field plate on the oxide isolation layer is 10 to 15 micrometers, and the length is along the direction from the P-anode region to the N+ collector / source region.

[0014] In a possible implementation, the length of at least one of the first polysilicon field plates closer to the P-anode region is less than the length of at least one of the first polysilicon field plates closer to the N+ collector / source region, and the length is along the direction from the P-anode region to the N+ collector / source region.

[0015] In a possible implementation, in a set of the first polysilicon field plates and the first P-field rings corresponding in position, the difference between the length of the first polysilicon field plate and the length of the first P-field ring is 10 to 30 micrometers, and the length is along the direction from the P-anode region to the N+ collector / source region.

[0016] In a possible implementation, the length of the first metal field plate is at least 10 micrometers longer than the length of the first polysilicon field plate closest to the N+ collector / source region.

[0017] In a possible implementation, the semiconductor device further includes a second P-field ring between the first P-field ring closest to the P-anode region and the P-anode region, the second P-field ring has at least partial overlap with the P-anode region, and the depth of the second P-field ring is the same as the depth of the first P-field ring.

[0018] In a possible implementation, the semiconductor device further includes two second polysilicon field plates on the oxide isolation layer, and the orthographic projections of the two second polysilicon field plates on the base layer at least partially overlap with the P-anode region and the N+ collector / source region respectively;

[0019] The semiconductor device further includes two second metal field plates on the insulation isolation layer, and the orthographic projections of the two second metal field plates on the base layer at least partially overlap with the P-anode region and the N+ collector / source region respectively.

[0020] Another object of the present application is to provide an electronic device, characterized in that the electronic device includes the semiconductor device provided by the present application.

[0021] Compared with the prior art, the present application has the following beneficial effects:

[0022] A semiconductor device and an electronic device provided by an embodiment of the present application can, by means of the depth of the first P-field ring in the semiconductor device and adding a first metal field plate at a position corresponding to the first P-field ring closest to the N+ collector / source region, connect the extension regions of the first P-field rings with large depths when a reverse bias voltage is applied to the PN junction, more effectively expand the space charge region, reduce the electric field peak, and thus effectively improve the reverse voltage and stability. In this way, both the voltage requirement of the terminal can be ensured, and the fast-recovery product can retain good recovery and voltage drop characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can also be obtained based on these drawings without creative efforts.

[0024] Figure 1 One of the schematic diagrams of the semiconductor device provided by an embodiment of the present application;

[0025] Figure 2 Another schematic diagram of the semiconductor device provided by an embodiment of the present application;

[0026] Figure 3 Another schematic diagram of the semiconductor device provided by an embodiment of the present application;

[0027] Figure 4 Another schematic diagram of the semiconductor device provided by an embodiment of the present application;

[0028] Figure 5 Another schematic diagram of the semiconductor device provided by an embodiment of the present application;

[0029] Figure 6 Schematic diagram of a semiconductor device in the prior art. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0031] Accordingly, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0032] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings.

[0033] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0034] In addition, the terms "horizontal", "vertical", "overhanging", etc. do not mean that the components are required to be absolutely horizontal or overhanging, but may be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but may be slightly inclined.

[0035] In the description of the present application, it should also be noted that unless otherwise clearly defined and limited, the terms "set", "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0036] Please refer to Figure 1 , Figure 1 which is a schematic diagram of a semiconductor device provided for this embodiment. The semiconductor device may include a fast recovery diode (FRD) device. The semiconductor device includes a base layer 110, a P-anode region 120, an N+ collector / source region 130, a plurality of first P-field rings 141, an oxide isolation layer 150, a plurality of first polysilicon field plates 161, an insulating isolation layer 170, and a first metal field plate 181.

[0037] The P-anode region 120 and the N+ collector / source region 130 are formed on the base layer 110. In this embodiment, the P-anode region 120 and the N+ collector / source region 130 can be formed by doping P-type impurities and N-type impurities.

[0038] The plurality of first P-field rings 141 are formed between the P-anode region 120 and the N+ collector / source region 130. In this embodiment, a plurality of photolithography windows can be formed on the base layer 110 and P-type impurity implantation is performed, and after high-temperature diffusion, the plurality of first P-field rings 141 are formed. The depth of the first P-field ring 141 on the base layer 110 is greater than the depth of the P-anode region 120 on the base layer 110. In this embodiment, a 1200°C high-temperature N2 push-junction process can be used to form the plurality of first P-field rings 141.

[0039] The oxidation isolation layer 150 is located on the base layer 110. The oxidation isolation layer 150 can cover the first polysilicon field plate 161 and at least part of the P-anode region 120 and the N+ collector / source region 130. In this embodiment, the oxidation isolation layer 150 can be silicon dioxide (SiO2).

[0040] A plurality of the first polysilicon field plates 161 are located on the oxidation isolation layer 150, and each of the first polysilicon field plates 161 corresponds to one of the first P-field rings 141.

[0041] The insulation isolation layer 170 is located on the first polysilicon field plate 161. The insulation isolation layer 170 can cover the first polysilicon field plate 161 and the exposed oxidation isolation layer 150.

[0042] The first metal field plate 181 is located on the insulation isolation layer 170. The orthographic projection of the first metal field plate 181 on the base layer 110 and the orthographic projection of the first polysilicon field plate 161 closest to the N+ collector / source region 130 on the base layer 110 have an overlapping area. The material of the first metal field plate 181 can be aluminum (Al).

[0043] Based on the above design, in the solution provided in this embodiment, by adjusting the depth of the first P-field ring 141 in the semiconductor device and adding a first metal field plate 181 at the position corresponding to the first P-field ring 141 closest to the N+ collector / source region 130, when a reverse bias voltage is applied to the PN junction, the extended regions of the first P-field rings 141 with large depths can be connected, effectively expanding the space charge region and reducing the electric field peak, thereby effectively increasing the reverse voltage and stability. In this way, both the voltage requirement of the terminal can be ensured, and the fast recovery product can retain good recovery and voltage drop characteristics.

[0044] In some possible implementation manners, the depth of the first P-field ring 141 is from 10 micrometers to 30 micrometers. For example, please refer to Figure 2 , Figure 2 where the depth B1 shown is from 10 micrometers to 30 micrometers.

[0045] In some possible implementation manners, from the first P-field ring 141 closest to the P-anode region 120 to the first P-field ring 141 closest to the N+ collector / source region 130, the spacing between the first P-field rings 141 gradually increases. For example, please refer to Figure 3 , Figure 3 where among the lengths C1 to C6 shown, C1 < C2 < C3 < C4 < C5 < C6. In this embodiment, multiple photolithography windows with an equal difference increase in spacing can be formed on the base layer 110 by photolithography, and then P-type impurity implantation is performed to form multiple first P-field rings 141.

[0046] In some possible implementation manners, the length of the first polysilicon field plate 161 on the oxidation isolation layer 150 is from 10 micrometers to 15 micrometers, and the length is along the direction from the P-anode region 120 to the N+ collector / source region 130. For example, please refer to Figure 4 , Figure 4 where among the lengths A1 to A7 shown, A1 to A7 are all from 10 micrometers to 15 micrometers.

[0047] In some possible implementation manners, the length of at least one first polysilicon field plate 161 closer to the P-anode region 120 is less than the length of at least one first polysilicon field plate 161 closer to the N+ collector / source region 130, and the length is along the direction from the P-anode region 120 to the N+ collector / source region 130.

[0048] In one example, the lengths of the first polysilicon field plates 161 from the one closest to the P-anode region 120 to the one closest to the N+ collector / source region 130 increase in sequence. For example, please refer to Figure 4 ,Figure 4 Among the lengths A1 to A7 shown, A1 < A2 < A3 < A4 < A5 < A6 < A7.

[0049] In another example, the lengths of some of the first polysilicon field plates 161 may also be equal. For example, referring to Figure 4 , Figure 4 Among the lengths A1 to A7 shown, A1 < A2, A2 = A3, A3 < A4, A4 = A5, A5 < A6 < A7.

[0050] In some possible implementations, in a set of the first polysilicon field plates 161 and the first P-field ring 141 corresponding in position, the difference between the length of the first polysilicon field plate 161 and the length of the first P-field ring 141 is 10 to 30 micrometers, and the length is the length in the direction from the P-anode region 120 to the N+ collector / source region 130. For example, referring to Figure 4 and Figure 5 , Figure 5 the lengths E1 to E7 shown and Figure 4 the lengths A1 to A7 shown, the length ranges of A1 - E1, A2 - E2, A3 - E3, A4 - E4, A5 - E5, A6 - E6, A7 - E7 are all 10 micrometers to 30 micrometers.

[0051] In some possible implementations, the length of the first metal field plate 181 is at least 10 micrometers longer than the length of the first polysilicon field plate 161 closest to the N+ collector / source region 130. For example, referring to Figure 4 , Figure 4 the lengths D1 and A7 shown, D1 - A7 = 10 micrometers.

[0052] In some possible implementations, referring again to Figure 1 , the semiconductor device further includes a second P-field ring 142 located between the first P-field ring 141 closest to the P-anode region 120 and the P-anode region 120. The second P-field ring 142 and the P-anode region 120 have at least partial overlap, and the depth of the second P-field ring 142 is the same as the depth of the first P-field ring 141. The second P-field ring 142 and the first P-field ring 141 are made of the same material and are both formed by P-type impurity doping.

[0053] In some possible implementations, referring again to Figure 1 , the semiconductor device further includes two second polysilicon field plates 162 located on the oxide isolation layer 150. The orthographic projections of the two second polysilicon field plates 162 on the base layer 110 respectively have at least partial overlap with the P-anode region 120 and the N+ collector / source region 130.

[0054] The semiconductor device further includes two second metal field plates 182 located on the insulating isolation layer 170, and the positive projections of the two second metal field plates 182 on the base layer 110 at least partially coincide with the P-anode region 120 and the N+ collector / source region 130, respectively.

[0055] Please refer to Figure 6 , Figure 6 which is a schematic diagram of a semiconductor device in the prior art. Compared with the semiconductor device shown in Figure 6 , in the semiconductor device provided in this embodiment, the deep-junction first P-field rings 141 are adopted, and the first metal field plate 181 is additionally provided. Among them, a plurality of the first P-field rings 141 can obtain doping windows with gradually increasing spacing through one-time photolithography, and then through one-time implantation and high-temperature diffusion, respective diffusion regions are formed. When an external reverse bias voltage is applied, the PN junction depletion region first expands in the region of the second P-field ring 142. As the voltage increases and the electric field strengthens, the depletion regions of the second P-field ring 142 and the first P-field ring 141 closest to the second P-field ring 142 are connected. And so on, finally the depletion regions of all the first P-field rings 141 are all connected together. Under the combined action of the first polysilicon field plate 161 and the first metal field plate 181 closest to the N+ collector / source region 130, the electric field distribution is more stable. Compared with the original shallow-junction terminal, when the main junction depth remains unchanged, the depletion regions of each region at the terminal become wider and the field plates become shorter, reducing the electric field spikes caused by the influence of the outside world on the field plates. Through wafer comparison, the reverse leakage current is significantly reduced, and the parameter decay after aging is reduced. Compared with the prior art, the semiconductor device provided in this embodiment has the advantages of smaller terminal occupation area, more stable HTRB reliability of the breakdown voltage, easier control during the production and manufacturing process, and stronger packaging and storage compatibility ability.

[0056] Based on the same inventive concept, this embodiment also provides an electronic device, characterized in that the electronic device includes the semiconductor device provided in this embodiment.

[0057] In summary, a semiconductor device and an electronic device provided in an embodiment of the present application, by increasing the depth of the first P-field rings in the semiconductor device and adding a first metal field plate at the position corresponding to the first P-field ring closest to the N+ collector / source region, when a reverse bias voltage is applied to the PN junction, the expansion regions of the first P-field rings with large depths can be connected, the space charge region can be more effectively expanded, and the electric field spikes can be reduced, thereby effectively improving the reverse voltage and stability. In this way, both the voltage requirement of the terminal can be ensured, and the good recovery and voltage drop characteristics of the fast-recovery product can be retained.

[0058] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0059] As described above, the above are only various embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A base layer; A P-anode region and an N+ collector / source region formed on the base layer; A plurality of first P-field rings formed between the P-anode region and the N+ collector / source region, the depth of the first P-field rings on the base layer being greater than the depth of the P-anode region on the base layer; An oxide isolation layer located on the base layer; A plurality of first polysilicon field plates located on the oxide isolation layer, each of the first polysilicon field plates corresponding to one of the first P-field rings; An insulating isolation layer located on the first polysilicon field plates; A first metal field plate located on the insulating isolation layer, the orthographic projection of the first metal field plate on the base layer having an overlapping region with the orthographic projection of the first polysilicon field plate closest to the N+ collector / source region on the base layer.

2. The semiconductor device according to claim 1, characterized in that, The depth of the first P-field rings is from 10 microns to 30 microns.

3. The semiconductor device according to claim 1, wherein From the first P-field ring closest to the P-anode region to the first P-field ring closest to the N+ collector / source region, the spacing between the first P-field rings gradually increases.

4. The semiconductor device according to claim 1, wherein The length of the first polysilicon field plates on the oxide isolation layer is from 10 microns to 15 microns, and the length is the length in the direction from the P-anode region to the N+ collector / source region.

5. The semiconductor device according to claim 1, characterized in that, The length of at least one of the first polysilicon field plates closer to the P-anode region is less than the length of at least one of the first polysilicon field plates closer to the N+ collector / source region, and the length is the length in the direction from the P-anode region to the N+ collector / source region.

6. The semiconductor device according to claim 1, characterized in that, In a corresponding set of the first polysilicon field plates and the first P-field rings, the difference in length between the first polysilicon field plates and the first P-field rings is from 10 to 30 microns, and the length is the length in the direction from the P-anode region to the N+ collector / source region.

7. The semiconductor device according to claim 1, wherein, The length of the first metal field plate is at least 10 microns longer than the length of the first polysilicon field plate closest to the N+ collector / source region.

8. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a second P-field ring between the first P-field ring closest to the P-anode region and the P-anode region, the second P-field ring having at least partial overlap with the P-anode region, and the depth of the second P-field ring being the same as the depth of the first P-field ring.

9. The semiconductor device according to claim 8, wherein, The semiconductor device further includes two second polysilicon field plates located on the oxide isolation layer, the orthographic projections of the two second polysilicon field plates on the base layer having at least partial overlap with the P-anode region and the N+ collector / source region respectively; The semiconductor device further includes two second metal field plates located on the insulating isolation layer, the orthographic projections of the two second metal field plates on the base layer having at least partial overlap with the P-anode region and the N+ collector / source region respectively.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device according to any one of claims 1-9.

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