A flexible two-dimensional ferroelectric synapse transistor and a preparation method thereof

Abstract

The application discloses a flexible two-dimensional ferroelectric neural synapse transistor and a preparation method thereof. The flexible two-dimensional ferroelectric neural synapse transistor comprises a flexible substrate, a gate electrode which is an organic conductive polymer thin film and is formed on the flexible substrate, a gate dielectric layer which is an organic ferroelectric polymer thin film and is formed on the gate electrode, a channel which is a two-dimensional semiconductor thin film and is formed on the gate dielectric layer, and source and drain electrodes which are organic conductive polymer thin films and are formed on both sides of the channel. The neural synapse transistor can realize neural synapse characteristic simulation and obtain stable neural synapse short-term plasticity in different bending states, and can be used in highly bending-resistant wearable neural morphological computing electronic equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a flexible two-dimensional ferroelectric synapse transistor and a preparation method thereof. BACKGROUND

[0002] Two-dimensional semiconductor materials have gradually been explored by researchers for their application in integrated circuits due to their high mobility, tunable band structure, excellent optoelectronic properties, and size miniaturization. In particular, the excellent flexibility of two-dimensional semiconductor materials will provide more possibilities for their application in wearable scenarios.

[0003] Two-dimensional ferroelectric transistors have shown obvious advantages in neuromorphic computing, including device energy consumption, fast response, excellent on-off ratio, high durability, and high retention characteristics. In particular, its device structure is similar to traditional MOSFET, which can perfectly match traditional CMOS technology and has great industrial application value.

[0004] Compared with traditional inorganic ferroelectric materials such as hafnium oxide, organic polymer ferroelectric layers such as P(VDF-TrFE) have obvious advantages in flexibility, cost control, and process simplicity. Developing neuromorphic devices based on organic polymer ferroelectric layers is a crucial step for flexible two-dimensional ferroelectric transistors.

[0005] Although two-dimensional materials and organic polymer ferroelectric layers both have good bending resistance, traditional metal gates usually face problems such as cracking and leakage during bending, which limits the application of flexible ferroelectric transistors. Therefore, developing organic conductive polymer gate electrodes and designing two-dimensional ferroelectric synapse transistors based on organic gates have great development space and become an important part of the next generation of low-cost, high-durability, and portable wearable electronics. SUMMARY

[0006] The present application discloses a flexible two-dimensional ferroelectric synapse transistor, comprising: a flexible substrate; a gate electrode which is an organic conductive polymer thin film formed on the flexible substrate; a gate dielectric layer which is an organic ferroelectric polymer thin film formed on the gate electrode; a channel which is a two-dimensional semiconductor thin film formed on the gate dielectric layer; and a source electrode and a drain electrode which are organic conductive polymer thin films formed on both sides of the channel, realizing neural synapse characteristic simulation and obtaining stable neural synapse short-term plasticity in different bending states, for highly bending-resistant wearable neuromorphic computing electronic devices.

[0007] In the flexible two-dimensional ferroelectric synapse transistor of the present application, the organic conductive polymer thin film is preferably PEDOT:PSS, polyethylene, polypyrrole, polyphenylacetylene, or polyaniline.

[0008] In the flexible two-dimensional ferroelectric neural synapse transistor, preferably, the organic ferroelectric polymer thin film is P(VDF-TrFE).

[0009] In the flexible two-dimensional ferroelectric neural synapse transistor, preferably, the two-dimensional semiconductor thin film is MoS2, ReS2, WS2, MoSe2, WSe2.

[0010] In the flexible two-dimensional ferroelectric neural synapse transistor, preferably, the length of the channel is 5-50 mu m, and the width is 2-10 mu m.

[0011] The application further discloses a preparation method of the flexible two-dimensional ferroelectric neural synapse transistor, comprising the following steps: forming an organic conductive polymer thin film on the flexible substrate as a gate electrode; forming an organic ferroelectric polymer thin film on the gate electrode as a gate dielectric layer; forming a two-dimensional semiconductor thin film on the gate dielectric layer as a channel; and forming organic conductive polymer thin films on both sides of the channel as a source electrode and a drain electrode, so that the neural synapse characteristic simulation is realized under different bending states, the stable neural synapse short-term plasticity is obtained, and the wearable neural morphological computing electronic equipment with high bending resistance is obtained.

[0012] In the preparation method of the flexible two-dimensional ferroelectric neural synapse transistor, preferably, the organic conductive polymer thin film is PEDOT:PSS, polyethylene, polypyrrole, polyphenylacetylene or polyaniline.

[0013] In the preparation method of the flexible two-dimensional ferroelectric neural synapse transistor, preferably, the organic ferroelectric polymer thin film is P(VDF-TrFE).

[0014] In the preparation method of the flexible two-dimensional ferroelectric neural synapse transistor, preferably, the two-dimensional semiconductor thin film is MoS2, ReS2, WS2, MoSe2 or WSe2.

[0015] In the preparation method of the flexible two-dimensional ferroelectric neural synapse transistor, preferably, the organic conductive polymer thin film is formed by a spin coating method.

[0016] Beneficial effects:

[0017] (1) By virtue of the similar advantages of the two-dimensional ferroelectric transistor and the traditional MOSFET structure, the high cost problem caused by the introduced structure can be greatly reduced. And by virtue of the excellent micro-scaling property of the two-dimensional material, the size of the device can be reduced to the maximum extent, and the development of high-density integrated circuits is suitable.

[0018] (2) The organic polymer ferroelectric layer is used to replace the traditional hafnium-based ferroelectric material, which can not only avoid the problem of high temperature in the preparation process and the incompatibility with flexible substrates, but also has the characteristics of low cost, high flexibility and simple process, and is suitable for the preparation of flexible electronic devices.

[0019] (3) The organic polymer conductive material is used as the gate material to replace the traditional noble metal such as Au and Pt, which can avoid the problems of film cracking and performance degradation of flexible devices in the bending process, and provides an important help for wearable flexible neural computing devices. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a flow chart of a preparation method of a flexible two-dimensional ferroelectric neural synapse transistor.

[0021] Figures 2 to 5 is a structural schematic diagram of each stage of the preparation method of the flexible two-dimensional ferroelectric neural synapse transistor.

[0022] Figure 6 is a schematic diagram of the flexible two-dimensional ferroelectric neural synapse transistor in different bending states to realize the simulation of neural synapse characteristics. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application. The described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0024] In the description of the present application, it should be noted that the terms "upper", "lower", "vertical", "horizontal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used for the purpose of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0025] Furthermore, numerous specific details are set forth in the following description of the application, such as structural details, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the application. As will be understood by those skilled in the art, the application can be practiced without specific details. In other instances, well-known materials, structures and techniques have not been described in detail in order to avoid obscuring the application. Unless otherwise noted, the various components of the devices can be constructed of materials known to those skilled in the art, or of materials developed in the future that perform similar functions.

[0026] Figure 1 is a flow chart of a method for preparing a flexible two-dimensional ferroelectric neuromorphic transistor. As shown in Figure 1 , the flexible two-dimensional ferroelectric neuromorphic transistor comprises the following steps:

[0027] In step S1, a flexible PET substrate 100 is prepared for preparing a flexible two-dimensional ferroelectric neuromorphic transistor. The flexible substrate can also be PEN, PI, PDMS, etc.

[0028] In step S2, an organic conductive polymer PEDOT:PSS film is formed on the substrate 100 by spin coating. Specifically, spin coating is performed in a glove box using a spin coater at a speed of 2000 rpm to 5000 rpm for 20 s to 120 s, and then annealing is performed at 50°C to 150°C for 10 minutes to 30 minutes using a hot plate to obtain a PEDOT:PSS film as a gate electrode 101, as shown in Figure 2 The organic conductive polymer material can also be polyethylene, polypyrrole, polyphenylacetylene, polyaniline, etc.

[0029] In step S3, an organic ferroelectric polymer P(VDF-TrFE) film is formed on the gate electrode 101 as a gate dielectric layer 102 by spin coating, as shown in Figure 3 Specifically, P(VDF-TrFE) solution is spin coated in a glove box using a spin coater at a speed of 2000 rpm to 5000 rpm for 20 s to 120 s, and then annealing is performed at 100°C to 150°C for 100 minutes to 300 minutes using a hot plate to obtain a P(VDF-TrFE) film.

[0030] In step S4, a two-dimensional semiconductor film MoS2 of 1 nm to 10 nm thick is prepared as a channel 103 by mechanical exfoliation, as shown in Figure 4 The two-dimensional semiconductor material can also be ReS2, WS2, MoSe2, WSe2, etc.; the channel length is preferably 5 μm to 50 μm; and the channel width is preferably 2 μm to 10 μm.

[0031] In step S5, source and drain electrodes are formed on both sides of the channel. Specifically, the source and drain regions are first defined using photolithography, so that PMMA organic photoresist acts as a barrier layer to cover the area outside the two ends of the channel, facilitating the subsequent fabrication of the source and drain electrodes.

[0032] Then, the organic conductive polymer PEDOT:PSS is spread evenly on the substrate using spin coating. The preferred spin speed is 1000 rpm to 3000 rpm, and the spin coating time is 20 s to 120 s. Subsequently, the substrate is annealed on a hot plate at 40°C to 100°C for 3 to 5 minutes to obtain the PEDOT:PSS film. The organic conductive polymer film can also be polyethylene, polypyrrole, polyphenylene acetylene, polyaniline, etc.

[0033] Next, acetone is used to remove PMMA and excess PEDOT:PSS film, forming source 104 and drain 105 on both sides of the channel, as follows: Figure 5 As shown.

[0034] The flexible two-dimensional ferroelectric neural synapse transistor of the present invention, such as Figure 5 As shown, the system includes a flexible substrate 100; a gate electrode 101, which is an organic conductive polymer thin film formed on the flexible substrate 100; a gate dielectric layer 102, which is an organic ferroelectric polymer thin film formed on the gate electrode 101; a channel 103, which is a two-dimensional semiconductor thin film formed on the gate dielectric layer 102; and a source electrode 104 and a drain electrode 105, which are organic conductive polymer thin films formed on both sides of the channel 103. Figure 6 As shown, pulsed voltages can be applied to the gate 101 under different bending states. By recording the source-drain currents, the characteristics of neural synapses can be simulated, and stable short-term synaptic plasticity, such as paired pulse dissociation and excitatory postsynaptic currents, can be obtained. This technology can be used in highly bend-resistant wearable neuromorphic computing electronic devices.

[0035] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a flexible two-dimensional ferroelectric neural synaptic transistor, characterized in that, include: An organic conductive polymer film was formed on a flexible substrate by spin coating and annealed at 50℃~150℃ for 10 minutes~30 minutes to serve as a gate. An organic ferroelectric polymer film is formed on the gate using spin coating and annealed at 100°C to 150°C for 100 to 300 minutes to serve as the gate dielectric layer. A two-dimensional semiconductor thin film is formed on the gate dielectric layer to serve as a channel; An organic conductive polymer film is formed on both sides of the channel and annealed at 40°C to 100°C for 3 to 5 minutes to serve as the source and drain electrodes. By simulating neural synaptic characteristics under different bending states, stable short-term synaptic plasticity is obtained, which can be used for highly bend-resistant wearable neuromorphic computing electronic devices.

2. The method for fabricating a flexible two-dimensional ferroelectric neural synaptic transistor according to claim 1, characterized in that, The organic conductive polymer film is PEDOT:PSS, polyethylene, polypyrrole, polyphenylene acetylene, or polyaniline.

3. The method for fabricating a flexible two-dimensional ferroelectric neural synaptic transistor according to claim 1, characterized in that, The organic ferroelectric polymer film is P(VDF-TrFE).

4. The method for fabricating a flexible two-dimensional ferroelectric neural synaptic transistor according to claim 1, characterized in that, The two-dimensional semiconductor thin film is MoS2, ReS2, WS2, MoSe2, or WSe2.

5. A flexible two-dimensional ferroelectric synaptic transistor, fabricated by the method for fabricating a flexible two-dimensional ferroelectric synaptic transistor according to any one of claims 1 to 4, characterized in that, include: Flexible substrate; The gate, which is an organic conductive polymer thin film, is formed on the flexible substrate; A gate dielectric layer, which is an organic ferroelectric polymer film, is formed on the gate. The channel, which is a two-dimensional semiconductor thin film, is formed on the gate dielectric layer; The source and drain electrodes, which are thin films of organic conductive polymer, are formed on both sides of the channel. By simulating neural synaptic characteristics under different bending states, stable short-term synaptic plasticity is obtained, which can be used for highly bend-resistant wearable neuromorphic computing electronic devices.

6. The flexible two-dimensional ferroelectric neural synaptic transistor according to claim 5, characterized in that, The organic conductive polymer film is PEDOT:PSS, polyethylene, polypyrrole, polyphenylene acetylene, or polyaniline.

7. The flexible two-dimensional ferroelectric neural synaptic transistor according to claim 5, characterized in that, The organic ferroelectric polymer film is P(VDF-TrFE).

8. The flexible two-dimensional ferroelectric neural synaptic transistor according to claim 5, characterized in that, The two-dimensional semiconductor thin film is MoS2, ReS2, WS2, MoSe2, or WSe2.

9. The flexible two-dimensional ferroelectric neural synaptic transistor according to claim 5, characterized in that, The length of the channel is 5μm to 50μm and the width is 2μm to 10μm.

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