Semiconductor device and semiconductor circuit

Abstract

Provided are a semiconductor device and a semiconductor circuit that have a reduced recovery loss and an expanded safe operating area. The semiconductor device includes a semiconductor layer including a first trench, a second trench, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type that is in contact with the second trench and is between the first trench and the second trench, a third semiconductor region of the first conductivity type that is provided between the first trench and the second semiconductor region, a fourth semiconductor region of the second conductivity type that is between the first trench and a first surface and has a higher impurity concentration than the second semiconductor region, and a fifth semiconductor region of the second conductivity type that is provided between the second semiconductor region and the first surface, is separate from the fourth semiconductor region, is in contact with the second trench, and has a higher impurity concentration than the second semiconductor region; a first electrode on a first surface side of the semiconductor layer; and a second electrode on a second surface side of the semiconductor layer.

Description

[0001] [Related Applications]

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-40092 (filed on March 12, 2021). This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and semiconductor circuits. Background Technology

[0004] An example of a semiconductor device used in power applications is the Insulated Gate Bipolar Transistor (IGBT). An IGBT, for example, has a p-type collector region, an n-type drift region, and a p-type base region on its collector electrode. Furthermore, a gate electrode is provided in a trench that extends through the p-type base region and reaches the n-type drift region, separated by a gate insulating film. Finally, an n-type emitter region, connected to the emitter electrode, is provided on the surface of the p-type base region adjacent to the trench.

[0005] In recent years, reverse-conducting IGBTs (RC-IGBTs), which integrate IGBTs and freewheeling diodes onto the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The freewheeling diode allows current to flow in the opposite direction to the IGBT's conduction current. The freewheeling diode is, for example, formed from a pin (p-intrinsic-n) diode with a pn junction.

[0006] A pin diode incurs recovery losses during the reverse recovery operation (reverse recovery action), which involves switching from forward bias to reverse bias. In other words, the reverse recovery action is the switching action when the pin diode is turned off. During the reverse recovery action, carriers injected into the drift region are discharged, thus creating a recovery current flowing in the reverse direction. This current results in recovery losses. To reduce recovery losses, various structures have been proposed to reduce the number of carriers injected into the drift region.

[0007] Furthermore, during the reverse recovery operation of a pin diode, electric field concentration can sometimes occur at specific locations in the PN junction, leading to avalanche breakdown. If avalanche breakdown occurs and the current increases, the pin diode may be damaged. By suppressing pin diode damage during reverse recovery, the Reverse Recovery Safe Operating Area (RROS) can be expanded. The ROS Safe Operating Area is the usable current-voltage range during reverse recovery. Summary of the Invention

[0008] Embodiments of the present invention provide a semiconductor device and semiconductor circuit that reduce recovery loss and expand the safe operating area.

[0009] A semiconductor device according to an embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface; the semiconductor layer including: a first trench disposed on the first surface side; a second trench disposed on the first surface side; a first semiconductor region of a first conductivity type contacting the first trench and the second trench; a second semiconductor region of a second conductivity type disposed between the first surface and the first semiconductor region, and between the first trench and the second trench, and contacting the second trench; a third semiconductor region of a first conductivity type disposed between the first semiconductor region and the first surface, and between the first trench and the second semiconductor region, contacting the first trench and the second semiconductor region; and a fourth semiconductor region of a second conductivity type disposed between the third semiconductor region and the first surface. A first semiconductor region is disposed between the first trench and the second semiconductor region, in contact with the first trench and the second semiconductor region, and has a second conductivity type impurity concentration higher than that of the second semiconductor region; a second conductivity type fifth semiconductor region is disposed between the second semiconductor region and the first surface, and is disposed between the fifth semiconductor region and the fourth semiconductor region, in contact with the second trench, and has a second conductivity type impurity concentration higher than that of the second semiconductor region; a first electrode is disposed on the first surface side of the semiconductor layer, in contact with the second semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; and a second electrode is disposed on the second surface side of the semiconductor layer. Attached Figure Description

[0010] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0011] Figure 2 This is a schematic top view of the semiconductor device according to the first embodiment.

[0012] Figure 3 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0013] Figure 4 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0014] Figure 5 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0015] Figure 6 This is a schematic top view of a modified example of the semiconductor device according to the first embodiment.

[0016] Figure 7 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0017] Figure 8 This is a schematic diagram of the semiconductor circuit according to the third embodiment.

[0018] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0019] Figure 10 This is an explanatory diagram illustrating the function and effect of the semiconductor device and semiconductor circuit according to the third embodiment.

[0020] Figure 11 This is an explanatory diagram illustrating the function and effect of the semiconductor device and semiconductor circuit according to the third embodiment.

[0021] Figure 12 This is an explanatory diagram illustrating the function and effect of the semiconductor device and semiconductor circuit according to the third embodiment.

[0022] Figure 13 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0023] Figure 14 This is a schematic cross-sectional view of a first variation of the semiconductor device according to the fourth embodiment.

[0024] Figure 15 This is a schematic cross-sectional view of a second variation of the semiconductor device according to the fourth embodiment.

[0025] Figure 16 This is a schematic cross-sectional view of the semiconductor device circuit according to the fifth embodiment. Detailed Implementation

[0026] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar parts will be labeled with the same reference numerals, and descriptions of parts that have already been described once will be appropriately omitted.

[0027] In this specification, when there is n + Type, n-type, n - In the case of type marking, it means that the concentration of n-type impurities is in the order of n. + Type, n-type, n - The order of the type decreases. Additionally, when there is p... + Type, p type, p - In the case of p-type labeling, it means that the concentration of p-type impurities is p... + Type, p type, p - The order of the types decreases.

[0028] In this specification, the distribution and absolute value of impurity concentration in the semiconductor region can be determined, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitude of impurity concentration in the two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM). Additionally, the distribution and absolute value of impurity concentration can be determined, for example, using spreading resistance analysis (SRA). The relative magnitude and absolute value of carrier concentration in the semiconductor regions are determined using SCM and SRA. By assuming the activation rate of the impurities, the relative magnitude, distribution, and absolute value of impurity concentration in the two semiconductor regions can be determined based on the results of SCM and SRA measurements.

[0029] Furthermore, in this specification, the "p-type impurity concentration" of a p-type semiconductor region refers to the net (net) p-type impurity concentration obtained by subtracting the n-type impurity concentration of the region from the p-type impurity concentration of the region. Similarly, the "n-type impurity concentration" of an n-type semiconductor region refers to the net (net) n-type impurity concentration obtained by subtracting the p-type impurity concentration of the region from the n-type impurity concentration of the region.

[0030] In addition, the instruction manual states that, unless otherwise specified, the impurity concentration of a specific area refers to the maximum impurity concentration in that area.

[0031] (First Implementation)

[0032] The semiconductor device according to the first embodiment includes: a semiconductor layer having a first surface and a second surface facing the first surface; the semiconductor layer including: a first trench disposed on the first surface side; a second trench disposed on the first surface side; a first semiconductor region of a first conductivity type contacting the first trench and the second trench; a second semiconductor region of a second conductivity type disposed between the first surface and the first semiconductor region, and between the first trench and the second trench, and contacting the second trench; a third semiconductor region of a first conductivity type disposed between the first semiconductor region and the first surface, and between the first trench and the second semiconductor region, contacting the first trench and the second semiconductor region; and a fourth semiconductor region of a second conductivity type disposed on the third semiconductor region. A first semiconductor region is disposed between the first surface and the first trench, and in contact with the first trench and the second semiconductor region, having a second conductivity type impurity concentration higher than that of the second semiconductor region; a second conductivity type fifth semiconductor region is disposed between the second semiconductor region and the first surface, and a second semiconductor region is disposed between the fifth semiconductor region and the fourth semiconductor region, in contact with the second trench, having a second conductivity type impurity concentration higher than that of the second semiconductor region; a first electrode is disposed on the first surface side of the semiconductor layer, in contact with the second semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; and a second electrode is disposed on the second surface side of the semiconductor layer.

[0033] The semiconductor device in the first embodiment is a pin diode 100. The pin diode 100 is, for example, a fast recovery diode (FRD). The pin diode 100 is used, for example, as a freewheeling diode in an inverter circuit or the like. Alternatively, the pin diode 100 is used, for example, as a diode in an RC-IGBT.

[0034] The following explanation will be based on the case where the first conductivity type is n-type and the second conductivity type is p-type.

[0035] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 This is a schematic top view of the semiconductor device according to the first embodiment. Figure 1 yes Figure 2 AA' section. Figure 2 This is the top view of the first side, P1.

[0036] The pin diode 100 of the first embodiment includes a semiconductor layer 10, an anode electrode 12 (first electrode), a cathode electrode 14 (second electrode), and a trench insulating layer 15.

[0037] The semiconductor layer 10 includes trenches 20a (first trench), 20b (second trench), 20c, 20d, 20e, a cathode region 22, a drift region 24 (first semiconductor region), a substrate region 26 (second semiconductor region), a channel region 28 (third semiconductor region), a first anode region 30a (fourth semiconductor region), and a second anode region 30b (fifth semiconductor region).

[0038] Anode electrode 12 is an example of a first electrode. Cathode electrode 14 is an example of a second electrode. Trench 20a is an example of a first trench. Trench 20b is an example of a second trench. Drift region 24 is an example of a first semiconductor region. Substrate region 26 is an example of a second semiconductor region. Channel region 28 is an example of a third semiconductor region. First anode region 30a is an example of a fourth semiconductor region. Second anode region 30b is an example of a fifth semiconductor region.

[0039] Hereinafter, grooves 20a, 20b, 20c, 20d, and 20e will sometimes be collectively referred to as groove 20.

[0040] The semiconductor layer 10 has a first surface P1 and a second surface P2 opposite to the first surface P1. The semiconductor layer 10 is, for example, monocrystalline silicon. The film thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0041] In this specification, a direction parallel to the first surface P1 is referred to as the first direction. Furthermore, a direction parallel to the first surface P1 and orthogonal to the first direction is referred to as the second direction. Additionally, in this specification, "depth" is defined as the distance from the first surface P1 towards the second surface P2.

[0042] Trench 20 is disposed on the first surface P1 side of semiconductor layer 10. Trench 20 extends along a first direction on the first surface P1. Trench 20 is repeatedly disposed in a second direction.

[0043] The plurality of trenches 20 include trench 20a, trench 20b, trench 20c, trench 20d and trench 20e.

[0044] Trench 20 is a trench disposed in semiconductor layer 10. Trench 20 is part of semiconductor layer 10. Trench 20 extends through substrate region 26 and reaches drift region 24.

[0045] The depth of trench 20 is greater than the depth of substrate region 26. The depth of trench 20 is, for example, more than 2 μm and less than 10 μm.

[0046] The width of the groove 20 in the second direction is, for example, more than 0.5 μm and less than 2 μm.

[0047] The distance between adjacent trenches 20 is, for example, greater than the depth of trench 20. For example, the distance between adjacent trenches 20a and 20b is greater than the depth of trench 20a.

[0048] The distance between adjacent trenches 20 is, for example, more than 5 μm and less than 30 μm. The distance between adjacent trenches 20 is, for example, greater than 10 μm.

[0049] A trench insulating layer 15 is disposed within the trench 20. The trench insulating layer 15 is, for example, silicon oxide.

[0050] Cathode region 22 is n + Type semiconductor region. Cathode region 22 is in contact with the second surface P2.

[0051] Drift region 24 is n - A type of semiconductor region. A drift region 24 is disposed between the cathode region 22 and the first surface P1. The drift region 24 is in contact with the bottom of the trench 20.

[0052] The n-type impurity concentration in drift region 24 is lower than that in cathode region 22. The n-type impurity concentration in drift region 24 is, for example, 1 × 10⁻⁶. 12 atoms / cm 3 Above and 1×10 15 atoms / cm 3 the following.

[0053] The substrate region 26 is a p-type semiconductor region. The substrate region 26 is disposed between the drift region 24 and the first surface P1. The substrate region 26 is, for example, in contact with the drift region 24. The substrate region 26 extends along a first direction on the first surface P1.

[0054] The base region 26 is disposed between two adjacent trenches 20. For example, the base region 26 is disposed between trenches 20a and 20b. For example, the base region 26 is disposed between trenches 20a and 20c.

[0055] The base region 26 is in contact with at least a portion of the sidewalls of the trench 20. For example, the base region 26 is in contact with the sidewalls of the trench 20b. For example, the base region 26 is in contact with the sidewalls of the trench 20c.

[0056] The base region 26 is separated from at least a portion of the trench 20. For example, the base region 26 is separated from the trench 20a.

[0057] The concentration of p-type impurities in substrate region 26 is, for example, 1 × 10⁻⁶. 16 atoms / cm 3 Above and 5×10 17 atoms / cm 3 the following.

[0058] The depth of the substrate region 26 is shallower than the depth of the trench 20. The depth of the substrate region 26 is, for example, more than half the depth of the trench. The depth of the substrate region 26 is, for example, more than 2 μm and less than 8 μm.

[0059] Channel region 28 is n - A semiconductor region of the type. The channel region 28 is disposed between the drift region 24 and the first surface P1.

[0060] The channel region 28 is disposed between a portion of the trench 20 and the base region 26. For example, the channel region 28 is disposed between trench 20a and the base region 26. For example, the channel region 28 is disposed between trench 20d and the base region 26. For example, the channel region 28 is disposed between trench 20e and the base region 26.

[0061] The channel region 28 contacts a portion of the sidewall of the groove 20. For example, the channel region 28 contacts the sidewall of groove 20a. For example, the channel region 28 contacts the sidewall of groove 20d. For example, the channel region 28 contacts the sidewall of groove 20e.

[0062] The channel region 28 is in contact with the base region 26.

[0063] The concentration of n-type impurities in channel region 28 is, for example, higher than that in drift region 24. The concentration of n-type impurities in channel region 28 is, for example, 1 × 10⁻⁶. 12 atoms / cm 3 Above and 1×10 16 atoms / cm 3 the following.

[0064] The first anode region 30a is a p-type semiconductor region. The first anode region 30a is disposed between the channel region 28 and the first surface P1. The first anode region 30a extends along a first direction on the first surface P1.

[0065] The first anode region 30a contacts a portion of the side surface of the trench 20. For example, the first anode region 30a contacts the side surface of the trench 20a. For example, the first anode region 30a contacts the side surface of the trench 20d. For example, the first anode region 30a contacts the side surface of the trench 20e.

[0066] The first anode region 30a is in contact with the substrate region 26.

[0067] The p-type impurity concentration in the first anode region 30a is higher than that in the substrate region 26. For example, the p-type impurity concentration in the first anode region 30a is 1 × 10⁻⁶. 17 atoms / cm 3 Above and 1×10 21atoms / cm 3 the following.

[0068] The depth of the first anode region 30a is shallower than the depth of the substrate region 26. The depth of the first anode region 30a is, for example, more than 0.1 μm and less than 2 μm.

[0069] The width of the first anode region 30a in the second direction is greater than the width of the channel region 28 in the second direction.

[0070] The second anode region 30b is a p-type semiconductor region. The second anode region 30b is disposed between the substrate region 26 and the first surface P1. The second anode region 30b extends along a first direction on the first surface P1.

[0071] A substrate region 26 is provided between the second anode region 30b and the first anode region 30a. The second anode region 30b is in contact with the substrate region 26.

[0072] The second anode region 30b contacts a portion of the side of the trench 20. For example, the second anode region 30b contacts the side of the trench 20b. For example, the second anode region 30b contacts the side of the trench 20c.

[0073] The p-type impurity concentration in the second anode region 30b is higher than that in the substrate region 26. For example, the p-type impurity concentration in the second anode region 30b is 1 × 10⁻⁶. 17 atoms / cm 3 Above and 1×10 21 atoms / cm 3 the following.

[0074] The depth of the second anode region 30b is shallower than the depth of the substrate region 26. The depth of the second anode region 30b is, for example, more than 0.1 μm and less than 2 μm.

[0075] There is no channel region 28 between the second anode region 30b and the drift region 24. There is no n-type semiconductor region between the second anode region 30b and the drift region 24.

[0076] The anode electrode 12 is disposed on the first surface P1 side of the semiconductor layer 10. The anode electrode 12 is in contact with the first surface P1 of the semiconductor layer 10.

[0077] The anode electrode 12 includes a first portion 12a and a second portion 12b. The anode electrode 12, for example, contacts the substrate region 26 in the first portion 12a. The anode electrode 12, for example, contacts the first anode region 30a and the second anode region 30b in the second portion 12b.

[0078] The anode electrode 12 is in Schottky contact with the substrate region 26, for example, in the first portion 12a. The anode electrode 12 is in ohmic contact with the first anode region 30a and the second anode region 30b, for example, in the second portion 12b.

[0079] The anode electrode 12 is, for example, a metal. For example, the material of the first part 12a may also be different from the material of the second part 12b.

[0080] A cathode electrode 14 is disposed on the second surface P2 side of the semiconductor layer 10. The cathode electrode 14 is in contact with the second surface P2 of the semiconductor layer 10. The cathode electrode 14 is in contact with the cathode region 22. The cathode electrode 14 and the cathode region 22 are in ohmic contact.

[0081] The cathode electrode 14 is, for example, a metal.

[0082] Next, the function and effect of the pin diode 100 in the first embodiment will be explained.

[0083] Figure 3 as well as Figure 4 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 3 This indicates the flow of electrons (electron current) when the pin diode 100 is in the ON state. Figure 4 This indicates the flow of holes (hole current) when the pin diode 100 is in the ON state.

[0084] When the diode 100 is turned on, a forward bias voltage is applied between the anode electrode 12 and the cathode electrode 14. That is, a voltage is applied between the anode electrode 12 and the cathode electrode 14 such that the potential of the anode electrode 12 is higher than the potential of the cathode electrode 14. In other words, a voltage is applied between the anode electrode 12 side, which is positive. The anode electrode 12 becomes the positive terminal, and the cathode electrode 14 becomes the negative terminal.

[0085] First, the flow of electrons when the pin diode 100 is in the ON state will be explained. The cathode electrode 14 is in 22-ohm contact with the cathode region 22. Therefore, electrons injected from the cathode electrode 14 ( Figure 3 The “e” in n) comes from n + The cathode region 22 of type n - The drift region 24 of the p-type reaches directly below the base region 26 of the p-type.

[0086] The pin diode 100 has an n on a portion of the side of the trench 20. - The channel region 28 is of the p-type shape. Therefore, electrons that have reached directly below the base region 26 bypass the energy barrier between the drift region 24 and the base region 26 and flow towards the lower potential channel region 28. Electrons flow to p +Up to directly below the first anode region 30a of the type.

[0087] Electrons that have reached directly below the first anode region 30a bypass the energy barrier between the first anode region 30a and the channel region 28 and flow towards the substrate region 26, which has a lower potential. The electron flow continues until it reaches directly below the anode electrode 12.

[0088] The substrate region 26 is in Schottky contact with the anode electrode 12. That is, the contact between the substrate region 26 and the anode electrode 12 constitutes a Schottky contact between a p-type semiconductor and a metal. Therefore, the contact between the substrate region 26 and the anode electrode 12 acts as an energy barrier for holes, but not for electrons. Consequently, electrons flow from the substrate region 26 to the anode electrode 12.

[0089] As described above, when the pin diode 100 is in the ON state, electrons travel from the cathode electrode 14 via n + Type 22, n cathode region - Type 24, n - The electron current flows from the cathode electrode 14 to the anode electrode 12 through the p-type channel region 28 and the p-type substrate region 26.

[0090] Next, the flow of holes (hole current) when the pin diode 100 is in the ON state will be explained.

[0091] As described above, in the on-state, electrons that have reached directly below the first anode region 30a bypass the energy barrier between the first anode region 30a and the channel region 28 and flow towards the substrate region 26, which has a lower potential. Figure 4 As shown, electrons move laterally below the first anode region 30a and flow into the substrate region 26.

[0092] The lateral movement of these electrons generates a voltage drop below the first anode region 30a. This voltage drop, generated in the first anode region 30a, causes... Figure 4 As shown, the first anode region 30a and the channel region 28 directly below the first anode region 30a are in a forward bias state. Additionally, the first anode region 30a and the substrate region 26 directly below the first anode region 30a are in a forward bias state.

[0093] The first anode region 30a and the channel region 28 directly below the first anode region 30a are in a forward bias state, and holes are injected from the first anode region 30a into the channel region 28. Figure 4 The "h" in the text. Additionally, the first anode region 30a and the substrate region 26 directly below it are in a forward bias state, thereby injecting holes from the first anode region 30a into the substrate region 26. Figure 4 (the "h" in the text).

[0094] The injected holes flow to the cathode electrode 14 via the drift region 24 and the cathode region 22. The hole current flows from the anode electrode 12 to the cathode electrode 14.

[0095] The greater the width or depth of the first anode region 30a in the second direction, the greater the hole current. Furthermore, the greater the contact area between the first anode region 30a and the anode electrode 12, the greater the hole current. In other words, by adjusting the width, depth, or contact area of ​​the first anode region 30a in the second direction with the anode electrode 12, the amount of hole injected from the anode electrode 12 can be adjusted.

[0096] When the pin diode 100 is in the ON state, electrons flow to the anode electrode 12 via the channel region 28. Electrons have difficulty flowing directly from the drift region 24 directly below the substrate region 26 to the anode electrode 12 via the substrate region 26.

[0097] A portion of the electrons are injected from the drift region 24 into the substrate region 26 without passing through the channel region 28. Through this electron injection, hole injection occurs from the substrate region 26 into the drift region 24.

[0098] However, by allowing most of the electrons to flow from the drift region 24 to the anode electrode 12 via the channel region 28, hole injection into the drift region 24 is suppressed.

[0099] A pin diode incurs recovery losses during the reverse recovery operation, which involves switching from forward bias to reverse bias. During reverse recovery, charge carriers injected into the drift region are displaced, resulting in a recovery current flowing in the opposite direction. This current causes recovery losses. Recovery losses can be reduced by decreasing the number of charge carriers injected into the drift region.

[0100] According to the pin diode 100 of the first embodiment, by providing the channel region 28, the number of carriers injected into the drift region 24 can be reduced. Therefore, the pin diode 100 according to the first embodiment can reduce recovery loss.

[0101] Figure 5 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 5 This is an explanatory diagram of the reverse recovery operation of the pin diode 100.

[0102] During the reverse recovery operation of pin diode 100, that is, when pin diode 100 is turned off, pin diode 100 switches from the on state to the off state. The voltage applied between the anode electrode 12 and the cathode electrode 14 changes from forward bias to reverse bias.

[0103] When the diode 100 is turned off, the voltage change between the anode electrode 12 and the cathode electrode 14 is such that the potential of the anode electrode 12 is lower than the potential of the cathode electrode 14. That is, when turned off, a positive voltage is applied between the anode electrode 12 and the cathode electrode 14. The anode electrode 12 becomes the negative electrode, and the cathode electrode 14 becomes the positive electrode.

[0104] During the reverse recovery operation of a pin diode, electric field concentration can sometimes occur at specific locations in the PN junction, leading to avalanche breakdown. Furthermore, if avalanche breakdown occurs and the current increases, the pin diode may be damaged. By suppressing pin diode damage during reverse recovery, the safe operating region during recovery can be expanded. The safe operating region during recovery is the usable current-voltage range during reverse recovery.

[0105] In the pin diode 100, when turned off, an electric field concentration easily occurs at the bottom of the trench 20. Therefore, as Figure 5 As shown, avalanche breakdown is likely to occur at the bottom of trench 20 when the switch is turned off.

[0106] Avalanche breakdown occurring at the bottom of trench 20 generates a large number of charge carriers. The flow of these charge carriers is called avalanche current. If the avalanche current increases, the pin diode may be damaged. For example, if the avalanche current concentrates in a specific area, causing a temperature rise, the pin diode may be damaged.

[0107] In the pin diode 100, p-shaped diodes are located on both sides of the trench 20. + The first anode region 30a or p of the type + The second anode region 30b is of type 2. The cavities generated at the bottom of the trench 20 due to avalanche breakdown are discharged from the bottom of the trench 20 to the anode electrode 12 via the first anode region 30a or the second anode region 30b with the shortest distance.

[0108] In the pin diode 100, trenches 20 are formed in a certain proportion within the semiconductor layer 10. Therefore, during turn-off, the sites where avalanche breakdown would occur are dispersed. Furthermore, each trench 20 has a p-shaped path on both sides that serves as a hole discharge path. + The first anode region 30a or p of the type + The second anode region 30b of the type. Therefore, the venting path of the holes is also dispersed.

[0109] Therefore, in the pin diode 100, avalanche current concentration at specific locations is less likely to occur. Consequently, according to the pin diode 100, damage during reverse recovery is suppressed, and the safe operating area during recovery can be expanded.

[0110] From the viewpoint of reducing the recovery loss of the pin diode 100, it is considered to reduce the occupancy ratio of the channel region 28 in the semiconductor layer 10. Regardless of whether there is a channel region 28 in contact with the trench 20, the pin diode 100 has a first anode region 30a or a second anode region 30b on both sides of the trench 20. Therefore, from the viewpoint of reducing recovery loss, even if the occupancy ratio of the channel region 28 in the semiconductor layer 10 is reduced, damage during reverse recovery operation can be suppressed.

[0111] From the viewpoint of reducing the occupancy ratio of the channel region 28 in the semiconductor layer 10 and reducing the recovery loss of the pin diode 100, the distance between adjacent trenches 20 is preferably larger.

[0112] Based on the above viewpoint, the distance between adjacent trenches 20 is preferably greater than the depth of the trench 20. The distance between adjacent trenches 20 is preferably at least 1.5 times the depth of the trench 20, and more preferably at least 2 times.

[0113] Based on the above viewpoint, the distance between adjacent trenches 20 is preferably greater than 10 μm, more preferably 12 μm or more, and even more preferably 15 μm or more.

[0114] When the difference between the depth of trench 20 and the depth of substrate region 26 increases, the electric field strength at the bottom of trench 20 increases when pin diode 100 is turned off. Therefore, the breakdown voltage of pin diode 100 may decrease.

[0115] Based on the above viewpoint, the depth of the base region 26 is preferably more than one-half the depth of the trench 20, more preferably more than three-quarters, and even more preferably more than nine-tenths.

[0116] The n-type impurity concentration in the channel region 28 is preferably higher than that in the drift region 24. By making the n-type impurity concentration in the channel region 28 higher than that in the drift region 24, electrons can more easily flow from the drift region 24 to the channel region 28.

[0117] In the pin diode 100, the material of the first portion 12a of the anode electrode 12 is preferably different from the material of the second portion 12b. It is easy to make the contact between the first portion 12a and the substrate region 26 a Schottky contact, and the contact between the second portion 12b and the first anode region 30a and the second anode region 30b an ohmic contact.

[0118] Figure 6 This is a schematic top view of a modified example of the semiconductor device according to the first embodiment. The modified example of the semiconductor device according to the first embodiment is a pin diode 101.

[0119] The pin diode 101 differs from the pin diode 101 of the first embodiment in that the first anode region 30a and the second anode region 30b are divided into multiple portions and arranged in the first direction. Furthermore, although in Figure 6 Although not shown in the figure, the channel region 28 below the first anode region 30a is also divided into multiple and configured in the first direction.

[0120] Based on the first embodiment and its variations, a pin diode with reduced recovery loss and expanded safe operating area can be provided.

[0121] (Second Implementation)

[0122] The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in that it has a fifth semiconductor region sandwiched between the fifth semiconductor region and the fourth semiconductor region, and in contact with the first trench. Hereinafter, descriptions that are repeated in the first embodiment will be omitted.

[0123] The semiconductor device in the second embodiment is a pin diode 200.

[0124] Figure 7 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0125] The pin diode 200 of the second embodiment includes a semiconductor layer 10, an anode electrode 12 (first electrode), a cathode electrode 14 (second electrode), and a trench insulating layer 15.

[0126] The semiconductor layer 10 includes trenches 20a (first trench), 20b (second trench), 20c, 20d, 20e, a cathode region 22, a drift region 24 (first semiconductor region), a substrate region 26 (second semiconductor region), a channel region 28 (third semiconductor region), a first anode region 30a (fourth semiconductor region), and a second anode region 30b (fifth semiconductor region).

[0127] Anode electrode 12 is an example of a first electrode. Cathode electrode 14 is an example of a second electrode. Trench 20a is an example of a first trench. Trench 20b is an example of a second trench. Drift region 24 is an example of a first semiconductor region. Substrate region 26 is an example of a second semiconductor region. Channel region 28 is an example of a third semiconductor region. First anode region 30a is an example of a fourth semiconductor region. Second anode region 30b is an example of a fifth semiconductor region.

[0128] Hereinafter, grooves 20a, 20b, 20c, 20d, and 20e will sometimes be collectively referred to as groove 20.

[0129] In the pin diode 200, a first anode region 30a and a second anode region 30b are formed by sandwiching a trench 20 in the middle. In other words, a trench 20 is formed between the first anode region 30a and the second anode region 30b. The first anode region 30a is in contact with one side of the same trench 20, and the second anode region 30b is in contact with the other side.

[0130] For example, a first anode region 30a and a second anode region 30b are provided by sandwiching a trench 20a in the middle. For example, a trench 20a is provided between the first anode region 30a and the second anode region 30b. For example, the first anode region 30a is in contact with one side of the trench 20a, and the second anode region 30b is in contact with the other side.

[0131] According to the second embodiment of the pin diode 200, compared with the first embodiment of the pin diode 100, the distribution deviation of the channel region 28 within the semiconductor layer 10 is smaller. Therefore, hole injection into the drift region 24 becomes more uniform. Consequently, the current flow in the pin diode 200 becomes more uniform.

[0132] According to the second embodiment, a pin diode with reduced recovery loss and expanded safe operating area can be provided.

[0133] (Third Implementation)

[0134] The semiconductor device of the third embodiment differs from that of the semiconductor device of the first embodiment in that it further includes a third electrode, which is disposed in the first trench and the second trench and electrically separated from the first electrode and the second electrode. Hereinafter, descriptions that are repeated in the first embodiment will be omitted.

[0135] The semiconductor circuit of the third embodiment includes: the semiconductor device described above; and a control circuit that drives the semiconductor device to apply a negative voltage relative to the first electrode when the first conductivity type is n-type and a positive voltage is applied between the first electrode and the second electrode at the second electrode side, and to apply a positive voltage relative to the first electrode at the third electrode when the first conductivity type is p-type and a negative voltage is applied between the first electrode and the second electrode at the second electrode side.

[0136] The semiconductor device in the third embodiment is a pin diode 300.

[0137] The control circuit in the third embodiment is a gate drive circuit 350. The semiconductor circuit in the third embodiment consists of a semiconductor device and a control circuit that controls the semiconductor device.

[0138] The following explanation will be based on the case where the first conductivity type is n-type and the second conductivity type is p-type.

[0139] Figure 8 This is a schematic diagram of a semiconductor circuit according to a third embodiment. The semiconductor circuit of the third embodiment includes a pin diode 300 and a gate drive circuit 350. The gate drive circuit 350 controls the pin diode 300.

[0140] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0141] The pin diode 300 of the third embodiment includes a semiconductor layer 10, an anode electrode 12 (first electrode), a cathode electrode 14 (second electrode), a trench gate insulating film 16, a trench gate electrode 18 (third electrode), an interlayer insulating layer 19, and an electrode pad 310.

[0142] The semiconductor layer 10 includes trenches 20a (first trench), 20b (second trench), 20c, 20d, 20e, a cathode region 22, a drift region 24 (first semiconductor region), a substrate region 26 (second semiconductor region), a channel region 28 (third semiconductor region), a first anode region 30a (fourth semiconductor region), and a second anode region 30b (fifth semiconductor region).

[0143] Anode electrode 12 is an example of a first electrode. Cathode electrode 14 is an example of a second electrode. Trench gate electrode 18 is an example of a third electrode. Trench 20a is an example of a first trench. Trench 20b is an example of a second trench. Drift region 24 is an example of a first semiconductor region. Substrate region 26 is an example of a second semiconductor region. Channel region 28 is an example of a third semiconductor region. First anode region 30a is an example of a fourth semiconductor region. Second anode region 30b is an example of a fifth semiconductor region.

[0144] Hereinafter, grooves 20a, 20b, 20c, 20d, and 20e will sometimes be collectively referred to as groove 20.

[0145] A trench gate electrode 18 is disposed in a trench 20. For example, the trench gate electrode 18 is disposed in trench 20a. For example, the trench gate electrode 18 is disposed in trench 20b. For example, the trench gate electrode 18 is disposed in trench 20c.

[0146] The trench gate electrode 18 is, for example, a semiconductor or a metal. The trench gate electrode 18 is, for example, amorphous silicon or polycrystalline silicon containing n-type or p-type impurities.

[0147] The trench gate electrode 18 is electrically isolated from the anode electrode 12 and the cathode electrode 14. The trench gate electrode 18 is electrically connected to the electrode pad 310.

[0148] A trench gate insulating film 16 is disposed between the trench gate electrode 18 and the semiconductor layer 10. The trench gate insulating film 16 is, for example, silicon oxide.

[0149] An interlayer insulating layer 19 is disposed between the trench gate electrode 18 and the anode electrode 12. The interlayer insulating layer 19 electrically separates the trench gate electrode 18 and the anode electrode 12. The interlayer insulating layer 19 is, for example, silicon oxide.

[0150] Electrode pads 310 are disposed on the first surface P1 side of semiconductor layer 10. Electrode pads 310 are electrically connected to trench gate electrode 18. Electrode pads 310 and trench gate electrode 18 are connected, for example, through metal wiring (not shown).

[0151] Next, the function and effects of the semiconductor device and semiconductor circuit of the third embodiment will be explained. Figure 10 , Figure 11 and Figure 12 This is an explanatory diagram illustrating the function and effect of the semiconductor device and semiconductor circuit according to the third embodiment. Figure 10 This is a schematic diagram showing the voltage applied to a pin diode. Figure 11 This is an example of a timing diagram for the voltage applied to a pin diode. Figure 12 This is an illustration of the reverse recovery operation of the PIN diode 300.

[0152] like Figure 10 As shown, a first voltage (V1) is applied to the anode electrode 12 of the pin diode 300, a second voltage (V2) is applied to the cathode electrode 14, and a third voltage (V3) is applied to the trench gate electrode 18. The third voltage (V3) applied to the trench gate electrode 18 is controlled, for example, by the gate drive circuit 350.

[0153] like Figure 11 As shown, when the pin diode 300 is in the ON state, a voltage is applied between the anode electrode 12 and the cathode electrode 14 such that the potential of the anode electrode 12 is higher than the potential of the cathode electrode 14. In other words, in the ON state, a positive voltage is applied to the anode electrode 12 side between the anode electrode 12 and the cathode electrode 14. That is, in the ON state, the first voltage V1 applied to the anode electrode 12 is higher than the second voltage V2 applied to the cathode electrode 14.

[0154] exist Figure 11In the case of the pin diode 300 being turned on, for example, the first voltage V1 is 0V and the second voltage V2 is a negative voltage. Furthermore, the third voltage V3 applied to the trench gate electrode 18 is, for example, equal to the first voltage V1, which is 0V.

[0155] like Figure 11 As shown, when the pin diode 300 switches from the ON state to the OFF state, the voltage between the anode electrode 12 and the cathode electrode 14 changes such that the potential of the anode electrode 12 is lower than the potential of the cathode electrode 14. That is, when the diode is off, a positive voltage is applied between the anode electrode 12 and the cathode electrode 14. Specifically, when the diode is off, the second voltage V2 applied to the cathode electrode 14 is higher than the first voltage V1 applied to the anode electrode 12.

[0156] When turned off, the third voltage V3 applied to the trench gate electrode 18 is applied as a negative voltage relative to the first voltage V1 applied to the anode electrode 12.

[0157] exist Figure 11 In the process, when the pin diode 300 is turned off and in the open state, for example, the first voltage V1 is 0V and the second voltage V2 is a positive voltage. In addition, the third voltage V3 applied to the trench gate electrode 18 is a negative voltage.

[0158] When the pin diode 300 is turned off, a negative voltage relative to the anode electrode 12 is applied to the trench gate electrode 18. Thus, as... Figure 12 As shown, a p-type accumulation layer is formed on the side of the trench 20 semiconductor layer 10.

[0159] By forming a p-type accumulation layer on the semiconductor layer 10 on the side of the trench 20, hole discharge from the drift region 24 during turn-off is facilitated. Therefore, the recovery loss of the pin diode 300 is further reduced compared to the pin diode 100 of the first embodiment.

[0160] Furthermore, by forming a p-type accumulation layer on the semiconductor layer 10 on the side of the trench 20, the discharge of holes generated at the bottom of the trench 20 due to avalanche breakdown can also be promoted. Therefore, according to the pin diode 300, compared with the pin diode 100, the damage during reverse recovery is further suppressed, and the safe operating area during recovery can be further expanded.

[0161] in addition, Figure 11 The timing diagram shown is an example of the operation of the pin diode 300. For example, when the pin diode 300 is turned off, it is possible that an equal voltage or positive voltage is applied to the trench gate electrode 18 as to the anode electrode 12.

[0162] According to the third embodiment, a pin diode with reduced recovery loss and expanded safe operating area, as well as a semiconductor circuit having the pin diode, can be provided.

[0163] (Fourth Implementation)

[0164] The semiconductor device of the fourth embodiment differs from that of the semiconductor device of the first embodiment in that the semiconductor layer further includes a semiconductor region of a first conductivity type between the first semiconductor region and the second surface. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0165] The semiconductor device in the fourth embodiment is a pin diode 400.

[0166] Figure 13 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0167] The pin diode 400 of the fourth embodiment includes a semiconductor layer 10, an anode electrode 12 (first electrode), a cathode electrode 14 (second electrode), and a trench insulating layer 15.

[0168] The semiconductor layer 10 includes trenches 20a (first trench), 20b (second trench), 20c, 20d, 20e, a cathode region 22, a drift region 24 (first semiconductor region), a substrate region 26 (second semiconductor region), a channel region 28 (third semiconductor region), a first anode region 30a (fourth semiconductor region), a second anode region 30b (fifth semiconductor region), and a buffer region 32.

[0169] Anode electrode 12 is an example of a first electrode. Cathode electrode 14 is an example of a second electrode. Trench 20a is an example of a first trench. Trench 20b is an example of a second trench. Drift region 24 is an example of a first semiconductor region. Substrate region 26 is an example of a second semiconductor region. Channel region 28 is an example of a third semiconductor region. First anode region 30a is an example of a fourth semiconductor region. Second anode region 30b is an example of a fifth semiconductor region.

[0170] The buffer region 32 is an n-type semiconductor region. The buffer region 32 is disposed between the cathode region 22 and the drift region 24.

[0171] The n-type impurity concentration in buffer region 32 is lower than that in cathode region 22. The n-type impurity concentration in buffer region 32 is higher than that in drift region 24.

[0172] According to the fourth embodiment, the pin diode 400, by having a buffer region 32, suppresses current oscillations and voltage oscillations during reverse recovery operation.

[0173] Figure 14 This is a schematic cross-sectional view of a first modified example of the semiconductor device according to the fourth embodiment. The first modified example of the semiconductor device according to the fourth embodiment is a pin diode 401.

[0174] The difference between pin diode 401 and pin diode 400 in the fourth embodiment is that the cathode region 22 is divided into multiple parts along the second direction.

[0175] Cathode electrode 14 is in ohmic contact with cathode region 22. Cathode electrode 14 is in Schottky contact with buffer region 32.

[0176] According to the pin diode 401 of the first modification, by dividing the cathode region 22 into multiple segments, the injection of electrons from the cathode electrode 14 is suppressed. By suppressing electron injection, recovery loss is reduced.

[0177] Figure 15 This is a schematic cross-sectional view of a second variation of the semiconductor device according to the fourth embodiment. The second variation of the semiconductor device according to the fourth embodiment is a pin diode 402.

[0178] The pin diode 402 differs from the pin diode 401 of the first variant of the fourth embodiment in that a pin is provided between the divided cathode regions 22. + Type 34.

[0179] According to the second modified example of the pin diode 402, during reverse recovery operation, the diode travels from the cathode electrode 14 via the pin diode... + Holes are injected into the drift region 24 from the type region 34. By injecting holes into the drift region 24, current oscillations and voltage oscillations during reverse recovery are suppressed.

[0180] Based on the fourth embodiment and its variations, a pin diode with reduced recovery loss and expanded safe operating area can be provided.

[0181] (Fifth Implementation)

[0182] The semiconductor device of the fifth embodiment differs from that of the semiconductor device of the first embodiment in that it is an RC-IGBT that includes the pin diode of the first embodiment. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0183] The semiconductor device of the fifth embodiment is an RC-IGBT500 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT500 is a trench-gate type IGBT with a gate electrode formed in a trench in a semiconductor layer. The RC-IGBT500 includes the pin diode 100 of the first embodiment as a freewheeling diode.

[0184] The following explanation will be based on the case where the first conductivity type is n-type and the second conductivity type is p-type.

[0185] Figure 16 This is a schematic cross-sectional view of the semiconductor device circuit according to the fifth embodiment.

[0186] The RC-IGBT 500 of the fifth embodiment has an IGBT region 501 and a diode region 502. The diode region 502 includes the pin diode 100 of the first embodiment.

[0187] IGBT region 501 operates as an IGBT. Diode region 502 operates as a freewheeling diode.

[0188] The RC-IGBT500 of the fifth embodiment includes a semiconductor layer 10, an upper electrode 62 (first electrode), a lower electrode 64 (second electrode), a gate insulating film 41, a gate electrode 51, an interlayer insulating layer 61, and a trench insulating layer 15.

[0189] In the semiconductor layer 10 of the IGBT region 501, a gate trench 71 and a p-type gate are provided. + Type 78, n collector region - The drift region of the n-type is 24, the body region of the p-type is 74, the emitter region of the n-type is 76, and the contact region of the p-type is 80.

[0190] In the semiconductor layer 10 of diode region 502, trench 20a (first trench), trench 20b (second trench), trench 20c, cathode region 22, drift region 24 (first semiconductor region), substrate region 26 (second semiconductor region), channel region 28 (third semiconductor region), first anode region 30a (fourth semiconductor region) and second anode region 30b (fifth semiconductor region) are provided.

[0191] The upper electrode 62 functions as the emitter electrode of the IGBT in the IGBT region 501. The upper electrode 62 also functions as the anode electrode of the diode in the diode region 502.

[0192] The lower electrode 64 functions as the collector electrode of the IGBT in the IGBT region 501. The lower electrode 64 also functions as the cathode electrode of the diode in the diode region 502.

[0193] Gate electrode 51 functions as the gate electrode of the IGBT transistor. A gate voltage (Vg) is applied to gate electrode 51.

[0194] The RC-IGBT500 incorporates a pin diode within the same semiconductor chip, reducing recovery losses and expanding the safe operating area. Therefore, the RC-IGBT500 achieves both reduced recovery losses and an expanded safe operating area.

[0195] According to the fifth embodiment, an RC-IGBT with reduced recovery loss and expanded safe operating range can be provided.

[0196] In the first to fifth embodiments, the case where the semiconductor layer is monocrystalline silicon was described as an example, but the semiconductor layer is not limited to monocrystalline silicon. For example, it may also be other monocrystalline semiconductors such as monocrystalline silicon carbide.

[0197] In the first to fifth embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was described as an example, but it is also possible to set the first conductivity type to p-type and the second conductivity type to n-type. When the first conductivity type is p-type and the second conductivity type is n-type, for example, in the pin diode 300 of the third embodiment, when turned off, the third voltage V3 applied to the trench gate electrode 18 is applied as a voltage that is positive relative to the first voltage V1 applied to the anode electrode 12.

[0198] In the fifth embodiment, the structure of the RC-IGBT including the pin diode of the first embodiment is described as an example, but the structure of the RC-IGBT including the pin diode of the second to fourth embodiments can also be used.

[0199] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment may be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including: a first trench provided on the first surface side; a second trench provided on the first surface side; a first semiconductor region of a first conductivity type in contact with the first trench and the second trench; a second semiconductor region of a second conductivity type provided between the first surface and the first semiconductor region, provided between the first trench and the second trench, and in contact with the second trench; a third semiconductor region of the first conductivity type provided between the first semiconductor region and the first surface, provided between the first trench and the second semiconductor region, in contact with the first semiconductor region, in contact with the first trench, and in contact with the second semiconductor region; a fourth semiconductor region of the second conductivity type provided between the third semiconductor region and the first surface, provided between the first trench and the second semiconductor region, in contact with the first trench, in contact with the second semiconductor region, and having a second-conductivity-type impurity concentration higher than a second-conductivity-type impurity concentration of the second semiconductor region; and a fifth semiconductor region of the second conductivity type provided between the second semiconductor region and the first surface, the second semiconductor region being provided between the fifth semiconductor region and the fourth semiconductor region, the fifth semiconductor region being in contact with the second trench, and having a second-conductivity-type impurity concentration higher than the second-conductivity-type impurity concentration of the second semiconductor region; a first electrode provided on the first surface side of the semiconductor layer, in contact with the second semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; and a second electrode provided on the second surface side of the semiconductor layer, wherein the second semiconductor region is in contact with a first side surface of the second trench, and the fifth semiconductor region is in contact with the first side surface of the second trench.

2. The semiconductor device according to claim 1, wherein a distance between the first trench and the second trench is greater than a depth of the first trench.

3. The semiconductor device according to claim 1 or 2, wherein a first-conductivity-type impurity concentration of the third semiconductor region is higher than a first-conductivity-type impurity concentration of the first semiconductor region.

4. The semiconductor device according to claim 1 or 2, wherein a material of a first portion of the first electrode in contact with the second semiconductor region is different from a material of a second portion of the first electrode in contact with the fourth semiconductor region.

5. The semiconductor device according to claim 1 or 2, further comprising a third electrode provided in the first trench and in the second trench and electrically separated from the first electrode and the second electrode.

6. The semiconductor device according to claim 5, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ In a case where the first conductivity type is n-type, the third electrode is applied with a voltage that is negative with respect to the first electrode in a state where a voltage that is positive on the second electrode side is applied between the first electrode and the second electrode, In a case where the first conductivity type is p-type, the third electrode is applied with a voltage that is positive with respect to the first electrode in a state where a voltage that is negative on the second electrode side is applied between the first electrode and the second electrode.

7. The semiconductor device according to claim 5, wherein Further provided is an electrode pad that is provided on the first surface side of the semiconductor layer and is electrically connected to the third electrode.

8. A semiconductor circuit comprising: the semiconductor device according to claim 5 or 7; and a control circuit that drives the semiconductor device, the third electrode being applied with a voltage that is negative with respect to the first electrode in a state where a voltage that is positive on the second electrode side is applied between the first electrode and the second electrode in a case where the first conductivity type is n-type, the third electrode being applied with a voltage that is positive with respect to the first electrode in a state where a voltage that is negative on the second electrode side is applied between the first electrode and the second electrode in a case where the second conductivity type is p-type.

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