Semiconductor device

Abstract

To obtain a semiconductor device in which a mesa is easily miniaturized and latch tolerance is high. An active trench (8) penetrates the emitter layer (6) and the base layer (5) from the upper surface of the semiconductor substrate (1). A dummy trench (9) penetrates the contact layer (7) and the base layer from the upper surface of the semiconductor substrate (1) while sandwiching the active trench. A gate trench electrode (10) is formed inside the active trench through a gate insulating film (11). A dummy gate trench electrode (12) is formed inside the dummy trench through the gate insulating film. A filling insulating film (13) is formed on the gate trench electrode inside the active trench and on the dummy gate trench electrode inside the dummy trench. The upper end of the filling insulating film is lower than the upper surface of the semiconductor substrate. An emitter electrode (14) contacts the emitter layer at the upper surface of the semiconductor substrate and the inner wall of the active trench and contacts the contact layer at the upper surface of the semiconductor substrate and the inner wall of the dummy trench.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] From the viewpoint of energy saving, IGBTs and diodes are used for power modules and the like used in the field of variable speed control of three-phase motors in general inverters, AC servers, and the like. In order to reduce inverter loss, a device having low turn-off loss and low turn-on voltage is required as an IGBT and a diode.

[0003] As a device having low turn-off loss, there is a trench gate type IGBT. In the case of the trench gate type IGBT, it is possible to increase the IE effect and reduce the turn-on voltage by making the width of the mesa sandwiched by the trench gate narrow. However, the narrower the width of the mesa, the narrower the width of the contact hole for connecting the emitter electrode to the emitter layer and the contact layer. Therefore, fine processing is required, and thus it is not easy to make the width of the mesa fine. In contrast, a configuration in which a buried insulating film is formed on the gate trench electrode inside the trench has been proposed (for example, refer to Patent Document 1). Thereby, it is possible to connect the emitter electrode to the emitter layer and the contact layer without forming an interlayer insulating film and a contact hole, and thus it is easy to achieve the fine of the mesa.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2015-188104

[0005] However, the deeper the upper end of the trench gate electrode, the deeper the emitter layer needs to be made,

[0006] Therefore, the length of the base layer in the up-down direction becomes shorter. The hole current flowing from the collector at the time of cutoff flows laterally through the base layer, and thus if the length of the base layer is short, the resistance of the hole current path becomes high, and the potential of the base layer rises. Thereby, the NPN transistor composed of the emitter layer / base layer / drift layer operates, and the parasitic thyristor composed of the emitter layer / base layer / drift layer / collector layer is latched to cause destruction of the device. Therefore, there is a problem that the latch tolerance becomes poor. SUMMARY

[0007] The present application has been made in order to solve the above-described problems, and has an object to obtain a semiconductor device in which the fine of the mesa is easy and the latch tolerance is high.

[0008] The semiconductor device according to the present application is characterized by including: a semiconductor substrate having an upper surface and a lower surface opposite to each other, a drift layer of a first conductivity type formed between the upper surface and the lower surface; a base layer of a second conductivity type formed between the drift layer and the upper surface; an emitter layer of the first conductivity type and a contact layer of the second conductivity type formed between the base layer and the upper surface; an active trench passing through the emitter layer and the base layer from the upper surface; a dummy trench passing through the contact layer and the base layer from the upper surface, sandwiching the active trench; a gate trench electrode formed inside the active trench through a gate insulating film; a dummy gate trench electrode formed inside the dummy trench through the gate insulating film; a fill insulating film formed on the gate trench electrode inside the active trench and on the dummy gate trench electrode inside the dummy trench, the upper end of the fill insulating film being lower than the upper surface; and an emitter electrode in contact with the emitter layer at the upper surface and the inner wall of the active trench, and in contact with the contact layer at the upper surface and the inner wall of the dummy trench.

[0009] Effects of the Invention

[0010] In the present application, the fill insulating film is formed on the gate trench electrode inside the active trench. Thus, the emitter electrode can be connected to the emitter layer and the contact layer without forming the interlayer insulating film and the contact hole, and therefore, the mesa can be easily miniaturized. In addition, the contact layer is in contact with the emitter electrode not only at the upper surface of the semiconductor substrate but also at the inner wall of the dummy trench. Thus, at the time of cutoff, holes are discharged from the upper surface of the semiconductor substrate and the inner wall of the dummy trench to the emitter electrode. Therefore, the holes are easily discharged, and the latch-up tolerance is high. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a plan view showing the semiconductor device according to Embodiment 1.

[0012] Figure 2 is a sectional view taken along Figure 1 of I-II.

[0013] Figure 3 is a sectional view taken along Figure 1 of III-IV.

[0014] Figure 4 is a sectional view taken along Figure 1 of V-VI.

[0015] Figure 5 is a sectional view showing the semiconductor device according to Embodiment 2.

[0016] Figure 6 This is a cross-sectional view of the semiconductor device involved in Embodiment 3.

[0017] Figure 7 This is a cross-sectional view of the semiconductor device involved in Embodiment 4.

[0018] Figure 8 This is a cross-sectional view of the semiconductor device involved in Embodiment 5.

[0019] Figure 9 This is a cross-sectional view of the semiconductor device involved in Embodiment 6.

[0020] Figure 10 This is a cross-sectional view of the semiconductor device according to Embodiment 7.

[0021] Figure 11 This is a cross-sectional view showing the semiconductor device involved in Embodiment 8. Detailed Implementation

[0022] The semiconductor device according to the embodiments will be described with reference to the accompanying drawings. The same or corresponding structural elements are labeled with the same reference numerals, and sometimes repeated descriptions are omitted.

[0023] Implementation Method 1

[0024] Figure 1 This is a top view showing the semiconductor device according to Embodiment 1. The semiconductor substrate 1 has an active region 2 and a wiring region 3 when viewed from above. Furthermore, in... Figure 1 The electrodes on the substrate and the interlayer insulating film are omitted.

[0025] Figure 2 It is along Figure 1 The diagram shows a cross-sectional view along line I-II. The semiconductor substrate 1 has opposing main surfaces, namely an upper surface and a lower surface, and a drift layer 4 of a first conductivity type formed between the upper and lower surfaces. A base layer 5 of a second conductivity type is formed between the drift layer 4 and the upper surface of the semiconductor substrate 1. Furthermore, for example, the first conductivity type is n-type, and the second conductivity type is p-type. An emitter layer 6 of the first conductivity type and a contact layer 7 of the second conductivity type are formed between the base layer 5 and the upper surface of the semiconductor substrate 1.

[0026] The active trench 8 extends from the upper surface of the semiconductor substrate 1 through the emitter layer 6 and the base layer 5 to the drift layer 4. Therefore, the emitter layer 6 is formed on both sides of the active trench 8. The dumb trench 9 extends from the upper surface of the semiconductor substrate 1 through the contact layer 7 and the base layer 5 to the drift layer 4. Therefore, the contact layer 7 is formed on both sides of the dumb trench 9.

[0027] The active trench 8 and the dummy trench 9 are arranged in parallel with each other in plan view. Two dummy trenches 9 sandwich the active trench 8. Therefore, two active trenches 8 are not adjacent, and therefore the emitter layer 6 does not contact the two active trenches 8.

[0028] The gate trench electrode 10 is formed in the inside of the active trench 8 with the gate insulating film 11 interposed therebetween. The dummy gate trench electrode 12 is formed in the inside of the dummy trench 9 with the gate insulating film 11 interposed therebetween. The buried insulating film 13 is formed on the gate trench electrode 10 in the inside of the active trench 8, and is formed on the dummy gate trench electrode 12 in the inside of the dummy trench 9.

[0029] If the depth from the upper surface of the semiconductor substrate 1 to the upper end of the buried insulating film 13 is set as Dl, the depth from the upper surface of the semiconductor substrate 1 to the upper end of the gate trench electrode 10 and the dummy gate trench electrode 12 is set as D2, the depth from the upper surface of the semiconductor substrate 1 to the lower end of the emitter layer 6 is set as D3, and the depth from the upper surface of the semiconductor substrate 1 to the lower end of the contact layer 7 is set as D4, then 0 < Dl < D2 < D3 < D4. The upper end of the buried insulating film 13 is lower than the upper surface of the semiconductor substrate 1 (0 < Dl), and therefore the contact layer 7 also contacts the emitter electrode 14 at the inner wall of the dummy trench 9.

[0030] The emitter electrode 14 contacts the emitter layer 6 at the upper surface of the semiconductor substrate 1 and the inner wall of the active trench 8, and contacts the contact layer 7 at the upper surface of the semiconductor substrate 1 and the inner wall of the dummy trench 9. The buffer layer 15 of the first conductivity type is formed below the drift layer 4. The collector layer 16 of the second conductivity type is formed below the buffer layer 15. The collector electrode 17 is connected to the collector layer 16.

[0031] As described above, in the present embodiment, the buried insulating film 13 is formed on the gate trench electrode 10 in the inside of the active trench 8. Thereby, the emitter electrode 14 can be connected to the emitter layer 6 and the contact layer 7 without forming an interlayer insulating film and a contact hole, and therefore the miniaturization of the mesa is easily achieved.

[0032] Further, the contact layer 7 contacts the emitter electrode 14 not only at the upper surface of the semiconductor substrate 1, but also at the inner wall of the dummy trench 9. Therefore, at the time of cutoff, holes are discharged to the emitter electrode 14 not only from the upper surface of the semiconductor substrate 1, but also from the inner wall of the dummy trench 9. Therefore, the holes become easy to discharge, and the latch-up tolerance becomes high.

[0033] Further, the lower end of the contact layer 7 is lower than the lower end of the emitter layer 6 (D3 < D4). Therefore, at the time of cutoff, holes are easy to discharge to the contact layer 7, and the latch-up tolerance becomes high.

[0034] Further, a region between the active trench 8 and the dummy trench 9 adjacent to each other is referred to as an active mesa. If a width of the active mesa is set as Wl, a width of the emitter layer 6 exposed at the upper surface of the semiconductor substrate 1 is set as W2, and a width of the contact layer 7 exposed at the upper surface of the semiconductor substrate 1 is set as W3, Wl = W2 + W3. At the active mesa, the width W3 of the contact layer 7 exposed at the upper surface is wider than the width W2 of the emitter layer 6 exposed at the upper surface (W3 > W2). Thus, the cross-sectional area of the contact layer 7 is made larger than that of the emitter layer 6, and the hole discharge path is expanded. Thus, the latch-up tolerance is increased.

[0035] Further, the carrier accumulation layer 18 of the first conductivity type is formed between the drift layer 4 and the base layer 5. The impurity concentration of the carrier accumulation layer 18 is higher than that of the drift layer 4. Due to the carrier accumulation layer 18, the electron injection is increased, the carrier density in the drift layer 4 is increased, and thus the on-voltage is decreased.

[0036] Further, the width of the emitter layer 6 is narrowed from the upper surface toward the lower surface of the semiconductor substrate 1. Thus, the hole discharge path can be expanded, and the latch-up tolerance can be increased.

[0037] Figure 3 is a cross-sectional view taken along Figure 1 In the wiring region 3, the well layer 19 of the second conductivity type is formed between the drift layer 4 and the upper surface of the semiconductor substrate 1. The gate electrode 21 is formed at the upper surface of the semiconductor substrate 1 with the interlayer insulating film 20 interposed therebetween. In the active trench 8, the buried insulating film 13 is not formed, and the upper end of the gate trench electrode 10 is exposed at the upper surface of the semiconductor substrate 1. The gate trench electrode 10 is connected to the gate electrode 21 via the opening of the interlayer insulating film 20. Thus, the gate trench electrode 10 can be connected to the gate electrode 21 without burying the gate electrode 21 to the inside of the active trench 8.

[0038] Figure 4 is a cross-sectional view taken along Figure 1 In a part of the active region 2, in the dummy trench 9, the buried insulating film 13 is not formed, and the upper end of the dummy gate trench electrode 12 is exposed at the upper surface of the semiconductor substrate 1 to be connected to the emitter electrode 14. Thus, the dummy gate trench electrode 12 can be connected to the emitter electrode 14 without burying the emitter electrode 14 to the depth of the dummy trench 9.

[0039] Further, the emitter electrode 14 is composed of, for example, a metal such as Al or AlSi. A barrier metal can be formed between the emitter electrode 14 and the emitter layer 6 and the contact layer 7. The barrier metal is composed of, for example, Ti, TiN, or TiSi. A plug composed of W or the like can also be formed.

[0040] Embodiment 2

[0041] Figure 5 is a sectional view showing a semiconductor device to which Embodiment 2 is applied. The region between the dummy trenches 9 adjacent to each other without passing through the active trench 8 is called a dummy mesa. In the present embodiment, at the dummy mesa, the interlayer insulating film 20 is formed between the upper surface of the semiconductor substrate 1 and the emitter electrode 14, and the semiconductor substrate 1 is insulated from the emitter electrode 14. Thereby, the escape of holes from the upper portion of the dummy mesa is suppressed, the carrier density in the drift layer 4 is increased, and thus the on-voltage is decreased.

[0042] Embodiment 3

[0043] Figure 6 is a sectional view showing a semiconductor device to which Embodiment 3 is applied. In the present embodiment, the width of the dummy trench 9 is larger than the width of the active trench 8. Thereby, the width of the dummy mesa is narrowed. Further, the depth of the dummy trench 9 is larger than the depth of the active trench 8. Thereby, the escape of holes from the upper portion of the dummy mesa is suppressed, the carrier density in the drift layer 4 is increased, and thus the on-voltage is decreased.

[0044] Embodiment 4

[0045] Figure 7 is a sectional view showing a semiconductor device to which Embodiment 4 is applied. In the present embodiment, in the inside of the active trench 8, the shield electrode 22 is formed under the gate trench electrode 10. The shield electrode 22 is connected to the emitter electrode 14. The gate trench electrode 10 and the shield electrode 22 are insulated from each other by the insulating film. The upper end of the shield electrode 22 is lower than the lower end of the base layer 5. Thereby, the parasitic capacitance of the gate trench electrode 10 can be decreased.

[0046] Embodiment 5

[0047] Figure 8 is a sectional view showing a semiconductor device to which Embodiment 5 is applied. In the inside of the active trench 8, the polysilicon 23 is formed over the gate trench electrode 10 with the buried insulating film 13 interposed therebetween. The polysilicon 23 is connected to the emitter electrode. The upper end of the polysilicon 23 is lower than the upper surface of the semiconductor substrate 1. Generally, the burying property of polysilicon is better than that of the insulating film, and thus the burying property of the upper portion of the active trench 8 can be improved.

[0048] Embodiment 6

[0049] Figure 9is a sectional view showing a semiconductor device to which Embodiment 6 is applied. In the present embodiment, the gate trench electrode 10 has a first portion 10a inside the active trench 8 and a second portion 10b which is protruded upward compared to the upper surface of the semiconductor substrate 1 at a part of the wiring region 3. The second portion 10b is connected with the gate electrode 21 via the opening of the interlayer insulating film 20. The width of the second portion 10b is larger than the width of the first portion 10a. Thereby, even in the case where the position or size of the opening of the interlayer insulating film 20 fluctuates, the opening is easily formed within the range of the second portion 10b. Therefore, the possibility that the opening of the interlayer insulating film 20 shifts and causes the gate electrode 21 to contact the semiconductor substrate 1 is low, and thus, the insulating property can be improved.

[0050] Embodiment 7

[0051] Figure 10 is a sectional view showing a semiconductor device to which Embodiment 7 is applied. In the present embodiment, the width of the active trench 8 at the wiring region 3 is larger than the width of the active trench 8 at the active region 2. In this region, the gate trench electrode 10 is connected with the gate electrode 21 via the opening of the buried insulating film 13. Thereby, the opening of the buried insulating film 13 can be formed large, and thus, the filling property of the metal of the gate electrode 21 into the opening can be improved.

[0052] Embodiment 8

[0053] Figure 11 is a sectional view showing a semiconductor device to which Embodiment 8 is applied. In the present embodiment, at a part of the active region 2, the width of the dummy trench 9 is larger than the width of the active trench 8. In this region, the dummy gate trench electrode 12 is connected with the emitter electrode 14 via the opening of the buried insulating film 13. In this way, the filling property of the metal between the dummy gate trench electrode 12 and the emitter electrode 14 can be improved by making the width of the dummy trench 9 wide.

[0054] In the above-described embodiments, the case where the semiconductor device is an insulated gate type transistor (IGBT) is explained. The structure of the present application is not limited to this, and can be applied to a power device such as a MOSFET, an RC-IGBT, and the like. The withstand voltage class, FZ substrate / MCZ substrate / epitaxial substrate, and the like are not limited. In addition, a combination of different embodiments can be realized, and the structure of the other embodiment can be applied locally to certain regions.

[0055] Further, the semiconductor substrate 1 is not limited to be formed of silicon, but can be formed of a wide bandgap semiconductor having a larger bandgap than silicon. The wide bandgap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. The semiconductor device formed of such a wide bandgap semiconductor can be downsized because of high withstand voltage and high allowable current density. By using the downsized semiconductor device, a semiconductor module assembled with the semiconductor device can also be downsized and highly integrated. Further, because of high heat resistance of the semiconductor device, a heat dissipation fin of a heat sink can be downsized, a water cooling portion can be air-cooled, and thus the semiconductor module can be further downsized. Further, because of low power loss and high efficiency of the semiconductor device, the semiconductor module can be made efficient.

[0056] Explanation of reference numerals

[0057] 1 semiconductor substrate, 2 active region, 3 wiring region, 4 drift layer, 5 base layer, 6 emitter layer, 7 contact layer, 8 active trench, 9 dummy trench, 10 gate trench electrode, 10a first portion, 10b second portion, 11 gate insulating film, 12 dummy gate trench electrode, 13 buried insulating film, 14 emitter electrode, 18 carrier accumulation layer, 20 interlayer insulating film, 21 gate electrode, 22 shield electrode, 23 polysilicon

Claims

1. A semiconductor device, characterized by comprising: has: a semiconductor substrate having an upper surface and a lower surface opposite to each other, a drift layer of a first conductivity type formed between the upper surface and the lower surface; a base layer of a second conductivity type formed between the drift layer and the upper surface; an emitter layer of the first conductivity type and a contact layer of the second conductivity type formed between the base layer and the upper surface; an active trench passing through the emitter layer and the base layer from the upper surface; a dummy trench passing through the contact layer and the base layer from the upper surface sandwiching the active trench; a gate trench electrode formed inside the active trench through a gate insulating film; a dummy gate trench electrode formed inside the dummy trench through the gate insulating film; a filling insulating film formed on the gate trench electrode inside the active trench and on the dummy gate trench electrode inside the dummy trench, the upper end of the filling insulating film being lower than the upper surface; and an emitter electrode in contact with the emitter layer at the upper surface and the inner wall of the active trench, in contact with the contact layer at the upper surface and the inner wall of the dummy trench, the semiconductor substrate has an active region and a wiring region in plan view, in the active region, the emitter electrode is formed on the upper surface, in the wiring region, a gate electrode is formed on the upper surface through an interlayer insulating film, the gate trench electrode is connected to the gate electrode through an opening of the interlayer insulating film, the gate trench electrode has a first portion inside the active trench and a second portion wider than the first portion, the second portion protruding upward from the upper surface at a part of the wiring region.

2. The semiconductor device according to claim 1, wherein a lower end of the contact layer is lower than a lower end of the emitter layer.

3. The semiconductor device according to claim 1 or 2, wherein a width of the contact layer exposed at the upper surface is greater than a width of the emitter layer exposed at the upper surface in a region between the active trench and the dummy trench adjacent to each other.

4. The semiconductor device according to claim 1 or 2, wherein a width of the emitter layer narrows from the upper surface toward the lower surface.

5. The semiconductor device according to claim 1 or 2, further comprising: a carrier accumulation layer of the first conductivity type formed between the drift layer and the base layer, the impurity concentration of which is higher than that of the drift layer.

6. The semiconductor device according to claim 1 or 2, wherein an insulating film is formed between the upper surface and the emitter electrode in a region between the dummy trenches adjacent to each other.

7. The semiconductor device according to claim 1 or 2, wherein a width of the dummy trench is greater than a width of the active trench, a depth of the dummy trench is greater than a depth of the active trench.

8. The semiconductor device according to claim 1 or 2, wherein ​ ​ Further comprising a shield electrode formed inside the active trench below the gate trench electrode in connection with the emitter electrode, An upper end of the shield electrode is lower than a lower end of the base layer.

9. The semiconductor device according to claim 1 or 2, wherein Further comprising a polysilicon formed inside the active trench above the gate trench electrode in connection with the emitter electrode, An upper end of the polysilicon is lower than the upper surface.

10. The semiconductor device according to claim 1 or 2, wherein A width of the active trench at a portion of the wiring region is larger than a width of the active trench at the active region.

11. The semiconductor device according to claim 1 or 2, wherein At a portion of the active region, an upper end of the dummy gate trench electrode is exposed at the upper surface in connection with the emitter electrode.

12. The semiconductor device according to claim 11, wherein At a portion of the active region, a width of the dummy trench is larger than a width of the active trench, and the dummy gate trench electrode is connected to the emitter electrode via an opening of the fill-in insulating film.

13. The semiconductor device according to claim 1 or 2, wherein The semiconductor substrate is formed of a wide bandgap semiconductor.

Images