Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate including a first device region, the first device region including a channel region and a source / drain region isolated from the channel region, an isolation structure formed in the substrate between the source / drain region and the channel region, wherein in the first device region, a top surface of the substrate in the channel region is lower than a top surface of the substrate in the source / drain region; forming a gate oxide layer on the surface of the substrate in the channel region in the first device region; forming a first gate structure on the gate oxide layer, the first gate structure extending to the junction of the substrate in the channel region and the isolation structure and covering a portion of the top of the isolation structure; forming a protective layer on the sidewalls of the first gate structure, the protective layer also extending to cover a portion of the top of the isolation structure and exposing the substrate in the source / drain region. The protective layer can effectively cover the corners of the first gate structure and the isolation structure, thereby enhancing protection of the sidewalls of the first gate structure during subsequent cleaning processes, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, the development of ultra-large-scale integrated circuits (VLSIs) has led to a continuous reduction in IC feature size. To accommodate this reduction, the channel length of MOSFETs has also been shortened. However, as the device channel length decreases, the distance between the source and drain electrodes also decreases. This weakens the gate's ability to control the channel, making it increasingly difficult for the gate to shut off the channel. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, the short-channel effect poses significant challenges to gate structure formation in semiconductor manufacturing processes. Currently, high-k dielectric layers and metal gate structures are commonly used to replace traditional polysilicon gates to increase device speed. However, in processes that combine digital circuits with high-voltage logic circuits, simultaneously forming the gate structures for multiple devices to ensure optimal performance presents a challenge. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first device region, the first device region including a channel region, and a source and drain region isolated from the channel region, an isolation structure is formed in the substrate between the source and drain region and the channel region, and in the first device region, the top surface of the substrate of the channel region is lower than the top surface of the substrate of the source and drain region; a gate oxide layer, located on the substrate of the channel region of the first device region; a first gate structure, located on the gate oxide layer, and extending to the junction of the channel region substrate and the isolation structure and covering a portion of the top of the isolation structure; a protective layer, covering the sidewalls of the first gate structure, the protective layer also extending to cover a portion of the top of the isolation structure and exposing the substrate of the source and drain region.

[0006] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region, the first device region comprising a channel region, and a source / drain region isolated from the channel region, an isolation structure being formed in the substrate between the source / drain region and the channel region, wherein in the first device region, a top surface of the substrate of the channel region is lower than a top surface of the substrate of the source / drain region; in the first device region, a gate oxide layer is formed on the surface of the substrate of the channel region; a first gate structure is formed on the gate oxide layer, the first gate structure extends to the junction of the channel region substrate and the isolation structure and covers a portion of the top of the isolation structure; a protective layer is formed on the sidewall of the first gate structure, the protective layer also extends to cover a portion of the top of the isolation structure and exposes the substrate of the source / drain region.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] An embodiment of the present invention provides a semiconductor structure, comprising a first gate structure, located on the gate oxide layer, extending to the junction of the channel region base and the isolation structure and covering a portion of the top of the isolation structure, a protective layer covering the sidewalls of the first gate structure, the protective layer also extending to cover a portion of the top of the isolation structure and exposing the base of the source and drain regions; during the formation of the semiconductor structure, in the first device region, in order to make the top surface of the base of the channel region of the first device region lower than the top surface of the base of the source and drain regions, a step morphology is usually caused on the top surface of the isolation structure, that is, the top surface of the portion of the isolation structure adjacent to the channel region base is lower than the top surface of the remaining isolation structure; therefore, by making the protective layer also extend to cover a portion of the top of the isolation structure, when the first gate When the gate structure also extends to cover the side walls of the step, the protective layer can better cover the corners of the first gate structure and the isolation structure, thereby reducing the probability of the cleaning liquid contacting the side walls of the first gate structure through the corners during the subsequent cleaning process, enhancing the protection of the side walls of the first gate structure, and effectively reducing the damage to the first gate structure during the cleaning process. Specifically, a high-k gate dielectric layer and a metal barrier layer are stacked in sequence from bottom to top between the first gate structure and the substrate, and between the first gate structure and the isolation structure. The protective layer can protect the high-k gate dielectric layer and the metal barrier layer, and correspondingly reduces the probability of the metal barrier layer and the high-k gate dielectric layer being damaged during the cleaning process due to exposure, thereby improving the performance of the semiconductor structure.

[0009] In the formation method provided by an embodiment of the present invention, a first gate structure is formed on the gate oxide layer, the first gate structure extends to the junction of the channel region base and the isolation structure and covers a portion of the top of the isolation structure, and a protective layer is formed on the sidewall of the first gate structure, the protective layer also extends to cover a portion of the top of the isolation structure and exposes the base of the source and drain regions; during the formation of the semiconductor structure, in the first device region, in order to make the top surface of the base of the channel region of the first device region lower than the top surface of the base of the source and drain regions, a step morphology is usually caused on the top surface of the isolation structure, that is, the top surface of the portion of the isolation structure adjacent to the channel region base is lower than the top surface of the remaining isolation structure. Therefore, by making the protective layer also extend to cover a portion of the top of the isolation structure, when the When the first gate structure also extends to cover the side walls of the step, the protective layer can better cover the corners of the first gate structure and the isolation structure, thereby reducing the probability of the cleaning liquid contacting the side walls of the first gate structure through the corners during the subsequent cleaning process, enhancing the protection of the side walls of the first gate structure, and effectively reducing the damage to the first gate structure during the cleaning process. Specifically, a high-k gate dielectric layer and a metal barrier layer are stacked in sequence from bottom to top between the first gate structure and the substrate, and between the first gate structure and the isolation structure. The protective layer can protect the high-k gate dielectric layer and the metal barrier layer, and correspondingly reduces the probability of the metal barrier layer and the high-k gate dielectric layer being damaged during the cleaning process due to exposure, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figure 5 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0012] Figures 6 to 11 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in conjunction with a method for forming a semiconductor structure.

[0014] Figures 1 to 4 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1A substrate 10 is provided, including a first device region 10H, wherein the first device region 10H includes a channel region 10H1 and a source / drain region 10H2 isolated from the channel region 10H1, an isolation structure 12 is formed in the substrate 10 between the source / drain region 10H2 and the channel region 10H1, in the first device region 10H, a top surface of the substrate 10 of the channel region 10H1 is lower than a top surface of the substrate 10 of the source / drain region 10H2, a gate oxide layer 11 is formed on the surface of the substrate of the channel region 10H1, and the substrate 10 further includes a second device region 10L, wherein an operating voltage of the first device region 10H is greater than an operating voltage of the second device region 10L.

[0016] In order to improve the flatness of the top surface of the gate oxide layer 11, the top surface of the substrate 10 of the source and drain regions 10H2, and the top surface of the substrate 10 of the second device region 10L, before forming the gate oxide layer 11, it is necessary to make the top surface of the substrate 10 of the channel region 10H1 lower than the top surface of the substrate 10 of the source and drain regions 10H2. This usually results in a step morphology (such as Figure 1 (shown by the dotted circle in the middle).

[0017] refer to Figure 2 A gate structure 23 is formed on the gate oxide layer 11 and the substrate of the second device region 10L. In the first device region 10H, the gate structure 23 extends to the junction of the substrate 10 of the channel region 10H1 and the isolation structure 12 and covers a portion of the top of the isolation structure 12. The gate structure 23 includes a high-k gate dielectric layer 21, a metal barrier layer 22 located on the high-k gate dielectric layer 21, and a polysilicon gate layer 20 located on the metal barrier layer 22.

[0018] It should be noted that the gate structures 23 of the first device region 10H and the second device region 10L are formed together, and a metal gate structure needs to be formed on the second device region 10L later. Since the metal gate structure is formed by first forming a high-k gate dielectric layer and then forming a metal gate (high k first metal gate last) process, the gate structure 23 includes a high-k gate dielectric layer 21 and a metal barrier layer 22 located on the high-k gate dielectric layer 21. When the gate structure 23 of the first device region 10H is formed on the step on the top surface of the isolation structure 12, the total thickness of the high-k gate dielectric layer 21, the metal barrier layer 22, and the polysilicon gate layer 20 at the step is greater than the total thickness of the high-k gate dielectric layer 21, the metal barrier layer 22, and the polysilicon gate layer 20 in the remaining areas in a direction perpendicular to the surface of the substrate 10. Therefore, in the etching process for forming the gate structure 23, the high-k gate dielectric layer 21, the metal barrier layer 22 and the polysilicon gate layer 20 located on the step on the top surface of the isolation structure 12 are difficult to be completely etched, resulting in the high-k gate dielectric layer 21, the metal barrier layer 22 and the polysilicon gate layer 20 being difficult to form sidewalls perpendicular to the surface of the substrate 10 at the step. As a result, the sidewalls of the high-k gate dielectric layer 21 and the metal barrier layer 22 are prone to present an inclined surface morphology due to their proximity to the inclined surface of the step.

[0019] refer to Figure 3 , forming a protection layer 40 on the sidewall of the gate structure 23 .

[0020] It should be noted that the steps of forming the protective layer 40 are as follows: forming a protective material layer (not shown) that conformally covers the top surface of the substrate 10 and the gate structure 23, then removing the protective material layer on the top surface of the substrate 10 and the top surface of the gate structure 23, and retaining the protective material layer on the sidewalls of the gate structure 23 to form the protective layer 40. In the first device region 10H, since the sidewalls of the high-k gate dielectric layer 21 and the metal barrier layer 22 at the corners of the gate structure 23 and the isolation structure 12 have inclined surface morphologies, the thickness of the protective material layer at the corners is much smaller than the thickness of the protective material layer on the sidewalls of the gate structure 23 in the second device region 10L in the direction perpendicular to the surface of the substrate 10. Therefore, when removing the protective material layer on the top surface of the substrate 10 and the top surface of the gate structure 23, the protective material layer on the sidewalls of the high-k gate dielectric layer 21 and the metal barrier layer 22 is easily removed together, resulting in the exposure of the sidewalls of the high-k gate dielectric layer 21 and the metal barrier layer 22 (as shown in FIG. 1 ). Figure 3 (shown by the dotted circle in the middle).

[0021] refer to Figure 4 A sidewall spacer 41 is formed on the sidewall of the protection layer 40 on the sidewall of the gate structure 23 .

[0022] Specifically, a sidewall 41 is formed on the sidewall of the protection layer 40 .

[0023] Since the high-k gate dielectric layer 21 and the metal barrier layer 22 have inclined surfaces, the sidewalls 41 still cannot cover the exposed high-k gate dielectric layer 21 and the metal barrier layer 22 (eg, Figure 4 In the process after forming the sidewall 41, the entire substrate 10 needs to be cleaned. Since the high-k gate dielectric layer 21 and the metal barrier layer 22 are exposed, the high-k gate dielectric layer 21 and the metal barrier layer 22 are easily damaged during the cleaning process, and even part of the high-k gate dielectric layer 21 and the metal barrier layer 22 under the gate structure 23 may be removed. The integrity of the gate structure 23 is difficult to ensure, thereby affecting the performance of the semiconductor structure.

[0024] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, including a first device region, the first device region including a channel region, and a source and drain region isolated from the channel region, an isolation structure is formed in the substrate between the source and drain region and the channel region, and in the first device region, the top surface of the substrate of the channel region is lower than the top surface of the substrate of the source and drain region; in the first device region, a gate oxide layer is formed on the surface of the substrate of the channel region; a first gate structure is formed on the gate oxide layer, the first gate structure extends to the junction of the channel region substrate and the isolation structure and covers a portion of the top of the isolation structure; a protective layer is formed on the sidewall of the first gate structure, the protective layer also extends to cover a portion of the top of the isolation structure and exposes the substrate of the source and drain region.

[0025] In the formation method provided by an embodiment of the present invention, a first gate structure is formed on the gate oxide layer, the first gate structure extends to the junction of the channel region base and the isolation structure and covers a portion of the top of the isolation structure, and a protective layer is formed on the sidewall of the first gate structure, the protective layer also extends to cover a portion of the top of the isolation structure and exposes the base of the source and drain regions; in the formation process of the semiconductor structure, in the first device region, in order to make the top surface of the base of the channel region of the first device region lower than the top surface of the base of the source and drain regions, it usually causes the top surface of the isolation structure to have a step morphology, that is, the top surface of the portion of the isolation structure adjacent to the channel region base is lower than the top surface of the remaining isolation structure. Therefore, by making the protective layer also extend to cover a portion of the top of the isolation structure, when the first device region is formed, the top surface of the isolation structure is lower than the top surface of the remaining isolation structure. When a gate structure also extends to cover the side wall of the step, the protective layer can better cover the corners of the first gate structure and the isolation structure, thereby reducing the probability of the cleaning liquid contacting the side wall of the first gate structure through the corner during the subsequent cleaning process, enhancing the protection of the side wall of the first gate structure, and effectively reducing the damage to the first gate structure during the cleaning process. Usually, a high-k gate dielectric layer and a metal barrier layer stacked from bottom to top are formed between the first gate structure and the substrate, and between the first gate structure and the isolation structure. The protective layer can also protect the high-k gate dielectric layer and the metal barrier layer, and correspondingly reduces the probability of the metal barrier layer and the high-k gate dielectric layer being damaged during the cleaning process due to exposure, thereby improving the performance of the semiconductor structure.

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figure 5 FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

[0028] The semiconductor structure includes: a substrate 101 including a first device region 101H, wherein the first device region 101H includes a channel region 101H1 and a source / drain region 101H2 isolated from the channel region 101H1, an isolation structure 121 is formed in the substrate 101 between the source / drain region 101H2 and the channel region 101H1, wherein in the first device region 101H, a top surface of the substrate 101 in the channel region 101H1 is lower than a top surface of the substrate 101 in the source / drain region 101H2; and a gate oxide layer 111. , located on the substrate 101 of the channel region 101H1 of the first device region 101H; the first gate structure 201, located on the gate oxide layer 111, and extends to the junction of the substrate 101 of the channel region 101H1 and the isolation structure 121 and covers a portion of the top of the isolation structure 121; the protective layer 401, covering the sidewalls of the first gate structure 201, the protective layer 401 also extends to cover a portion of the top of the isolation structure 121, and exposes the substrate 101 of the source and drain region 101H2.

[0029] During the formation of the semiconductor structure, in the first device region 101H, in order to make the top surface of the substrate 101 of the channel region 101H1 of the first device region 101H lower than the top surface of the substrate 101 of the source and drain region 101H2, a step morphology is usually caused on the top surface of the isolation structure 121, that is, the top surface of the portion of the isolation structure 121 adjacent to the substrate 101 of the channel region 101H1 is lower than the top surface of the remaining isolation structure 121. Therefore, by extending the protection layer 401 to cover a portion of the top of the isolation structure 121, when the first gate structure 201 also extends to cover the sidewalls of the step, the protection layer 401 can better cover the first gate structure 201 and the isolation structure 121. The protective layer 401 is formed at the corner of the first gate structure 201, thereby reducing the probability of the cleaning liquid contacting the side wall of the first gate structure 201 through the corner during the subsequent cleaning process, enhancing the protection of the side wall of the first gate structure 201, and effectively reducing the damage to the first gate structure 201 caused by the cleaning process. Specifically, a high-k gate dielectric layer and a metal barrier layer are stacked in sequence from bottom to top between the first gate structure 201 and the substrate 101, and between the first gate structure 201 and the isolation structure 121. The protective layer 401 can protect the high-k gate dielectric layer and the metal barrier layer, and correspondingly reduces the probability of the metal barrier layer and the high-k gate dielectric layer being damaged during the cleaning process due to exposure, thereby improving the performance of the semiconductor structure.

[0030] The substrate 101 provides a process operation basis for the formation process of the semiconductor structure.

[0031] The base 101 includes a substrate. In this embodiment, the substrate is made of silicon. In other embodiments, the substrate can be made of one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate can be made of a material suitable for process requirements or easy to integrate.

[0032] It should be noted that when the formation method is used to form a fin field effect transistor, the substrate 100 may further include a fin portion located on the substrate. As an example, the fin portion and the substrate are made of the same material.

[0033] In this embodiment, the substrate 101 includes a first device region 101H, and the first device region 101H is used to form a first device.

[0034] In this embodiment, the first device includes one or both of a medium-voltage device and a high-voltage device. The operating voltages of the medium-voltage device and the high-voltage device increase in sequence. Specifically, the operating voltage of the medium-voltage device is 1V to 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0035] As an example, the first device is a high-voltage device.

[0036] In this embodiment, the first device region 101H includes a channel region 101H1 and a source / drain region 101H2 isolated from the channel region 101H1. When the semiconductor structure is working, the channel region 101H1 is used to form a channel, and the source / drain region 101H2 is used to form source / drain doping regions of the first device.

[0037] The isolation structure 121 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation structure 121 is usually formed between an NMOS transistor and a PMOS transistor.

[0038] In this embodiment, in the first device region 101H, the isolation structure 121 is used to achieve insulation between the channel region 101H1 and the source and drain regions 101H2.

[0039] The isolation structure 121 is made of an insulating material. In this embodiment, the isolation structure 121 is made of silicon oxide.

[0040] The gate oxide layer 111 is used as a gate dielectric layer of the first device.

[0041] The gate oxide layer 111 is made of silicon oxide.

[0042] It should be noted that, in order to improve the flatness of the top surface of the gate oxide layer 111 on the substrate 101 of the channel region 101H1 and the top surface of the substrate 101 of the source and drain region 101H2, the top surface of the substrate 101 of the channel region 101H1 is made lower than the top surface of the substrate 101 of the source and drain region 101H2. During the formation of the semiconductor structure, the substrate 101 of the channel region 101H1 is usually etched so that the top surface of the substrate 101 of the channel region 101H1 is lower than the top surface of the substrate 101 of the source and drain region 101H2. During this etching process, part of the isolation structure 121 adjacent to the substrate 101 of the channel region 101H1 is usually exposed, resulting in the loss of part of the isolation structure 121, which usually causes the top surface of the isolation structure 121 between the channel region 101H1 and the source and drain region 101H2 to have a step morphology (such as Figure 5 (shown by the dotted circle in the middle).

[0043] The first gate structure 201 is a device gate structure of the first device region 101H, and is used to control the opening and closing of the channel of the first device.

[0044] It should be noted that, since the first gate structure 201 extends to the junction of the channel region 101H1 substrate 101 and the isolation structure 121 and covers a portion of the top of the isolation structure 121, when the first gate structure 201 extends to cover the sidewall of the step, along the direction perpendicular to the surface of the substrate 101, the thickness of the first gate structure 201 at the step is greater than the thickness of the first gate structure 201 in the remaining area. Therefore, in the etching process for forming the first gate structure 201, it is difficult to completely etch the first gate structure 201 located on the sidewall of the step, which makes it difficult for the first gate structure 201 to form a sidewall perpendicular to the surface of the substrate 101, especially the sidewall of the bottom portion of the first gate structure 201 presents an inclined surface morphology (such as Figure 5 (shown by the dotted circle in the middle).

[0045] In this embodiment, the first gate structure 201 includes a polysilicon gate structure. Specifically, the first device includes one or both of a medium voltage device and a high voltage device. The first device has a relatively high operating voltage, and the polysilicon gate structure is used to meet the performance requirements of the first device.

[0046] In this embodiment, the operating voltage of the first device is relatively high. Therefore, the substrate 101 further includes a second device region 101L for forming a second device. The operating voltage of the second device region 101L is lower than that of the first device region 101H.

[0047] In this embodiment, the second device is a low-voltage device. The operating voltages of the low-voltage device, the medium-voltage device, and the high-voltage device increase in sequence. As an example, the operating voltage of the low-voltage device is less than 1V.

[0048] In this embodiment, the second device region 101L includes an NMOS region 101N for forming an N-type transistor and a PMOS region 101P for forming a P-type transistor.

[0049] In this embodiment, the semiconductor structure further includes a second gate structure 601 located on the substrate 101 in the second device region 101L.

[0050] The second gate structure 601 is a device gate structure of a second device, and is used to control the opening and closing of a channel of the second device.

[0051] In this embodiment, the second gate structure 601 includes a metal gate structure. Since the operating voltage of the second device is relatively low, a metal gate structure is used to improve the short channel effect.

[0052] The metal gate structure includes a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer.

[0053] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TaN, TiAl, Mo, MoN, AlN, and TiAlC.

[0054] The gate electrode layer is used to electrically lead out the metal gate structure. In this embodiment, the gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti or W.

[0055] It should be noted that, during the formation of the semiconductor structure, a metal gate structure is formed by first forming a high-k gate dielectric layer and then forming a metal gate (high k first metal gate last) process. Before forming the metal gate structure, a first gate structure 201 is usually formed at the position of the metal gate structure to occupy the position of the metal gate structure.

[0056] Therefore, in this embodiment, the semiconductor structure also includes a high-k gate dielectric layer 211, which is located between the first gate structure 201 and the gate oxide layer 111, between the first gate structure 201 and the isolation structure 121, and between the second gate structure 601 and the substrate 101; and a metal barrier layer 221, which is located between the first gate structure 201 and the high-k gate dielectric layer 211, and between the second gate structure 601 and the high-k dielectric layer 211.

[0057] The high-k gate dielectric layer 211 is made of a high-k dielectric material, where a high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. As an example, the material of the high-k gate dielectric layer 211 is HfO2.

[0058] The metal barrier layer 221 is used to isolate the high-k gate dielectric layer 211 and the gate electrode layer in the metal gate structure to protect the high-k gate dielectric layer 211. Moreover, the metal barrier layer 221 is also used to prevent easily diffusible ions (such as Al ions) in the gate electrode layer from diffusing into the high-k gate dielectric layer 211.

[0059] Specifically, the material of the metal barrier layer 221 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 221 is titanium nitride.

[0060] In this embodiment, since the high-k gate dielectric layer 211 and the metal barrier layer 221 are located at the bottom of the gate structure, at the step position on the top surface of the isolation structure 121, along the direction perpendicular to the surface of the substrate 101, the total thickness of the high-k gate dielectric layer 211 and the metal barrier layer 221 at the step is greater than the total thickness of the high-k gate dielectric layer 211 and the metal barrier layer 221 in the remaining areas. Therefore, in the etching process for removing the high-k gate dielectric layer 211 and the metal barrier layer 221 exposed by the first gate structure 201, it is difficult to completely etch the high-k gate dielectric layer 211 and the metal barrier layer 221 at the step, which easily causes the high-k gate dielectric layer 211 and the metal barrier layer 221 to present an inclined surface morphology at the step (e.g., Figure 5 dotted circle).

[0061] In this embodiment, a source-drain epitaxial layer 131 is further formed in the substrate on both sides of the second gate structure 601 of the PMOS region 101P.

[0062] The source / drain epitaxial layer 131 is formed by epitaxy. The material of the source / drain epitaxial layer 131 includes Si or SiGe. The source / drain epitaxial layer 131 provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The source / drain epitaxial layer 131 is doped with P-type ions, including B, Ga, or In.

[0063] In this embodiment, the protection layer 401 also covers the sidewalls of the second gate structure 601 .

[0064] The protective layer 401 is used to protect the sidewalls of the first gate structure 201 during the cleaning process after the spacer is formed. The protective layer 401 also extends to cover the portion of the top of the isolation structure 121 exposed by the first gate structure 201. Therefore, even if the sidewalls of the bottom portion of the first gate structure 201 have an inclined surface, the protective layer 401 can still completely cover the side of the first gate structure 201, thereby protecting the first gate structure 201.

[0065] Specifically in this embodiment, the protective layer 401 also covers the sidewalls of the high-k gate dielectric layer 211 and the metal barrier layer 221. In the first device region 101H, the protective layer 401 extends to cover a portion of the top of the isolation structure 121. Therefore, at the corners of the first gate structure 201 and the isolation structure 121, during the subsequent cleaning process, the protective layer 401 can cover the high-k gate dielectric layer 211 and the metal barrier layer 221 with inclined surfaces, thereby reducing the probability of the cleaning liquid contacting the sidewalls of the high-k gate dielectric layer 211 and the metal barrier layer 221 through the corners, thereby reducing the probability of damage to the high-k gate dielectric layer 211 and the metal barrier layer 221.

[0066] Moreover, the protective layer 401 also exposes the substrate of the source and drain region 101H2, for forming source and drain doped regions in the substrate of the source and drain region 101H2; in the second device region 101H, the protective layer 401 exposes the substrate 101 of the PMOS region, for forming a source and drain epitaxial layer 131.

[0067] The dimension d extending from the protective layer 401 to the top of the isolation structure 121 should not be too large or too small. If the dimension d extending from the protective layer 401 to the top of the isolation structure 121 is too large, it may easily extend and cover the top of the substrate 101 of the source and drain regions 101H2 adjacent to the isolation structure 121, making it difficult to form source and drain doped regions. If the dimension d extending from the protective layer 401 to the top of the isolation structure 121 is too small, there is a risk that the sidewalls of the first gate structure 201 may not be fully covered. Specifically, if the dimension d extending from the protective layer 401 to the top of the isolation structure 121 is too small, there is a risk that the sidewalls of the high-k gate dielectric layer 211 and the metal barrier layer 221 may not be fully covered, thereby increasing the probability of damage to the high-k gate dielectric layer 211 and the metal barrier layer 221. Therefore, in this embodiment, the dimension d extending from the protective layer 401 to the top of the isolation structure 121 is 30 nanometers to 60 nanometers.

[0068] In this embodiment, the material of the protective layer 401 includes silicon nitride, silicon oxynitride, or a stacked structure of silicon oxide and silicon nitride. The stacked structure of silicon oxide and silicon nitride means that the protective layer includes a silicon oxide layer and a silicon nitride layer covering the sidewalls of the silicon oxide layer, that is, the protective layer has an ON (oxide-nitride) structure.

[0069] Silicon nitride has high hardness and density, and can better protect the sidewall of the first gate structure 201 .

[0070] In this embodiment, a sidewall 411 is further formed on the sidewall of the protection layer 401 .

[0071] The spacer 411 enhances protection of the first gate structure 201 .

[0072] The sidewall spacer 411 is used to protect the sidewalls of the first gate structure 201 and the second gate structure 601 .

[0073] The material of the sidewall spacer 411 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride. The sidewall spacer 411 can have a single-layer structure or a stacked structure. In this embodiment, the sidewall spacer 411 has a stacked structure including a silicon oxide layer (not shown) and a silicon nitride layer (not shown) located on the silicon oxide layer.

[0074] In this embodiment, the semiconductor structure further includes source and drain doping regions (not shown) located in the substrate 101 exposed by the sidewalls 411 . The sidewalls 411 are also used to define the positions of the source and drain doping regions.

[0075] Specifically, a source-drain epitaxial layer 131 is formed in the substrate on both sides of the second gate structure 601 of the PMOS region 101P, and the source-drain epitaxial layer 131 is formed by epitaxy. Therefore, the source-drain doped regions are respectively located in the substrate 101 exposed by the side wall 411 of the first device region 101H, and in the substrate 101 exposed by the side wall 411 of the NMOS region 101N. The source-drain doped regions are formed by performing source-drain injection into the substrate 101.

[0076] Specifically, when the substrate 101 is used to form an NMOS transistor, the doping ions in the source and drain doping regions are N-type ions, and the N-type ions include P ions, As ions, or Sb ions; when the substrate 101 is used to form a PMOS transistor, the doping ions in the source and drain doping regions are P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0077] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 501 located on the substrate 101 and covering sidewalls of the first gate structure 201 and the second gate structure 601 . The interlayer dielectric layer 501 exposes the top of the second gate structure 601 .

[0078] The interlayer dielectric layer 501 is used to isolate adjacent devices and also to provide a process platform for forming the second gate structure 601 .

[0079] The material of the interlayer dielectric layer 501 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0080] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure.

[0081] Figures 6 to 11 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0082] refer to Figure 6 A substrate 100 is provided, including a first device region 100H, wherein the first device region 100H includes a channel region 100H1 and a source / drain region 100H2 isolated from the channel region 100H1, an isolation structure 120 is formed in the substrate 100 between the source / drain region 100H2 and the channel region 100H1, and in the first device region 100H, a top surface of the substrate 100 in the channel region 100H1 is lower than a top surface of the substrate 100 in the source / drain region 100H2.

[0083] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0084] The base 100 includes a substrate. In this embodiment, the substrate is made of silicon. In other embodiments, the substrate can be made of one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. The substrate can be made of a material suitable for process requirements or easy to integrate.

[0085] It should be noted that when the formation method is used to form a fin field effect transistor, the substrate 100 may further include a fin portion located on the substrate. As an example, the fin portion and the substrate are made of the same material.

[0086] In this embodiment, the substrate 100 includes a first device region 100H, and the first device region 100H is used to form a first device.

[0087] In this embodiment, the first device includes one or both of a medium-voltage device and a high-voltage device. The operating voltages of the medium-voltage device and the high-voltage device increase in sequence. Specifically, the operating voltage of the medium-voltage device is 1V to 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0088] As an example, the first device is a high-voltage device.

[0089] In this embodiment, the first device region 100H includes a channel region 100H1 and a source / drain region 100H2 isolated from the channel region 100H1. When the semiconductor structure is operating, the channel region 100H1 is used to form a channel, and the source / drain region 100H2 is used to form source / drain doping regions of the first device.

[0090] The isolation structure 120 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation structure 120 is usually formed between an NMOS transistor and a PMOS transistor.

[0091] In this embodiment, in the first device region 100H, the isolation structure 120 is used to achieve insulation between the channel region 100H1 and the source and drain region 100H2.

[0092] The isolation structure 120 is made of an insulating material. In this embodiment, the isolation structure 120 is made of silicon oxide.

[0093] It should be noted that a gate oxide layer needs to be formed on the surface of the substrate 100 of the channel region 101H1 later. In order to improve the flatness of the top surface of the gate oxide layer on the substrate 100 of the channel region 100H1 and the top surface of the substrate 100 of the source and drain region 100H2, the top surface of the substrate 100 of the channel region 100H1 is made lower than the top surface of the substrate 100 of the source and drain region 100H2. During the formation of the semiconductor structure, the substrate 100 of the channel region 100H1 is usually etched so that the top surface of the substrate 100 of the channel region 100H1 is lower than the top surface of the substrate 100 of the source and drain region 100H2. During this etching process, part of the isolation structure 120 adjacent to the substrate 100 of the channel region 100H1 is usually exposed, resulting in the loss of part of the isolation structure 120, which usually causes a step morphology (such as Figure 6 (shown by the dotted circle in the middle).

[0094] The substrate 100 further includes a second device region 100L for forming a second device. The operating voltage of the second device region 100L is lower than the operating voltage of the first device region 100H.

[0095] In this embodiment, the second device is a low-voltage device. The operating voltages of the low-voltage device, the medium-voltage device, and the high-voltage device increase in sequence. As an example, the operating voltage of the low-voltage device is less than 1V.

[0096] In this embodiment, the second device region 100L includes an NMOS region 100N and a PMOS region 100P, which are used to form an N-type transistor and a P-type transistor, respectively.

[0097] Continue to refer Figure 6 In the first device region 100H, a gate oxide layer 110 is formed on the surface of the substrate 100 in the channel region 100H1.

[0098] The gate oxide layer 110 is used as a gate dielectric layer of a transistor formed in the first device.

[0099] In this embodiment, the gate oxide layer 110 is formed by an oxidation process.

[0100] The gate oxide layer 110 is made of silicon oxide.

[0101] refer to Figure 7 A first gate structure 200 is formed on the gate oxide layer 110 . The first gate structure 200 extends to the junction of the channel region 100H1 substrate 100 and the isolation structure 120 and covers a portion of the top of the isolation structure 120 .

[0102] In the first device region 100H, the first gate structure 200 is a device gate structure of a first device, and is used to control the opening and closing of a channel of the first device.

[0103] It should be noted that, since the first gate structure 200 extends to the junction of the channel region 100H1 substrate 100 and the isolation structure 120 and covers part of the top of the isolation structure 120, when the first gate structure 200 extends to cover the side wall of the step, along the direction perpendicular to the surface of the substrate 100, the thickness of the first gate structure 200 at the step is greater than the thickness of the first gate structure 200 in the remaining areas. Therefore, in the etching process for forming the first gate structure 200, the first gate structure 200 located on the side wall of the step is difficult to be completely etched, which makes it difficult for the first gate structure 200 to form a side wall perpendicular to the substrate 100 at the step, especially the side wall of the bottom part of the first gate structure 200 presents an inclined surface morphology.

[0104] In this embodiment, the first device has a relatively high operating voltage, and therefore, the first gate structure 200 comprises a polysilicon gate structure. Specifically, the first device comprises one or both of a medium-voltage device and a high-voltage device. The first device has a relatively high operating voltage, and the polysilicon gate structure is employed to meet the performance requirements of the first device.

[0105] In this embodiment, in the step of forming the first gate structure 200 , the first gate structure 200 is further formed on the substrate 100 in the second device region 100L.

[0106] In the second device region 100L, the first gate structure 200 occupies space for a metal gate structure to be formed later. Since the operating voltage of the second device is relatively low, a metal gate structure is subsequently used to improve the short channel effect.

[0107] Specifically, in this embodiment, the steps of forming the first gate structure 200 include: forming a first gate structure material layer (not shown) on the substrate 100, removing part of the first gate structure material layer, retaining part of the first gate structure material layer located at the junction of the substrate 100 and the isolation structure 120 in the channel area 100H1 and covering part of the top of the isolation structure 120, and part of the first gate structure material layer located on the substrate 100 in the second device area 100L as the first gate structure 200.

[0108] Since the first gate structure 200 located in the second device region 100L needs to be subsequently formed into a metal gate structure, and the metal gate structure is formed by first forming a high-k gate dielectric layer and then forming a metal gate (high k first metal gate last) process, therefore, in this embodiment, before forming the first gate structure 200 on the gate oxide layer 110, it also includes: forming a high-k gate dielectric layer 210 on the gate oxide layer 110, the isolation structure 120 and the substrate 100 of the second device region 100L, and a metal barrier layer 220 located on the high-k gate dielectric layer 210.

[0109] The first gate structure 200 is correspondingly formed on the metal barrier layer 220; therefore, the formation method also includes: removing the metal barrier layer 220 and the high-k gate dielectric layer 210 exposed by the first gate structure 200, so that in the first device area 100H, the high-k gate dielectric layer 210 and the metal barrier layer 220 extend to the junction of the channel area 100H1 substrate 100 and the isolation structure 120 and cover part of the top of the isolation structure 120.

[0110] The high-k gate dielectric layer 210 is made of a high-k dielectric material, where a high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. As an example, the material of the high-k gate dielectric layer 210 is HfO2.

[0111] The metal barrier layer 220 is used to isolate the high-k gate dielectric layer 210 and the gate electrode layer in the metal gate structure to protect the high-k gate dielectric layer 210. Moreover, the metal barrier layer 220 is also used to prevent easily diffusible ions (such as Al ions) in the gate electrode layer from diffusing into the high-k gate dielectric layer 210.

[0112] Specifically, the material of the metal barrier layer 220 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 220 is titanium nitride.

[0113] In this embodiment, since the high-k gate dielectric layer 210 and the metal barrier layer 220 are located at the bottom of the first gate structure 200, at the step morphology position on the top surface of the isolation structure 120, along the direction perpendicular to the surface of the substrate 100, the total thickness of the high-k gate dielectric layer 210 and the metal barrier layer 220 at the step is greater than the total thickness of the high-k gate dielectric layer 210 and the metal barrier layer 220 in the remaining area. Therefore, in the etching process for removing the high-k gate dielectric layer 210 and the metal barrier layer 220 exposed by the first gate structure 200, it is difficult to completely etch the high-k gate dielectric layer 210 and the metal barrier layer 220 located at the step, which easily causes the high-k gate dielectric layer 210 and the metal barrier layer 220 to present an inclined surface morphology (such as Figure 7 dotted circle).

[0114] In this embodiment, a hard mask layer 300 is further formed on the top of the first gate structure 200 .

[0115] The hard mask layer 300 serves as an etching mask for forming the first gate structure 200 and is also used to protect the top of the first gate structure 200 .

[0116] The material of the hard mask layer 300 includes silicon nitride.

[0117] Combined with reference Figure 8 and Figure 9 A protection layer 400 is formed on the sidewalls of the first gate structure 200 . The protection layer 400 also extends to cover a portion of the top of the isolation structure 120 and exposes the substrate 100 of the source and drain region 100H2 .

[0118] During the formation of the semiconductor structure, in the first device region 100H, in order to make the top surface of the substrate 100 of the channel region 100H1 of the first device region 100H lower than the top surface of the substrate 100 of the source and drain region 100H2, a step morphology is usually caused on the top surface of the isolation structure 120, that is, the top surface of the portion of the isolation structure 120 adjacent to the substrate 100 of the channel region 100H1 is lower than the top surface of the remaining isolation structure 120. Therefore, by extending the protection layer 400 to cover a portion of the top of the isolation structure 120, when the first gate structure 200 also extends to cover the sidewalls of the step, the protection layer 400 can better cover the first gate structure 200 and the isolation structure 120. The corners are located at the bottom of the first gate structure 200, thereby reducing the probability of the cleaning liquid contacting the side walls of the first gate structure 200 through the corners during the subsequent cleaning process, enhancing the protection of the side walls of the first gate structure 200, and effectively reducing the damage to the first gate structure 200 caused by the cleaning process. Specifically, a high-k gate dielectric layer and a metal barrier layer are formed between the first gate structure 200 and the substrate 100, and between the first gate structure 200 and the isolation structure 120. The protective layer 400 can protect the high-k gate dielectric layer and the metal barrier layer, and correspondingly reduces the probability of the metal barrier layer and the high-k gate dielectric layer being damaged during the cleaning process due to exposure, thereby improving the performance of the semiconductor structure.

[0119] Specifically, the high-k gate dielectric layer 210 and the metal barrier layer 220 are located at the bottom of the first gate structure 200. Therefore, in the step of forming the protective layer 400 on the sidewalls of the first gate structure 200, the protective layer 400 also covers the sidewalls of the high-k gate dielectric layer 210 and the metal barrier layer 220. The protective layer 400 can cover the sidewalls of the high-k gate dielectric layer 210 and the metal barrier layer 220, thereby reducing the probability of damage to the high-k gate dielectric layer 210 and the metal barrier layer 220 due to exposure in subsequent processes.

[0120] The dimension d extending from the protective layer 400 to the top of the isolation structure 120 should not be too large or too small. If the dimension d extending from the protective layer 400 to the top of the isolation structure 120 is too large, it may easily extend and cover the top of the substrate 100 of the source and drain regions 100H2 adjacent to the isolation structure 120, making it difficult to form source and drain doped regions. If the dimension d extending from the protective layer 400 to the top of the isolation structure 120 is too small, there is a risk that the sidewalls of the first gate structure 200 may not be fully covered. Specifically, if the dimension d extending from the protective layer 400 to the top of the isolation structure 120 is too small, there is a risk that the sidewalls of the high-k gate dielectric layer 210 and the metal barrier layer 220 may not be fully covered, thereby increasing the probability of damage to the high-k gate dielectric layer 210 and the metal barrier layer 220. Therefore, in this embodiment, the dimension d extending from the protective layer 400 to the top of the isolation structure 120 is 30 nanometers to 60 nanometers.

[0121] In this embodiment, the material of the protective layer 400 includes silicon nitride, silicon oxynitride, or a stacked structure of silicon oxide and silicon nitride. The stacked structure of silicon oxide and silicon nitride means that the protective layer includes a silicon oxide layer and a silicon nitride layer covering the sidewalls of the silicon oxide layer, that is, the protective layer has an ON (oxide-nitride) structure.

[0122] Silicon nitride has high hardness and density, and can better protect the sidewall of the first gate structure 200 during the process of forming the semiconductor.

[0123] Specifically, refer to Figure 8 The step of forming the protective layer 400 includes: forming a protective material layer 410 on the substrate 100, wherein the protective material layer 410 conformally covers the top of the substrate 100 of the first device region 100H and the top and sidewalls of the first gate structure 200.

[0124] Forming the protective material layer 410 facilitates directly forming the protective layer 400 .

[0125] In this embodiment, the process of forming the protective material layer 410 includes an atomic layer deposition process or a chemical vapor deposition process.

[0126] The protective material layer 410 formed by the atomic layer deposition process or the chemical vapor deposition process has good thickness uniformity and good step coverage capability, so that the protective material layer 410 can conformally cover the top of the substrate 100 of the first device area 100H, the top and side walls of the first gate structure 200, and the bottom corners of the first gate structure 200 and the isolation structure 120.

[0127] The protective material layer 410 may be made of silicon nitride, silicon oxynitride, or a stacked structure of silicon oxide and silicon nitride.

[0128] In this embodiment, in the step of forming the protection material layer 410 , the protection material layer 410 also covers the substrate 100 of the second device region 100L and the top and sidewalls of the first gate structure 200 .

[0129] The protective layer 400 formed by the protective material layer 410 is also used to protect the side walls of the first gate structure 200 of the second device area 100L. In addition, it is necessary to form side walls on the side walls of the protective layer 400 later. Compared with the solution of forming only side walls, the thickness of the stack formed by the protective layer 400 and the side walls is larger, thereby enhancing the protection performance of the side walls of the first gate structure 200.

[0130] Continue to refer Figure 8 After forming the protective material layer 410 , a first patterning process is performed on the protective material layer 410 to remove the protective material layer 410 located on the top of the first gate structure 200 of the PMOS region 100P and the top of the substrate 100 .

[0131] A first patterning process is performed to expose the substrate 100 in the PMOS region 100P, so that the remaining protection material layer 410 serves as a mask for subsequent formation of source and drain epitaxial layers.

[0132] In this embodiment, a dry etching process is used to remove the protective material layer 410 located on the top of the first gate structure 200 and the top of the substrate 100 in the PMOS region 100P.

[0133] The dry etching process has anisotropic characteristics and good directionality during the etching process. Its vertical etching rate is much greater than the lateral etching rate, and it can obtain quite accurate pattern conversion. In the process of removing the protective material layer 410 located on the top of the first gate structure 200 and the top of the substrate 100 in the PMOS region 100P, damage to the protective material layer 410 located on the side wall of the first gate structure 200 is reduced.

[0134] Specifically, the first patterning step includes: forming a first mask layer (not shown) on the substrate 100, wherein a first opening is formed on the first mask layer to expose the protective material layer 410 of the PMOS region 100P; using the first opening as a mask opening, etching the protective material layer 410 located on the top of the first gate structure 200 of the PMOS region 100P and the top of the substrate 100; and removing the first mask layer.

[0135] In this embodiment, after the first patterning process, a source-drain epitaxial layer 130 is formed in the substrate 100 on both sides of the first gate structure 200 in the PMOS region 100P.

[0136] Specifically, the source / drain epitaxial layer 130 is formed by epitaxial growth, and in-situ self-doping is performed during the epitaxial growth process, so that the source / drain epitaxial layer 130 is doped with ions.

[0137] The source / drain epitaxial layer 130 is made of Si or SiGe. It provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The source / drain epitaxial layer 130 is doped with P-type ions, including B, Ga, or In.

[0138] refer to Figure 9 In the first device region 100H, the protective material layer 410 (eg, Figure 8 As shown), the remaining protective material layer 410 covering the top and sidewalls of the first gate structure 200 and a portion of the isolation structure 120 is retained as the protective layer 400.

[0139] In the first device region 100H, the protective layer 400 not only covers the sidewalls of the first gate structure 200 but also extends to cover a portion of the top of the isolation structure 120. Thus, the protective layer 401 can cover the high-k gate dielectric layer 210 and the metal barrier layer 220, which have inclined surfaces, thereby reducing the probability of damage to the high-k gate dielectric layer 210 and the metal barrier layer 220. Furthermore, the protective layer 400 also exposes the base of the source / drain region 100H2, facilitating subsequent source / drain implantation in the source / drain region 100H2.

[0140] Specifically, after forming the source and drain epitaxial layer 130, the protective material layer 410 is subjected to a second graphical treatment to remove the protective material layer 410 located on the top of the substrate 100 in the source and drain region 100H2 and the top of the partial isolation structure 120 adjacent to the substrate 100 in the source and drain region 100H2. At the same time, the protective material layer 410 located on the top of the first gate structure 200 of the NMOS region 100N and the top of the substrate 100 is removed. The remaining protective material layer 410 after the second graphical treatment serves as the protective layer 400.

[0141] The protective material layer 410 located on the top of the first gate structure 200 of the NMOS region 100N and the top of the substrate 100 is removed to expose the substrate 100 in preparation for subsequent source-drain implantation in the NMOS region 100N.

[0142] Moreover, by utilizing the second graphical treatment, the protective material layer 410 located on the top of the substrate 100 in the source / drain region 100H2 and on the top of the partial isolation structure 120 adjacent to the substrate 100 in the source / drain region 100H2 is removed, and at the same time, the protective material layer 410 located on the top of the first gate structure 200 in the NMOS region 100N and on the top of the substrate 100 is removed, thereby simplifying the process steps.

[0143] In this embodiment, a dry etching process is used to remove the protective material layer 410 located on the top of the substrate 100 in the source and drain region 100H2 and the top of the partial isolation structure 120 adjacent to the substrate 100 in the source and drain region 100H2. At the same time, the protective material layer 410 located on the top of the first gate structure 200 in the NMOS region and the top of the substrate 100 is removed.

[0144] The dry etching process has anisotropic characteristics and good directionality during the etching process. Its vertical etching rate is much greater than the lateral etching rate, and it can obtain quite accurate pattern conversion. In the process of removing the protective material layer 410 located on the top of the substrate 100 in the source and drain region 100H2 and the top of the partial isolation structure 120 adjacent to the substrate 100 in the source and drain region 100H2, and at the same time, removing the protective material layer 410 located on the top of the first gate structure 200 in the NMOS region 100N and the top of the substrate 100, damage to the protective layer 400 to be formed is reduced.

[0145] Specifically, the second patterning step includes: forming a second mask layer (not shown) on the substrate 100, wherein a second opening is formed on the second mask layer, exposing the top of the substrate 100 in the source and drain region 100H2, the top of the portion of the isolation structure 120 adjacent to the substrate 100 in the source and drain region 100H2, and the protective material layer 410 in the NMOS region 100N; using the second opening as a mask opening, etching the top of the substrate 100 in the source and drain region 100H2, the top of the portion of the isolation structure 120 adjacent to the substrate 100 in the source and drain region 100H2, the top of the first gate structure 200 in the NMOS region 100N, and the protective material layer 410 on the top of the substrate 100; and removing the second mask layer.

[0146] It should be noted that, compared with the prior art, in this embodiment, there is no need to increase the number of patterning processes, change the original process sequence, or add additional steps. It is only necessary to change the opening size and position of the second opening formed during the second patterning process so that the second opening exposes the top of the portion of the isolation structure 120 adjacent to the source / drain region 100H2 substrate 100. This can achieve the process effect without increasing the number of masks and avoiding increasing the process flow and process difficulty, which is conducive to simplifying the process flow and saving process costs.

[0147] refer to Figure 10 After forming the protection layer 400 , the method further includes: forming a sidewall 410 covering the protection layer 400 on the sidewall of the first gate structure 200 ; and performing source / drain implantation on the substrate 100 exposed by the sidewall 410 .

[0148] The sidewall spacer 410 is used to protect the sidewall of the first gate structure 200 . Meanwhile, the sidewall spacer 410 is also used to define the location for source and drain implantation.

[0149] Specifically, a source-drain epitaxial layer 130 is formed in the substrate 100 on both sides of the first gate structure 200 of the PMOS region 100P. The source-drain epitaxial layer 130 is formed by epitaxy. Therefore, source-drain injection is performed on the substrate 100 exposed by the sidewall 410 of the first device region 101H, and source-drain injection is performed on the substrate 100 exposed by the sidewall 410 of the NMOS region 100N, thereby forming source-drain doped regions in the first device region 101H and the NMOS region 100N, respectively (not shown in the figure).

[0150] The material of the sidewall spacer 410 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride. The sidewall spacer 410 can have a single-layer structure or a stacked structure. In this embodiment, the sidewall spacer 410 has a stacked structure including a silicon oxide layer (not shown) and a silicon nitride layer (not shown) located on the silicon oxide layer.

[0151] Specifically, when the substrate 100 is subjected to source-drain implantation to form a source-drain doped layer (not shown), when the substrate 100 is used to form an NMOS transistor, the implanted ions of the source-drain implantation are N-type ions, that is, the doped ions in the source-drain doped region are N-type ions, and the N-type ions include P ions, As ions or Sb ions; when the substrate 100 is used to form a PMOS transistor, the implanted ions of the source-drain implantation are P-type ions, that is, the doped ions in the source-drain doped region are P-type ions, and the P-type ions include B ions, Ga ions or In ions.

[0152] It should be noted that after forming the sidewall spacers 410 , the process further includes: cleaning the substrate 100 . The cleaning process is used to remove residues on the substrate 100 during the semiconductor manufacturing process, in preparation for the subsequent formation of an interlayer dielectric layer.

[0153] Among them, since in the first device area 100H, the protective layer 400 also extends to cover part of the top of the isolation structure 120, the protective layer 401 can be at the bottom corner of the first gate structure 200 and the isolation structure 120, and the probability of the cleaning solution contacting the high-k gate dielectric layer 210 and the metal barrier layer 220 through the corner is low.

[0154] refer to Figure 11 After forming the protection layer 400 , the method further includes: forming an interlayer dielectric layer 500 on the substrate 100 at the side of the first gate structure 200 , wherein the interlayer dielectric layer 500 exposes the top of the first gate structure 200 located in the second device region 200L.

[0155] The interlayer dielectric layer 500 is used to isolate adjacent devices and also to provide a process platform for the subsequent formation of a metal gate structure.

[0156] The material of the interlayer dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0157] In this embodiment, the interlayer dielectric layer 500 is formed by sequentially performing a deposition process and a planarization process (eg, a chemical mechanical polishing process).

[0158] Specifically, during the planarization process of forming the interlayer dielectric layer 500 , the hard mask layer 300 located on top of the first gate structure 200 in the second device area 100L is removed to prepare for the subsequent removal of the first gate structure 200 in the second device area 100L.

[0159] In this embodiment, after forming the interlayer dielectric layer 500 , in the second device region 100L, the first gate structure 200 is removed, and a gate opening (not shown) is formed in the interlayer dielectric layer 500 ; and a second gate structure 600 is formed in the gate opening.

[0160] Removing the first gate structure 200 is used to prepare for the subsequent formation of a metal gate structure, wherein the gate opening is used to provide a space for forming the second gate structure 600 .

[0161] The second gate structure 600 is a device gate structure, which is used to control the opening and closing of the channel of the second device.

[0162] In this embodiment, the second gate structure 600 includes a metal gate structure.

[0163] The metal gate structure includes a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer.

[0164] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TaN, TiAl, Mo, MoN, AlN, and TiAlC.

[0165] The gate electrode layer is used to electrically lead out the metal gate structure. In this embodiment, the gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti or W.

[0166] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first device region, the first device region comprising a channel region and a source / drain region isolated from the channel region, an isolation structure formed in the substrate between the source / drain region and the channel region, wherein in the first device region, a substrate top surface of the channel region is lower than a substrate top surface of the source / drain region, and the isolation structure is used to achieve insulation between the channel region and the source / drain region; a gate oxide layer, located on the substrate in the channel region of the first device region; a first gate structure, located on the gate oxide layer, extending to the junction of the channel region substrate and the isolation structure and covering a portion of the top of the isolation structure; A protection layer covers the sidewalls of the first gate structure, and the protection layer also extends to cover a portion of the top of the isolation structure and exposes the base of the source and drain regions.

2. The semiconductor structure according to claim 1, wherein The substrate further includes a second device region, the second device region including an NMOS region and a PMOS region, wherein an operating voltage of the second device region is lower than an operating voltage of the first device region; The semiconductor structure further includes: a second gate structure located on the substrate of the second device region; a source / drain epitaxial layer, located in the substrate on both sides of the second gate structure of the PMOS region; Wherein, the protection layer also covers the sidewalls of the second gate structure.

3. The semiconductor structure according to claim 2, wherein: The second gate structure includes a metal gate structure.

4. The semiconductor structure according to claim 3, wherein: The semiconductor structure further includes: a high-k gate dielectric layer located between the first gate structure and the gate oxide layer, between the first gate structure and the isolation structure, and between the second gate structure and the substrate; a metal barrier layer, located between the first gate structure and the high-k gate dielectric layer, and between the second gate structure and the high-k dielectric layer; The protection layer also covers the sidewalls of the high-k gate dielectric layer and the metal barrier layer.

5. The semiconductor structure according to claim 1 or 2, wherein: The semiconductor structure further includes: a sidewall spacer located on a sidewall of the protective layer; The source and drain doping regions are located in the substrate where the sidewalls are exposed.

6. The semiconductor structure according to claim 2, wherein: The semiconductor structure further includes an interlayer dielectric layer located on the substrate and covering sidewalls of the first gate structure and the second gate structure, wherein the interlayer dielectric layer exposes a top of the second gate structure.

7. The semiconductor structure according to claim 1, wherein: The dimension of the protection layer extending to the top of the isolation structure is 30 nanometers to 60 nanometers.

8. The semiconductor structure according to claim 1, wherein: The material of the protective layer includes silicon nitride, silicon oxynitride, or a stacked structure of silicon oxide and silicon nitride.

9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, including a first device region, the first device region including a channel region and a source / drain region isolated from the channel region, an isolation structure formed in the substrate between the source / drain region and the channel region, wherein in the first device region, a top surface of the substrate in the channel region is lower than a top surface of the substrate in the source / drain region, and the isolation structure is used to achieve insulation between the channel region and the source / drain region; In the first device region, forming a gate oxide layer on the substrate surface of the channel region; forming a first gate structure on the gate oxide layer, wherein the first gate structure extends to the junction of the channel region substrate and the isolation structure and covers a portion of the top of the isolation structure; A protection layer is formed on the sidewalls of the first gate structure, and the protection layer also extends to cover a portion of the top of the isolation structure and exposes the base of the source and drain regions.

10. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the protective layer includes: forming a protective material layer on the substrate, wherein the protective material layer conformally covers the top of the substrate of the first device region and the top and sidewalls of the first gate structure; In the first device area, the protective material layer located on the top of the substrate of the source and drain area and the top of the partial isolation structure adjacent to the substrate of the source and drain area is removed, and the remaining protective material layer covering the top and side walls of the first gate structure and the partial isolation structure is retained as a protective layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing a substrate, the substrate further includes a second device region, the second device region includes an NMOS region and a PMOS region, wherein an operating voltage of the second device region is lower than an operating voltage of the first device region; In the step of forming the first gate structure, the first gate structure is further formed on the substrate of the second device region; In the step of forming the protective material layer, the protective material layer also covers the base of the second device region and the top and sidewalls of the first gate structure; After forming the protective material layer, the method further includes: performing a first patterning process on the protective material layer to remove the protective material layer located on the top of the first gate structure and the top of the substrate in the PMOS region; After the first patterning process, forming a source-drain epitaxial layer in the substrate on both sides of the first gate structure in the PMOS region; After forming the source and drain epitaxial layers, the method further includes: performing a second patterning process on the protective material layer to remove the protective material layer located on the top of the first gate structure and the top of the substrate in the NMOS region and the source and drain regions; During the second graphical treatment, the protective material layer located on the top of the substrate in the source and drain regions and on the top of the partial isolation structure adjacent to the substrate in the source and drain regions is removed, and the remaining protective material layer after the second graphical treatment serves as a protective layer.

12. The method for forming a semiconductor structure according to claim 9 or 11, wherein: After forming the protection layer, the method further includes: forming a sidewall covering the protection layer on the sidewall of the first gate structure; and performing source and drain implantation on the substrate exposed by the sidewall.

13. The method for forming a semiconductor structure according to claim 11, wherein: After forming the protection layer, the method further includes: forming an interlayer dielectric layer on the substrate at the side of the first gate structure, wherein the interlayer dielectric layer exposes the top of the first gate structure located in the second device area; In the second device region, the first gate structure is removed, a gate opening is formed in the interlayer dielectric layer, and a second gate structure is formed in the gate opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: The second gate structure includes a metal gate structure.

15. The method for forming a semiconductor structure according to claim 14, wherein: Before forming the first gate structure on the gate oxide layer, the method further includes: forming a high-k gate dielectric layer and a metal barrier layer on the high-k gate dielectric layer on the gate oxide layer, the isolation structure and the substrate of the second device region; In the step of forming the first gate structure, the first gate structure is formed on the metal barrier layer; Before forming the protection layer, the formation method further includes: removing the metal barrier layer and the high-k gate dielectric layer exposed by the first gate structure, wherein in the first device region, the high-k gate dielectric layer and the metal barrier layer extend to the junction of the channel region substrate and the isolation structure and cover a portion of the top of the isolation structure; In the step of forming a protection layer on the sidewalls of the first gate structure, the protection layer also covers the sidewalls of the high-k gate dielectric layer and the metal barrier layer.

16. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the protective material layer includes an atomic layer deposition process or a chemical vapor deposition process.

17. The method for forming a semiconductor structure according to claim 10, wherein: The process of removing the protective material layer located on the top of the substrate in the source / drain region and the top of a portion of the isolation structure adjacent to the substrate in the source / drain region includes a dry etching process.

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