Schottky diode devices with single-event burn-out resistance and their fabrication method

Abstract

This invention discloses a Schottky diode device with single-event burn-out resistance and its fabrication method, comprising: an N+ substrate layer; N-type multi-buffer layers of varying concentrations on the N+ substrate layer; a P-type region, including a P+ region and a P-buffer layer, the P-buffer layer being located below the P+ region; an N-type field-stop layer located below the P-buffer layer; an N-drift region, including a second N-drift region above the N-type field-stop layer and a first N-drift region above the N-type multi-buffer layers; and a trench located above the P+ region, the trench being filled with metal. Using the technical solution of this invention, when heavy ions are incident, the peak electric field, carrier collisional ionization rate, and transient current at the Schottky contact surface and the N- / N+ homojunction can be significantly reduced, thereby lowering the lattice temperature at the device surface and internally, and significantly improving the single-event burn-out safe operating area of ​​the device.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, and in particular relates to a single-particle burn-in-resistant structure for power semiconductor devices based on electric field modulation effect and its preparation method. Background Technology

[0002] Silicon carbide (SiC) possesses excellent electrical and thermal properties, including a wide bandgap, high critical breakdown electric field, and high thermal conductivity, making it a promising material for power semiconductor devices. Therefore, SiC Schottky diodes are well-suited for space power conversion applications. The junction barrier Schottky diode (JBS) of silicon carbide power semiconductor devices combines the low forward voltage of a Schottky barrier diode (SBD) with the low leakage current of a PiN diode, and is widely used in power management systems for power electronics, showing great development potential in the aerospace field.

[0003] However, research shows that SiC Schottky diodes are extremely sensitive to high-energy ion irradiation. If the reverse bias is high enough, it can lead to catastrophic single-event burn-in (SEB). When the device is in reverse bias, high-energy ion injection generates a large number of electron-hole pairs, thereby reducing the local resistivity, allowing for instantaneous high current flow, and generating Joule heating. Simultaneously, ion injection generates a high electric field at the Schottky interface, altering the electric field distribution in the drift region. The combination of a strong electric field and high conduction current density leads to increased power dissipation, causing the lattice temperature to rise above the sublimation temperature of SiC or the melting temperature of the metal / SiC interface, resulting in device leakage current degradation or catastrophic SEB. Summary of the Invention

[0004] The main objective of this invention is to propose a Schottky diode device structure and its fabrication method with resistance to single-particle burn-off, in order to solve the problem in the prior art where the highest temperature at the Schottky contact interface of the device exceeds the melting temperature of the metal and the internal temperature of the device exceeds the sublimation temperature of the SiC material after high-energy ion incident, thus causing catastrophic failure of the device due to single-particle burn-off.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A Schottky diode device structure with resistance to single-particle burn-out comprises two trenches formed at the anode of a semiconductor power device. The bottom of the trenches is formed by multiple ion implantations to form a P+ type region and a P- type buffer layer. An N-type field cutoff layer is disposed between the P- buffer layer and a first N-type drift region. A second N-type drift region is epitaxially formed on the N-type field cutoff layer. Multiple N-type buffer layers with different concentrations are disposed between the first N-type drift region and the N+ substrate.

[0007] Furthermore, the P+ type region has a depth of 0.6 μm, a width of 2 μm, and a doping concentration of 5 × 10⁻⁶. 18 cm -3 The P-type buffer layer has a depth of 0.2 μm, a width of 2 μm, and a doping concentration of 1 × 10⁻⁶. 17 cm -3 .

[0008] Furthermore, the trench has a depth of 2μm, a width of 2μm, and a distance of 2μm between adjacent trenches.

[0009] Furthermore, the N-type field stop layer has an epitaxial width of 8 μm, an overall epitaxial thickness of 0.4 μm, and a doping concentration of 1 × 10⁻⁶. 17 cm -3 .

[0010] Furthermore, the doping concentration of the first N-type drift region and the second N-type drift region is the same, both being 2 × 10⁻⁶. 15 cm -3 .

[0011] Furthermore, the N-type multi-buffer layer structure with different concentrations has an epitaxial width of 8 μm and an overall epitaxial thickness of 15 μm. It includes five sublayers with a thickness of 3 μm each, and the doping concentration of the sublayers increases progressively from top to bottom, with a doping range of 5.5 × 10⁻⁶. 16 cm -3 ~8.5×10 17 cm -3 .

[0012] This invention also provides a method for fabricating a Schottky diode device structure with resistance to single-event burn-out, comprising:

[0013] Step 1: Prepare the substrate area required for the Schottky diode device;

[0014] Step 2: An N-type multi-buffer layer structure with different concentrations is formed through multiple epitaxial layers in the substrate region;

[0015] Step 3: An N-type drift region is formed on the outer surface of the N-type multilayer buffer layer with different concentrations;

[0016] Step 4: An N-type field cutoff layer is formed above the first N-type drift region using epitaxial technology;

[0017] Step 5: Form a second N-type drift region above the N-type field cutoff layer using epitaxial technology;

[0018] Step 6: Use grooving technology to form a groove above the N-type drift region 1;

[0019] Step 7: Form a P-type buffer layer and a P+ type region at the bottom of the above trench through two ion implantations;

[0020] Step 8: Grow metal on the front and back sides of the device to complete the device fabrication.

[0021] The beneficial effects of this invention are:

[0022] This invention employs a two-stage ion implantation process after grooving to form a P+ region and a P- buffer layer. After high-energy particle incidence, this significantly shields the high electric field outside the Schottky interface, while simultaneously reducing the carrier collisional ionization rate at the Schottky interface, thereby lowering the transient current density. The lower transient current density reduces heat generation, resulting in a significant decrease in device surface temperature and preventing catastrophic device failure due to anode metal melting, thus improving the device's SEB resistance. Simultaneously, the P- buffer layer and N-type field cutoff layer reduce the thickness of the space charge region and the electron concentration at the interface, allowing the temperature at the interface to transfer to the device interior after high-energy particle incidence. Furthermore, the N-type multi-buffer layer structure significantly reduces the peak electric field and collisional ionization rate at the drift region and substrate homojunction, thus greatly reducing the lattice temperature at the homojunction. Subsequent simulations of devices with different power levels demonstrate that devices incorporating this structure exhibit a reduced probability of SEB occurrence at different incident locations, significantly improving SEB resistance reliability. Attached Figure Description

[0023] The following sections will describe some specific embodiments of this application in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0024] Figure 1 This is a schematic diagram of the cell structure of a traditional JBS diode device;

[0025] Figure 2 This is a schematic diagram of the cell structure of the trench JBS diode anti-single-event burn-off device based on the present invention;

[0026] Figures 3-9 yes Figure 2 The diagram shows the fabrication process of the trench JBS anti-single-event burn-off device.

[0027] Figure 10 yes Figure 1 The device temperature changes over time due to the single-event burn-out effect of the structure shown.

[0028] Figure 11 yes Figure 2 The device temperature changes over time due to the single-event burn-out effect of the structure shown.

[0029] Figure 12 yes Figure 1The structure shown and Figure 2 The structure shown has the Schottky contact interface temperature under different reverse bias voltages when particles are incident from the N-type region.

[0030] Specific implementation principle

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will now be described in detail with reference to the accompanying drawings.

[0032] like Figure 1 , 2 As shown, the present invention provides a Schottky diode device structure with resistance to single-event burn-out. Figure 2 and Figure 1 The structural difference is that, Figure 2 Multiple N-type buffer layers, N-type field-stop layers, P- buffer layers, and etching trenches of varying concentrations were added. Specifically, an N-type multilayer buffer layer structure was formed between the N+ substrate and the first N- drift region 2. The epitaxial width of the N-type multilayer buffer layer structure with varying concentrations was 8 μm, and the overall epitaxial thickness was 15 μm. It included five sublayers with a thickness of 3 μm each, and the doping concentration of the sublayers increased progressively from top to bottom, with a doping range of 5.5 × 10⁻⁶. 16 cm -3 ~8.5×10 17 cm -3 Trenches are formed by etching, and metal is filled into the trenches to form the device anode. The trenches are 2 μm deep, 2 μm wide, and 2 μm apart. A P+ region and a P- buffer layer are formed by two ion implantations. The P+ region is 0.6 μm deep, 2 μm wide, and has a doping concentration of 5 × 10⁻⁶. 18 cm -3 The P-type buffer layer has a depth of 0.2 μm, a width of 2 μm, and a doping concentration of 1 × 10⁻⁶. 17 cm -3 An N-type field stop layer is disposed between the P-buffer layer and the first N-drift region 2; the epitaxial width of the N-type field stop layer is 8 μm, the overall epitaxial thickness is 0.4 μm, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 A second N-type drift region is epitaxially formed above the N-type field cutoff layer; the doping concentration of the second N-type drift region 1 and the first N-type drift region 2 is the same, both being 2 × 10⁻⁶. 15 cm -3 .

[0033] Furthermore, the single-particle burn-in-resistant (SEB) hardened structure of the power device of this invention, formed by two ion implantations after grooving, creates a P+ region and a P- buffer layer. After high-energy particle injection, this structure significantly shields the high electric field outside the Schottky interface, while simultaneously greatly reducing the carrier collisional ionization rate at the Schottky interface, thereby lowering the transient current density. The lower transient current density reduces heat generation, significantly lowering the device surface temperature and preventing catastrophic failure due to anode metal melting, thus improving the device's SEB resistance. Simultaneously, the P- buffer layer and N-type field-stop layer reduce the thickness of the space charge region and the electron concentration at the interface, allowing the temperature at the interface to transfer to the device interior after high-energy particle injection. Therefore, the SEB-safe operating voltage of the device structure of this invention is significantly improved.

[0034] like Figure 3-9 As shown, the present invention also provides a method for fabricating a Schottky diode device structure with resistance to single-event burn-out, comprising:

[0035] Step 1: Prepare the substrate area required for the Schottky diode device;

[0036] Step 2: An N-type multi-buffer layer structure with different concentrations is formed through multiple epitaxial layers in the substrate region;

[0037] Step 3: An N-type drift region 2 is formed on the outer surface of the N-type multilayer buffer layer with different concentrations;

[0038] Step 4: An N-type field cutoff layer is formed above the N-type drift region 2 using epitaxial technology;

[0039] Step 5: Form an N-type drift region 1 above the N-type field cutoff layer using epitaxial technology;

[0040] Step 6: Use grooving technology to form a groove above the N-type drift region 1;

[0041] Step 7: Form a P-type buffer layer and a P+ type region at the bottom of the above trench through two ion implantations;

[0042] Step 8: Grow metal on the front and back sides of the device to complete the device fabrication.

[0043] The simulation verification method used below is only for... Figure 1 and Figure 2 The two structures shown are compared and discussed:

[0044] The traditional structure has a cell width of 8 μm and a drift region concentration of 2 × 10⁻⁶. 15 cm -3 The thickness of the P+ region is 0.8 μm; the cell width of the reinforced structure is 8 μm; and the concentrations of drift region 1 and drift region 2 are both 2 × 10⁻⁶.15 cm -3 .

[0045] During the simulation, the incident particle energy (linear energy transfer, LET) was chosen to be 0.5 pC / μm (for SiC material, 0.1 pC / μm = 15.1 MeV / mg / cm). 2 The particles were incident on both the N-type and P-type regions (the particles were incident perpendicularly and penetrated the entire device), with an incident trajectory radius of 0.05 μm and an initial charge generation time of 4 × 10⁻⁶. 12 s, the time width of the Gaussian distribution function is 2×10 12 s.

[0046] according to Figure 10 Simulation results show that when the LET value of the incident particle is 0.5 pC / μm, the reverse bias voltage of the device is 1000 V, and the particle is incident perpendicularly from above the N-type and P-type regions respectively. Figure 1 The highest lattice temperature of the device with this structure far exceeds 3100K, and thermal breakdown of the device leads to catastrophic failure.

[0047] Figure 11 Showing Figure 2 The simulation results are presented with an incident particle LET value of 0.5 pC / μm and a reverse bias voltage of 1000 V, simulating particle incidence from above the N-type and P-type regions. The simulation results show that the global maximum temperatures are 1989 K and 1973 K when the particle is incident vertically from above the N-type and P-type regions, respectively, and no thermal breakdown occurs.

[0048] according to Figure 12 Simulation results show that even with a high reverse bias, the temperature at the Schottky interface of the device in this invention remains relatively low, thus preventing the anode metal from melting and causing device failure. In contrast, the Schottky interface of a traditional JBS structure reaches a relatively high temperature even with a small reverse bias voltage. This is precisely because... Figure 2 The introduction of a trench structure significantly reduces the electric field and carrier collision ionization rate at the Schottky interface, thereby reducing the transient current density. The low transient current density reduces heat generation, which in turn significantly lowers the device surface temperature and significantly improves the device's SEB safe operating voltage.

[0049] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its essence and scope. It should be noted that the above descriptions are merely specific embodiments of this invention and do not limit the invention. Any adjustments and optimizations made within the spirit and principles of this invention are within the scope of the claims.

Claims

1. A Schottky diode device with single-event burn-out resistance, characterized in that, Two trenches are formed at the anode of the semiconductor power device. A P+ type region and a P- type buffer layer are formed at the bottom of the trenches through multiple ion implantations. An N-type field cutoff layer is set between the P- buffer layer and the first N-type drift region. A second N-type drift region is epitaxially formed on the N-type field cutoff layer. Multiple N-type buffer layers with different concentrations are set between the first N-type drift region and the N+ substrate.

2. The Schottky diode device with single-event burn-out resistance as described in claim 1, characterized in that, The P+ type region has a depth of 0.6 μm, a width of 2 μm, and a doping concentration of 5 × 10⁻⁶. 18 cm -3 The P-type buffer layer has a depth of 0.2 μm, a width of 2 μm, and a doping concentration of 1 × 10⁻⁶. 17 cm -3 .

3. The Schottky diode device with single-event burn-out resistance as described in claim 1, characterized in that, The trench has a depth of 2μm, a width of 2μm, and a distance of 2μm between adjacent trenches.

4. The Schottky diode device with single-event burn-out resistance as described in claim 1, characterized in that, The N-type field stop layer has an epitaxial width of 8 μm, an overall epitaxial thickness of 0.4 μm, and a doping concentration of 1 × 10⁻⁶. 17 cm -3 .

5. The Schottky diode device with single-event burn-out resistance as described in claim 1, characterized in that, The first N-type drift region and the second N-type drift region have the same doping concentration, both being 2 × 10⁻⁶. 15 cm -3 .

6. The Schottky diode device with single-event burn-out resistance as described in claim 1, characterized in that, The N-type multi-buffer layer structure with different concentrations has an epitaxial width of 8 μm and an overall epitaxial thickness of 15 μm. It includes five sublayers with a thickness of 3 μm each. The doping concentration of the sublayers increases from top to bottom, with a doping range of 5.5 × 10⁻⁶. 16 cm -3 ~8.5×10 17 cm -3 .

7. A method for fabricating a Schottky diode device with resistance to single-event burn-out, comprising: Step 1: Prepare the substrate area required for the Schottky diode device; Step 2: An N-type multi-buffer layer structure with different concentrations is formed through multiple epitaxial layers in the substrate region; Step 3: An N-type drift region is formed on the outer surface of the N-type multilayer buffer layer with different concentrations; Step 4: An N-type field cutoff layer is formed above the first N-type drift region using epitaxial technology; Step 5: Form a second N-type drift region above the N-type field cutoff layer using epitaxial technology; Step 6: Use grooving technology to form a groove above the N-type drift region 1; Step 7: Form a P-type buffer layer and a P+ type region at the bottom of the above trench through two ion implantations; Step 8: Grow metal on the front and back sides of the device to complete the device fabrication.

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