System physical address size aware cache memory

Abstract

In certain aspects, a tag memory (200) includes: a plurality of non-configurable tag columns (204) configured to be powered on during normal operation; and a plurality of configurable tag columns (202), wherein a first portion of the plurality of configurable tag columns is configured to be powered off during normal operation and a second portion of the plurality of configurable tag columns is configured to be powered on during normal operation.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. Patent Application No. 16 / 799,936, filed on February 25, 2020, entitled “SYSTEM PHYSICAL ADDRESS SIZEAWARE CACHE MEMORY,” the entire contents of which are incorporated herein. Background Art

[0003] Aspects of the present disclosure relate to cache memory, and more particularly, to configurable cache tag memory for power optimization.

[0004] Cache memory is a special type of high-speed memory. It is used to speed up and synchronize with high-speed CPUs. Cache memory is an extremely fast type of memory that acts as a buffer between the main memory (usually DDR or LPDDR memory) and the CPU. The cache holds frequently requested data and instructions, making them immediately available to the CPU when they are needed. Most CPUs have different independent caches, including instruction cache and data cache, where they are usually organized into a hierarchy of more cache levels (L1, L2, L3, L4, etc.).

[0005] Data is transferred between memory and cache in fixed-size blocks called cache lines or cache blocks. When a cache line is copied from memory into cache, a cache entry is created. The cache entry will include the copied data as well as the requested memory location called a tag. The tag contains the partial address of the actual data fetched from main memory. The effective memory address that accompanies the cache line is divided (from MSB to LSB) into a tag, index, and block offset. The index describes which cache set the data has been placed into. The block offset specifies the desired data within the storage data block within the cache line. The tag contains the most significant bits of the address, which are checked against all ways in the current set (which has been retrieved via the index) to see if that set contains the requested address. If so, a cache hit occurs.

[0006] Figure 1 An example memory address map according to certain aspects of the present disclosure is shown. Address 100 is for a 32KB cache with 4-way set associativity, 64-byte block size, 40-bit physical address. The offset of the 64-byte block has 6 bits (5:0). There are 512 cache blocks and 128 sets, so there are 128 indexes, requiring 7 bits (12:6). The remaining bits (39:13) are the tag field.

[0007] In computing, a physical address is a memory address represented as a binary number on an address bus circuit to enable the data bus to access a specific location of main memory or a register of a memory-mapped I / O device. The physical address space is the total number of physical addresses (memory locations) that are uniquely addressable at the physical level (i.e., in RAM). The maximum size of physical memory is limited by the width of the address bus. A computing device with 36-bit physical addresses can support up to 64GB of main memory.

[0008] However, the actual physical address size used is usually smaller. The actual physical address size depends on the main memory density and the peripheral device address mapping. For example, a processing unit in a system on a chip (SoC) can support physical addresses of up to 40 bits, which means that it can support up to 1TB of main memory. However, a device incorporated into the SoC may have 4GB of DDR. Therefore, only the lower 32 bits of the physical address are used. The signals at the upper 8 bits are not related to memory reads or writes. The power consumption caused by switching these bits is therefore wasted. In addition, the power consumption of the circuits used to derive these signals and subsequently process them is also wasted. Therefore, it is beneficial to reduce the power consumption of unused tag bits in cache memory. Summary of the invention

[0009] A brief overview of one or more implementations is given below to provide a basic understanding of these implementations. This content is not an extensive overview of all contemplated implementations, and is neither intended to identify key or important elements of all implementations nor to describe the scope of any or all implementations. The sole purpose of this content is to present concepts related to one or more implementations in a simplified form as a prelude to a more detailed description that will be given later.

[0010] In one aspect, a tag memory includes: a plurality of non-configurable tag columns configured to be powered on during normal operation; and a plurality of configurable tag columns, wherein a first portion of the plurality of configurable tag columns is configured to be powered off during normal operation, and a second portion of the plurality of configurable tag columns is configured to be powered on during normal operation.

[0011] In another aspect, a method for operating a tag memory includes: powering up a plurality of non-configurable tag columns during normal operation; powering down a first portion of a plurality of configurable tag columns during normal operation; and powering up a second portion of the plurality of configurable tag columns during normal operation.

[0012] To achieve the foregoing and related purposes, one or more implementations include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative aspects of one or more implementations. However, these aspects are merely indicative of some of the various ways in which the principles of various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example memory address map is shown in accordance with certain aspects of the present disclosure.

[0014] Figure 2 An exemplary tag memory according to certain aspects of the present disclosure is shown.

[0015] Figure 3 An exemplary cache tag comparison in accordance with certain aspects of the present disclosure is shown.

[0016] Figure 4 An exemplary bit comparator according to certain aspects of the present disclosure is shown.

[0017] Figure 5 An exemplary method of operating a tag memory according to certain aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0018] The detailed description set forth below in conjunction with the accompanying drawings is intended to describe various aspects, rather than merely represent aspects in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing an understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid confusion with these concepts.

[0019] The processing units in the SoC (such as general-purpose CPUs or DSPs) provide support for a maximum physical address size. A system integrating the SoC may have a system memory physical address size that is smaller than the maximum physical address supported by the SoC. Storing unused physical address bits in tag RAM at all cache levels in the SoC wastes a lot of energy and power. Even if the page table configuration can ensure that there will be no switching on higher unused physical address bits, dynamic (clock) power and leakage power will be wasted for these bits and their associated circuits. Therefore, it is beneficial to make these bits configurable to save dynamic power and leakage power.

[0020] Figure 2An exemplary tag memory according to certain aspects of the present disclosure is shown. The tag memory 200 includes two components. The first component 202 includes a plurality of configurable tag columns 202A, 202B, ..., 202M for the upper bits of the tag physical address. The second component 204 includes a plurality of non-configurable tag columns 204A, 204B, ..., 204N for the lower bits of the tag physical address. In addition, the tag memory 200 includes a plurality of configurable power switches 206 for the first component 202 and a plurality of non-configurable power switches 208 for the second component 204. Each configurable tag column of the tag memory 200 has a power switch, such as a power switch 206A for the tag column 202A, a power switch 206B for the tag column 202B, ..., and a power switch 206M for the tag column 202M. Each non-configurable tag column of tag memory 200 may also have a power switch, such as power switch 208A for tag column 204A, power switch 208B for tag column 204B, ..., and power switch 208N for tag column 204N. Power switches 206 and 208 couple the supply power VDD to each tag column 202A, 202B, ..., 202M and 204A, 204B, ..., 204N. For illustrative purposes, power switch 206 and power switch 208 are each represented by a PMOS transistor. A "0" logic gate signal turns on the power switch, and a "1" logic gate signal turns off the power switch. Other devices for selecting tag columns are also possible.

[0021] The first component 202 includes the most significant bits of the tag that may not be used by the system memory. These bits are configurable. For example, if the SoC supports 40-bit physical addresses and it is determined that the system can have system memory with a physical address size as small as 32 bits, the 8 most significant bits can be set to be configurable. If the system memory physical address size is 32 bits, all 8 most significant bits [39:32] will be configured to be powered off during normal operation. If the system memory physical address size is 36 bits, the 4 most significant bits [39:36] are configured to be powered off during normal operation, and the next 4 bits [35:32] are configured to be powered on during normal operation. The remaining tag bits [31:13] of the tag field (assuming a 27-bit tag for illustration purposes only) are always powered on during normal operation.

[0022] Therefore, the plurality of configurable tag columns in the first component 202 can be further divided into two parts: the first part of the plurality of configurable tag columns are the most significant bits of the tag, and the second part of the plurality of configurable tag columns are the remaining bits in the first component 202. The bits of the first part of the plurality of configurable tag columns are not part of the system memory physical address and can be powered off during normal operation. However, the second part of the plurality of configurable tag columns are part of the system memory physical address and should be powered on during normal operation.

[0023] The configuration of the power state of the plurality of configurable tag columns 202A, 202B, ..., 202M is performed by controlling the plurality of configurable power switches 206A, 206B, ..., 206M. For the first portion of the plurality of configurable tag columns, i.e., those most significant tag bits that are not part of the system memory physical address, the corresponding power switches will be turned off, thereby decoupling the supply power VDD from the tag columns during normal operation and during power crashes. Thus, significant power savings, including leakage power savings, are achieved. For example, for an SoC supporting 40-bit physical addresses, if the system memory only requires 36-bit physical addresses, the 4 most significant bit tag columns can be powered off by turning off the corresponding power switches.

[0024] In order to selectively turn on or off multiple configurable power switches 206A, 206B, ..., 206M, the control terminals of the multiple configurable power switches 206A, 206B, ..., 206M are coupled to corresponding switch control signals in multiple switch control signals S1, S2, ..., Sm. Multiple switch control signals S1, S2, ..., Sm are provided by the configuration circuit 210. As an example embodiment, the configuration circuit 210 includes a decoder 220. The decoder 220 receives the configuration bit as input and outputs the decoded switch control signals S1, S2, ..., Sm. For example, if there are 3 configuration bits, there may be 8 switch control signals S1, S2, ..., Sm. Other decoding schemes are possible. For example, a mapping table may be provided and implemented between the configuration bit and the control signal. The mapping table may be programmable.

[0025] Configuration bits can be programmed and reside in registers. Alternatively, configuration bits can be obtained from IO pins. IO pins are coupled to power supplies or ground to set the logic value of configuration bits. IO pin configuration provides system designers with flexibility to set configuration bits until the system memory size is determined. Configuration bits can be programmed once, such as by eFuse, EEPROM, etc. Other means can also define configuration bits. Configuration bits can be set by security software during startup and will not change until the next reset cycle. This is to ensure that these bits do not change during mission mode operation. In addition, these bits should be programmed even before enabling caches and MMUs.

[0026] For a cache that can collapse power, the configuration circuit 210 also receives a power-off control signal Sleep. When the power collapses, the power-off control signal Sleep is asserted (Sleep = "1"), and the tag memory 200 is powered off by turning off all power switches 206A, 206B, ..., 206M and 208A, 208B, ..., 208N. For a PMOS transistor power switch, a complementary power-off control signal can be generated by an inverter 212. Complementary power-off control signal is also provided to the configuration circuit 210, wherein a complementary power-down control signal is coupled to each of the decoded signals (eg, via Figure 2 , 208N are disconnected. When the power-off control signal Sleep is de-asserted (logical "0"), only a few of the most significant bit column power switches are disconnected. That is, only the first part of the plurality of configurable power switches (i.e., the configurable power switches coupled to the first part of the plurality of configurable tag columns) is disconnected. The other power switches are turned on to supply power to each column. Those power switches include the second part of the plurality of configurable power switches (i.e., the configurable power switches coupled to the second part of the plurality of configurable tag columns) and the third part of the plurality of non-configurable power switches (if any, i.e., the non-configurable power switches coupled to the plurality of non-configurable tag columns). The number of the most significant bit tag columns to be disconnected depends on the configuration bits and the decoding scheme.

[0027] To ensure correct subsequent operation when the unused physical address bit tag columns are powered off by the power switch, in an exemplary embodiment, clamp logic 214 may be added at the output of the plurality of configurable tag columns 202. The clamp logic 214 receives the switch control signals S1, S2, ..., Sm, and gates the outputs of the plurality of configurable tag columns 202A, 202B, ..., 202M using, for example, an AND logic operation. For example, the switch control signal S1 gates the output of the configurable tag column 202A, the switch control signal S2 gates the output of the configurable tag column 202B, ..., and the switch control signal Sm gates the output of the configurable tag column 202M. The clamp logic 214 is configured to pass each output of the second portion of the plurality of configurable tag columns and pass a fixed logic value for each output of the first portion of the plurality of configurable tag columns by, for example, AND logic gating during normal operation. The strobe outputs of the configurable tag columns 202A, 202B, . . . , 202M and the outputs of the non-configurable columns 204A, 204B, . . . , 204N form the tag bits 216 that are read out.

[0028] When there are unused most significant bits in the tag, subsequent comparisons against those bits to determine a cache hit or miss are unnecessary and can be disabled, further saving power. Figure 3 An exemplary cache tag comparison according to certain aspects of the present disclosure is shown. The cache tag system 300 includes a K-way cache Way 0, Way 1, ..., Way K. In each way, there are a plurality of non-configurable tag columns 304C for non-configurable bits, a second portion 304B of a plurality of configurable tag columns for used configurable bits, and a first portion 304A of a plurality of configurable tag columns for unused configurable bits. For example, if the SoC supports 40-bit physical addresses, and it is determined that the system can have a system memory with a physical address size as small as 32 bits, the tag columns for the 8 most significant bits can be set to configurable. If the system memory physical address size is 37 bits, the tag columns for the 3 most significant bits [39:37] are unused configurable bits and can be powered off during normal operation, while the tag columns for the next 5 bits [36:32] are used configurable bits and are powered on during normal operation. The tag columns used for the remaining bits [31:13] of the tag field (assuming a 27-bit tag for illustration purposes only) are not configurable and are always powered up during normal operation.

[0029] The tag system 300 also includes a register 302 containing a memory address. For an SoC that supports a 40-bit physical address, the address will be at least 40 bits long. The memory address contains an offset, an index, and a tag. The memory tag may include three parts: a non-configurable bit 314C, a used configurable bit 314B, and an unused configurable bit 314A. The memory tag bits 314A, 314B, and 314C are compared with the tag bits read from the tag columns 304A, 304B, and 304C in each way by a tag comparator 306. For configurable bits, switch control signals S1, S2, and Sm can turn on or off the comparison through a signal line 318. The switch control signals S1, S2, ..., Sm are signals generated by the configuration circuit 210. If the configurable tag bits are unused, the comparison is unnecessary and will not be performed, and the default result will be a match for these bits. If the configurable tag bits are used, the comparison will be enabled like those non-configurable bits.

[0030] Figure 4 An exemplary bit comparator according to certain aspects of the present disclosure is shown. The tag comparator 306 includes a plurality of bit comparators 400 for configurable tag bits. The bit comparator 400 includes an exclusive OR circuit XNOR402 having two comparison bits A and B. XNOR 402 is coupled to a power supply VDD through a head switch P1 and is coupled to ground through a foot switch N1. The foot switch N1 and the head switch PI are controlled by a complementary enable signal EN and its inversion (e.g., inverted by an inverter 404). In addition, when the enable signal EN is disconnected (off), the comparison output O is maintained as a logic high by the retainer P2. Applying the bit comparator 400 in the tag comparator 306, the two comparison bits A and B can be coupled to the configurable tag bits 314A and 314B of the memory tag and the corresponding configurable tag bits read from the configurable tag columns 304A and 304B. The enable signal EN is coupled to the corresponding switch control signals S1, S2, ..., Sm.

[0031] Figure 5An exemplary method 500 of operating a tag memory according to certain aspects of the present disclosure is shown. In normal operation, at 502, a plurality of non-configurable tag columns (e.g., a plurality of non-configurable tag columns 204A, 204B, ..., 204N, or 304C) are powered up. At the same time, a first portion of a plurality of configurable tag columns (e.g., a first portion of a plurality of configurable tag columns 202A, 202B, ..., 202M, or 304A) is powered down, and a second portion of a plurality of configurable tag columns (e.g., a second portion of a plurality of configurable tag columns 202A, 202B, 202M, or 304B) is powered up. The first portion of the plurality of configurable tag columns contains the most significant bits of a physical address, and the second portion of the plurality of configurable tag columns contains the second most significant bits of the physical address. The system memory may not use the full size of the physical address available to the SoC. Therefore, a portion of the most significant bits of the physical address may not be needed. Related circuits may be disconnected to save power consumption.

[0032] Power on or off can be controlled by multiple power switches. The tag memory includes multiple configurable power switches (e.g., multiple configurable power switches 206A, 206B, ..., 206M) coupled to multiple configurable tag columns, wherein each of the multiple configurable tag columns is coupled to a supply power source (e.g., supply power source VDD) through a corresponding configurable power switch in the multiple configurable power switches, and each of the multiple configurable tag columns is configured to be turned on or off by turning on or off a corresponding configurable power switch in the multiple configurable power switches. In addition, the tag memory includes multiple non-configurable power switches (e.g., multiple non-configurable power switches 208A, 208B, ..., 208N) coupled to multiple non-configurable tag columns.

[0033] Control signals for the plurality of configurable power switches may be generated by a configuration circuit (e.g., configuration circuit 210). This is performed at 504, where a plurality of switch control signals (e.g., a plurality of switch control signals S1, S2, ..., Sm) are generated, each switch control signal being coupled to a corresponding configurable power switch in the plurality of configurable power switches. Each of the plurality of switch control signals controls the turning on or off of a corresponding configurable power switch in the plurality of configurable power switches.

[0034] In a power collapse event, method 500 may power off the plurality of non-configurable tag columns, the first portion of the plurality of configurable tag columns, and the second portion of the plurality of configurable tag columns at 506 .

[0035] At 508 , method 500 may also maintain outputs of the first portion of the plurality of configurable columns at fixed logic values ​​during normal operation so that subsequent circuitry will not operate unstably.

[0036] The foregoing description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A tag memory, comprising: a plurality of non-configurable tag columns configured to be powered up during normal operation; as well as a plurality of configurable tag columns, wherein a first portion of the plurality of configurable tag columns are configured to be powered off during the normal operation and a second portion of the plurality of configurable tag columns are configured to be powered on during the normal operation, wherein the first portion of the plurality of configurable tag columns comprises most significant bits of a physical address, and the second portion of the plurality of configurable tag columns comprises second most significant bits of the physical address, The plurality of non-configurable tag columns include remaining bits of the tag field.

2. The tag memory according to claim 1, further comprising a plurality of configurable power switches coupled to the plurality of configurable tag columns, wherein each of the plurality of configurable tag columns is coupled to a supply power source through a corresponding configurable power switch among the plurality of configurable power switches, and each of the plurality of configurable tag columns is configured to be powered on or powered off by turning on or off the corresponding configurable power switch among the plurality of configurable power switches. 3 . The tag memory of claim 2 , wherein each of the plurality of configurable power switches comprises a PMOS transistor.

4. The tag memory according to claim 2, further comprising a configuration circuit configured to provide a plurality of switch control signals, each switch control signal being coupled to the corresponding configurable power switch among the plurality of configurable power switches, wherein each of the plurality of switch control signals controls turning on or off the corresponding configurable power switch among the plurality of configurable power switches. 5 . The tag memory according to claim 4 , wherein the configuration circuit comprises a decoder to generate the plurality of switch control signals according to configuration bits.

6. The tag memory of claim 5, wherein the configuration bits reside in registers.

7. The tag memory of claim 5, wherein the configuration bit is configured to be set during startup.

8. The tag memory of claim 1 , further comprising a plurality of non-configurable power switches coupled to the plurality of non-configurable tag columns, wherein each non-configurable tag column of the plurality of non-configurable tag columns is coupled to a supply power source through a corresponding non-configurable power switch of the plurality of non-configurable power switches. 9 . The tag memory of claim 8 , wherein the plurality of non-configurable tag columns are configured to be powered up during the normal operation and powered down during a power collapse by the plurality of non-configurable power switches.

10. The tag memory of claim 9, wherein the first portion of the plurality of configurable tag columns is configured to be powered off during the normal operation, and the second portion of the plurality of configurable tag columns is configured to be powered on during the normal operation, and wherein both the first portion and the second portion of the plurality of configurable tag columns are configured to be powered off during the power collapse.

11. The tag memory of claim 1 , further comprising clamping logic coupled to outputs of the plurality of configurable tag columns, wherein the clamping logic is configured to pass each output of the second portion of the plurality of configurable tag columns and pass a fixed logic value for each output of the first portion of the plurality of configuration tag columns.

12. The tag memory of claim 11, wherein the clamping logic comprises a plurality of 2-input AND logic gates, wherein each of the plurality of 2-input AND logic gates receives one output of the plurality of configurable tag columns and a corresponding switch control signal.

13. The tag memory of claim 1 , further comprising a first plurality of bit comparators, each of the first plurality of bit comparators being coupled to each output of the first portion of the plurality of configurable tag columns, wherein the first plurality of bit comparators are configured to be powered down during the normal operation.

14. The tag memory of claim 13 , further comprising a second plurality of bit comparators and a third plurality of bit comparators, wherein the second plurality of bit comparators are each coupled to each output of the second portion of the plurality of configurable tag columns, and the third plurality of bit comparators are each coupled to each output of the plurality of non-configurable tag columns, wherein the second plurality of bit comparators and the third plurality of bit comparators are configured to be powered on during the normal operation.

15. The tag memory according to claim 1, wherein the tag memory is a part of a first-level cache.

16. A method for operating a tag memory, comprising: Powering up multiple non-configurable tag columns during normal operation; de-energizing a first portion of the plurality of configurable tag columns during said normal operation; as well as powering up a second portion of the plurality of configurable tag columns during the normal operation, wherein the first portion of the plurality of configurable tag columns comprises most significant bits of a physical address, and the second portion of the plurality of configurable tag columns comprises second most significant bits of the physical address, The plurality of non-configurable tag columns include remaining bits of the tag field.

17. The method of claim 16, wherein the tag memory comprises a plurality of configurable power switches coupled to the plurality of configurable tag columns, wherein each of the plurality of configurable tag columns is coupled to a power supply through a corresponding configurable power switch of the plurality of configurable power switches, and each of the plurality of configurable tag columns is configured to be powered on or off by turning on or off the corresponding configurable power switch of the plurality of configurable power switches.

18. The method of claim 17 , further comprising generating a plurality of switch control signals, each switch control signal being coupled to the corresponding configurable power switch among the plurality of configurable power switches, wherein each switch control signal among the plurality of switch control signals controls turning on or off the corresponding configurable power switch among the plurality of configurable power switches.

19. The method of claim 16, further comprising powering off the plurality of non-configurable tag columns, the first portion of the plurality of configurable tag columns, and the second portion of the plurality of configurable tag columns during a power collapse.

20. The method of claim 16, further comprising maintaining outputs of the first portion of the plurality of configurable columns at fixed logic values ​​during the normal operation.

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