Video processor, video processing method, display control system and electronic device

Abstract

A video processor, a video processing method, a display control system and an electronic device. The video processor comprises a receiving module, a preprocessing module, a picture quality processing module, a post-processing module and a video output module, so that the video receiving, video preprocessing, video picture quality processing, video post-processing and video output functions can be integrated in one system. Compared with the distributed system, the integrated video processor reduces the connection and data interaction between the processing cores, improves the system stability, and reduces the influence of power consumption and electromagnetic compatibility problems on the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display control, and in particular to a video processor, a video processing method, a display control system and an electronic device. BACKGROUND

[0002] 4K resolution belongs to ultra-high definition resolution, under which resolution, the audience can see every detail and close-up in the picture. At present, in a monitoring level system, since the function and performance requirements of the monitoring system are very high, the monitoring system usually adopts a display with 4K resolution. However, the traditional monitoring system usually adopts a distributed system when processing 4K input video data, and the connection relationship between each subsystem is complex, and the data interaction is much, which leads to unstable system. SUMMARY

[0003] The present application aims to at least solve one of the technical problems in the related art. To this end, a first object of the present application is to provide a video processor with high stability.

[0004] A second object of the present application is to provide a display control system.

[0005] A third object of the present application is to provide a video processing method.

[0006] A fourth object of the present application is to provide a computer readable storage medium.

[0007] A fifth object of the present application is to provide an electronic device.

[0008] To achieve the above-mentioned objects, the first aspect of the present application provides a video processor, comprising:

[0009] a receiving module configured to receive source video display data with different communication protocols through at least one input interface, and parse the source video display data with different communication protocols into effective video display data;

[0010] a preprocessing module connected to the receiving module, the preprocessing module being configured to preprocess the video format of the effective video display data to generate effective video display data with a preset video format;

[0011] a picture quality processing module connected to the preprocessing module, the picture quality processing module being configured to adjust the picture quality parameters in the effective video display data with the preset video format to output a first video picture;

[0012] The post-processing module is connected with the pre-processing module and the picture processing module, and is configured to extract video parameters of the effective video display data, generate the superimposed picture according to the video parameters, and superimpose the superimposed picture to the first video picture.

[0013] The video output module is connected with the post-processing module, and is configured to perform data format conversion on the effective video display data of the first video picture and the effective video display data of the superimposed picture, encapsulate the output video display data, and output the output video display data to an external display through a video output interface, so as to superimpose and display the superimposed picture on the first video picture.

[0014] According to the video processor provided by the embodiment of the present application, the video receiving, the video pre-processing, the video picture processing, the video post-processing and the video output can be integrated in one system through the cooperation of the receiving module, the pre-processing module, the picture processing module, the post-processing module and the video output module, compared with the distributed system, the integrated video processor reduces the connection and data interaction between the processing cores, improves the system stability, and reduces the influence of the power consumption and the electromagnetic compatibility problem on the system. In addition, the video processor further comprises at least one input interface, can receive the source video display data with different communication protocols, and process and output the source video display data with different communication protocols to the external display for display, thereby improving the compatibility of the video processor.

[0015] To achieve the above object, the second aspect of the present application provides a display control system comprising the video processor, and the display control system further comprises a controller configured to control the video processor to process the received source video display data and output the processed video display data to a display.

[0016] According to the display control system provided by the embodiment of the present application, the video receiving, the video pre-processing, the video picture processing, the video post-processing and the video output can be integrated in one system through the cooperation of the video processor, compared with the distributed system, the integrated video processor reduces the connection and data interaction between the processing cores, improves the system stability, and reduces the influence of the power consumption and the electromagnetic compatibility problem on the system. In addition, the video processor further comprises at least one input interface, can receive the source video display data with different communication protocols, and process and output the source video display data with different communication protocols to the external display for display, thereby improving the compatibility of the video processor.

[0017] To achieve the above object, the third aspect of the present application provides a video processing method, comprising:

[0018] receive source video display data with different communication protocols through at least one input interface, and parse the source video display data with different communication protocols into valid video display data;

[0019] pre-process a video format of the valid video display data to generate valid video display data with a preset video format;

[0020] adjust a quality parameter in the valid video display data with the preset video format to output a first video picture;

[0021] extract a video parameter of the valid video display data, generate an overlay picture according to the video parameter, and overlay the overlay picture to the first video picture;

[0022] perform data format conversion on the valid video display data of the first video picture and the valid video display data of the overlay picture to encapsulate into output video display data, and output the output video display data to an external display through a video output interface, so as to display the overlay picture overlaid to the first video picture.

[0023] According to the video processing method, the source video display data with different communication protocols is parsed into valid video display data, the video format of the valid video display data is pre-processed to generate valid video display data with a preset video format, the quality parameter in the valid video display data with the preset video format is adjusted to output a first video picture, the video parameter of the valid video display data is extracted, an overlay picture is generated according to the video parameter, and the overlay picture is overlaid to the first video picture, data format conversion is performed on the valid video display data of the first video picture and the valid video display data of the overlay picture to encapsulate into output video display data, and the output video display data is output to an external display through a video output interface, so as to display the overlay picture overlaid to the first video picture. Thus, video receiving, video pre-processing, video quality processing, video post-processing and video output and other functions can be integrated in one system, the connection and data interaction between processing cores are reduced, the system stability is improved, and the influence of power consumption and electromagnetic compatibility on the system is reduced. Moreover, the source video display data with different communication protocols is received through at least one input interface, and the source video display data with different communication protocols is processed and output to an external display for display, so that the data compatibility is improved.

[0024] To achieve the above object, the fourth aspect of the present application provides a computer readable storage medium, which stores a video processing program, and the video processing program is executed by a processor to implement the above video processing method.

[0025] According to the video processing method, the video receiving, video preprocessing, video quality processing, video post-processing and video output and the like can be integrated in one system, the connection and data interaction between processing cores are reduced, the system stability is improved, and the influence of power consumption and electromagnetic compatibility problems on the system is reduced. The source video display data with different communication protocols can be received through the at least one input interface, and the source video display data with different communication protocols is processed and output to an external display for display, and the data compatibility is improved.

[0026] To achieve the above object, the fifth aspect of the present application provides an electronic device, comprising a memory, a processor and a video processing program stored in the memory and executable on the processor, when the processor executes the video processing program, the above-mentioned video processing method is realized.

[0027] According to the electronic device, the video receiving, video preprocessing, video quality processing, video post-processing and video output and the like can be integrated in one system, the connection and data interaction between processing cores are reduced, the system stability is improved, and the influence of power consumption and electromagnetic compatibility problems on the system is reduced. The source video display data with different communication protocols can be received through the at least one input interface, and the source video display data with different communication protocols is processed and output to an external display for display, and the data compatibility is improved.

[0028] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 The structure schematic diagram of the video processor according to one embodiment of the present application;

[0030] Figure 2 The hardware interface structure schematic diagram of the video processor according to the embodiment of the present application;

[0031] Figure 3 The structure schematic diagram of the video processor according to another embodiment of the present application;

[0032] Figure 4 The resolution conversion mode schematic diagram according to one embodiment of the present application;

[0033] Figure 5 The resolution conversion mode schematic diagram according to another embodiment of the present application;

[0034] Figure 6Fig. 2 is a schematic diagram of a scan mode conversion method according to an embodiment of the present application;

[0035] Figure 7 Fig. 3 is a schematic diagram of a scan mode conversion method according to another embodiment of the present application;

[0036] Figure 8 Fig. 4 is a schematic diagram of a scan mode conversion method according to yet another embodiment of the present application;

[0037] Figure 9 Fig. 5 is a schematic diagram of a quad display method according to an embodiment of the present application;

[0038] Figure 10 Fig. 6 is a schematic diagram of a display system structure according to an embodiment of the present application;

[0039] Figure 11 Fig. 7 is a flowchart of a video processing method according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] Embodiments of the present application are described in detail below with reference to the accompanying drawings. The same or similar components are denoted by the same or similar reference numerals throughout the drawings, and repeated description thereof is omitted. The embodiments described below are exemplary and are intended to explain the present application, and are not to be understood as limiting the present application.

[0041] A video processor, a display control system, a video processing method, a computer readable storage medium and an electronic device according to embodiments of the present application are described below with reference to the accompanying drawings.

[0042] Reference Figure 1As shown, in the present application, the video processor includes a receiving module 110, a preprocessing module 120, a picture processing module 130, a post-processing module 140 and a video output module 150. Among them, the receiving module 110 is used to receive source video display data with different communication protocols through at least one input interface, and parse the source video display data with different communication protocols into valid video display data. The preprocessing module 120 is connected with the receiving module 110, and is used to preprocess the video format of the valid video display data to generate valid video display data with a preset video format. The picture processing module 130 is connected with the preprocessing module 120, and is used to adjust the picture quality parameters in the valid video display data with the preset video format to output a first video picture. The post-processing module 140 is connected with the preprocessing module 120 and the picture processing module 130, and is used to extract the video parameters of the valid video display data, and generate a superimposed picture according to the video parameters, and superimpose the superimposed picture to the first video picture. The video output module 150 is connected with the post-processing module 140, and is used to perform data format conversion on the valid video display data of the first video picture and the valid video display data of the superimposed picture, to encapsulate into output video display data, and output the output video display data to an external display through a video output interface, so as to superimpose the superimposed picture on the first video picture for display.

[0043] Specifically, in the present application, the video processor can be FPGA (Field Programmable Gate Array, programmable logic array). The FPGA has a large parallelism, multiple modules in the FPGA can simultaneously and independently perform calculation, has a high processing speed, and can allocate internal resources according to needs to complete different logical functions. The video processor is used to process the received video signal and output to the 4K display connected in the rear stage. Among them, the 4K display is a super high definition display, and the pixel resolution can reach 4096*2160, which can be used in monitoring systems or other display scenarios with high requirements for display picture accuracy.

[0044] The video processor can include a plurality of input interfaces for receiving source video display data having different communication protocols, and the receiving module 110 includes a plurality of receiving units, each of which corresponds to a type of input interface and is configured to parse the source video display data having different communication protocols into effective video display data that can be processed by the video processor. It can be understood that the data formats of the effective video display data parsed from the source video display data received by different input interfaces are the same, but the specific display contents can be different. The preprocessing module 120 is configured to receive the effective video display data and process the video format of the effective video display data to convert the effective video display data into effective video display data having a preset video format so as to adapt to the display connected in the subsequent stage. The video format can include resolution, scanning mode, frame rate, color format, color bit depth, etc. After the preprocessing module 120 converts the video format of the effective video display data into the preset video format, the quality processing module 130 adjusts the quality parameters in the effective video display data having the preset video format to output a first video picture, wherein the quality parameters can include tone, chroma, contrast, brightness, color temperature, color gamut, GAMMA correction parameter, color space conversion parameter, etc. The post-processing module 140 is configured to read the effective video display data from the preprocessing module 120 and extract video parameters from the effective video display data, and can generate an overlay picture according to the video parameters. The video output module 150 performs data format conversion on the effective video display data of the first video picture and the effective video display data of the overlay picture to encapsulate the output video display data, so that the external display processes the output video display data, and then the overlay picture can be superimposed on the first video picture for display.

[0045] The video processor provided by the above embodiments includes a receiving module, a preprocessing module, a quality processing module, a post-processing module, and a video output module, so that various functions such as video receiving, video preprocessing, video quality processing, video post-processing, and video output can be integrated in one system. Compared with a distributed system, the integrated video processor reduces the connection and data interaction between processing cores, improves system stability, and can reduce the impact of power consumption and electromagnetic compatibility problems on the system. Moreover, the video processor further includes at least one input interface, which can receive source video display data having different communication protocols and process the source video display data having different communication protocols to output to an external display for display, thereby improving the compatibility of the video processor.

[0046] In one of the embodiments, as Figure 2As shown, the first input interface module 160, the second input interface 162, the third input interface 163 and the fourth input interface 164. Among them, the first input interface module 160 is used to receive source video display data with 12G-SDI communication protocol, 6G-SDI communication protocol, 3G-SDI communication protocol or HD-SDI communication protocol. The second input interface 162 is used to receive source video display data with HDMI 2.0 communication protocol. The third input interface 163 is used to receive source video display data with DP 1.2 communication protocol. The fourth input interface 164 is used to receive OSD (On-Screen Display, screen menu type adjustment) menu picture source video display data.

[0047] Specifically, the first input interface module 160 can include at least one group of SDI (serial digital interface) input interfaces, and in this embodiment, two groups of SDI input interface modules are included in the first input interface. As shown in the figure, Figure 2 As shown, the first input interface module 160 includes the first group of SDI input interfaces 161 (such as Figure 2 As shown, SDI1) and the second group of SDI input interfaces 162 (such as Figure 2 As shown, SDI2), each group of SDI input interfaces includes 4 SDI input interfaces. In this embodiment, the SDI input interface can be a 12G-SDI input interface, and the 12G-SDI interface supports video signal input with a maximum resolution of 8K and a frame rate of 60fps. Moreover, the 12G-SDI input interface can be compatible with 12G-SDI communication protocol, 6G-SDI communication protocol, 3G-SDI communication protocol and HD-SDI communication protocol. The SDI input interface directly transmits the high-speed signal to the video processor through the SDI signal equalizer, and is received by the receiving module of the video processor. In this embodiment, the video processor also includes two groups of SDI output interfaces, each group of SDI output interfaces includes 4 SDI output interfaces, and the two groups of SDI output interfaces are connected one by one with the two groups of SDI input interfaces, and the SDI output interface is the physical loop-out of the SDI input interface.

[0048] The second input interface 163 can be an HDMI (High Definition Multimedia Interface) input interface, supporting audio and video input in compliance with the HDMI 2.0 communication protocol requirements. The third input interface 164 can be a DP (Display Port) input interface, supporting audio and video input in compliance with the DP 1.2 communication protocol requirements. The fourth input interface 165 can be an LVDS (Low-Voltage Differential Signaling) input interface, supporting video input with a maximum resolution of 2K and a frame rate of 60 fps. The external controller transmits the OSD menu screen to the video processor through the LVDS input interface. Among the above input interfaces, the SDI input interface, the HDMI input interface, and the DP input interface are used to receive audio data and video data input from external video sources, and the LVDS input interface is used to receive video data about the OSD menu input from the external controller.

[0049] Further, the input interface of the video processor further includes an external controller interface, which is used to connect the external controller, so that the external controller performs system upgrade and monitoring on the video processor through the external controller interface, respectively.

[0050] Specifically, the external controller interface includes an SPI (Serial Peripheral Interface) interface 166 and an I2C interface 167, which are used to connect the external controller. The external controller performs program upgrade on the video processor through the SPI interface 166, and performs monitoring on the video processor through the I2C (Inter-Integrated Circuit) interface 167.

[0051] The video output interface of the video processor includes two VBO (V-BY-ONE) output interfaces 168, which support video output with a maximum resolution of double 4K and a frame rate of 60 fps, and support driving an LCD (Liquid Crystal Display) display with a resolution of 4K based on the superposition screen technology. In addition, the video processor further includes four backlight control interfaces BLC-1OUT, BLC-2OUT, BLC-3OUT, and BLC-4OUT, which can control the backlight of the external display through SPI clock control or PWM (Pulse width modulation).

[0052] In addition, the video processor also includes a headphone output interface and a speaker output interface. The video processor extracts audio signals from the SDI input interface, HDMI input interface, and DP input interface, and then passes them to the audio processing module through the I2S (Inter-IC Sound, integrated circuit built-in audio) interface. The audio processing module includes an encoder, decoder, and amplifier for processing the audio signal, and then outputs it through the headphone output interface and the speaker output interface. The headphone output interface can drive the headphones for the left and right channels, and the speaker output interface can drive the speakers for the left and right channels. In addition, the video processor also includes a power input interface for inputting external power, and a GPIO (General-Purpose Input / Output Ports, general input and output) interface for controlling its functions through programming.

[0053] The above-mentioned video processor includes an SDI input interface, an HDMI input interface and a DP input interface, which can receive video data of different communication protocols from the above-mentioned video input interfaces, and process the video data of different communication protocols to output them to an external controller, thereby improving the compatibility of the video processor.

[0054] In one embodiment, Figure 3 As shown, the receiving module 110 includes a first receiving unit 111, a second receiving unit 112, a third receiving unit 113, and a fourth receiving unit 114. The first receiving unit 111 is connected to the first input interface module 160, and is used to parse the source video display data having the 12G-SDI communication protocol, the 6G-SDI communication protocol, the 3G-SDI communication protocol, or the HD-SDI communication protocol into the first valid video display data. The second receiving unit 112 is connected to the second input interface 163, and is used to parse the source video display data having the HDMI 2.0 communication protocol into the second valid video display data. The third receiving unit 113 is connected to the third input interface 164, and is used to parse the source video display data having the DP 1.2 communication protocol into the third valid video display data. The fourth receiving unit 114 is connected to the fourth input interface 165, and is used to parse the source video display data of the OSD menu screen transmitted by the external controller into the fourth valid video display data. The first valid video display data, the second valid video display data, the third valid video display data, and the fourth valid video display data have the same data format, so that the subsequent video pre-processing module 120 can pre-process the parsed valid video display data. By using the first receiving unit, the second receiving unit, the third receiving unit, and the fourth receiving unit, the video processor can extract valid video data from source video display data with different communication protocols for processing by the video processor, thereby improving the data compatibility of the video processor.

[0055] In one embodiment, as shown in Figure 3 The video pre-processing module 120 includes a synchronization unit 121 and a first buffer controller 122. The synchronization unit 121 is configured to store the valid video display data from different input interfaces into an external buffer, and read out the valid video display data from the external buffer by using a synchronous clock through the first buffer controller 122, so as to synchronize the valid video display data from different input interfaces.

[0056] Specifically, the synchronization unit 121 is responsible for synchronizing the video received from different input interfaces. The synchronization is achieved by storing the valid video display data from different input interfaces into an external buffer, and then reading out the valid video display data from the external buffer by using a synchronous clock and timing. The external buffer can be a DDR4-SDRAM (Double-Data-Rate Fourth Generation-Synchronous Dynamic Random Access Memory) buffer.

[0057] In one embodiment, the pre-processing module 120 further includes a resolution conversion unit 123. The resolution conversion unit 123 is configured to convert the resolution of the valid video display data after data synchronization, so as to reach a target resolution.

[0058] Further, the resolution conversion unit 123 converts the resolution of the valid video display data after data synchronization by using a resolution scaling conversion. When the resolution of the valid video display data after scaling conversion is less than the target resolution, pixel supplement is performed, so as to reach the target resolution of the display picture.

[0059] Specifically, in the present application, the external display connected to the video processor can be a 4K ultra-high definition display. Generally, the resolution of the 4K ultra-high definition display is 4096*2160. Therefore, in order to adapt to the resolution of the external display, the resolution conversion unit 123 can convert the resolution of the received valid video display data to 4096*2160. The resolution conversion unit 123 detects the resolution of the received valid video display data, and determines the up-scaling conversion or down-scaling conversion according to the resolution of the received valid video display data and the resolution of the external display, and determines the conversion coefficient, and then converts the valid video display data according to the conversion coefficient, so as to reach the target resolution, i.e. 4096*2160, of the converted valid video display data.

[0060] As shown in Figure 4As shown, when the resolution conversion unit 123 detects that the resolution of the input valid video display data is 2048*1080, the resolution of the input valid video display data is up-scaled and converted to 4096*2160 by a factor of 2; when the resolution conversion unit 123 detects that the resolution of the input valid video display data is 8192*4320, the resolution of the input video is down-scaled and converted to 4096*2160 by a factor of 2; when the resolution conversion unit 123 detects that the resolution of the input valid video display data is 4096*2160, it remains unchanged.

[0061] like Figure 5 As shown, if the input effective video display data has a horizontal pixel:vertical pixel ratio of 16:9, the resolution conversion unit 123 uniformly converts the effective video display data to a resolution of 3840*2160. It then adds 128 columns of monochrome pixels on either side of the video image, bringing the number of horizontally displayed pixels to 4096, thereby converting the resolution to 4096*2160. The added monochrome pixels can be black or white. For example, if the input effective video display data has a resolution of 1280*720 or 1920*1080, the resolution of the input effective video display data is upscaled to 3840*2160 using a conversion factor of 3 and a conversion factor of 2. If the input effective video display data has a resolution of 7680*4320, the resolution is downscaled to 3840*2160 using a conversion factor of 2. If the input effective video display data has a resolution of 3840*2160, the resolution remains unchanged. Then, 128 columns of black pixels are added on both sides of the video image, bringing its resolution to 4096*2160. Of course, 4K resolution also has various derivative resolutions, such as 4096*3112, 3656*2664, and 3840*2160. This application can also use the above resolution conversion method to convert the resolution of the effective video display data to the above derivative 4K resolution. The video processor of the above embodiment can receive video sources with multiple resolutions and convert them into the target resolution, and has good compatibility.

[0062] In one embodiment, the pre-processing module 120 further includes a scanning mode conversion unit 124, which is used to determine the scanning mode of the input valid video display data and convert the scanning mode of the valid video display data into progressive scanning according to the determination result.

[0063] As an example, when the scanning mode of the effective video display data is interlaced scanning, the scanning mode conversion unit 124 interweaves the effective video display data corresponding to the odd lines of the odd frame and the effective video display data corresponding to the even lines of the adjacent even frame to convert the interlaced scanning into progressive scanning.

[0064] like Figure 6 As shown, when the scanning method for valid video display data is interlaced scanning, assuming that image n is an odd-numbered frame, when scanning image n, only the display data corresponding to the odd-numbered lines are scanned, and the even-numbered lines are not scanned. When scanning image n+1, only the display data corresponding to the even-numbered lines are scanned, and the odd-numbered lines are not scanned. The scanning method for images n+2, n+3, and subsequent frames is similar. When converting from interlaced scanning to progressive scanning, the display data of the even-numbered lines of image n+1 is copied to the even-numbered lines of image n, and the display data of the odd-numbered lines of image n is copied to the odd-numbered lines of image n+1. In this way, the display data of adjacent odd and even frames are cross-combined, so that image n and image n+1 can each form a complete image frame, and the display content of image n and image n+1 is the same. When scanning image n and image n+1, the display data corresponding to the odd and even lines of the combined image are scanned progressively.

[0065] As another example, when the scanning mode of the effective video display data is interlaced scanning, the effective video display data corresponding to the odd lines of the odd frames is kept unchanged, and the even lines of the odd frames are filled with black pixels, and the effective video display data corresponding to the even lines of the adjacent even frames is kept unchanged, and the odd lines of the even frames are filled with black pixels, so as to convert the interlaced scanning into the progressive scanning.

[0066] like Figure 7 As shown, assuming that image n is an odd-numbered frame, during the interlaced scanning process, when scanning image n, only the display data corresponding to the odd-numbered rows is scanned, and the even-numbered rows are not scanned. When scanning image n+1, only the display data corresponding to the even-numbered rows is scanned, and the odd-numbered rows are not scanned. The scanning method for image n+2, image n+3, and subsequent frames is similar. When converting interlaced scanning to progressive scanning, the display data corresponding to the odd-numbered rows of image n remains unchanged, and the even-numbered rows of image n are filled with black pixels. During scanning, the odd and even rows are scanned line by line, with the odd rows displayed normally and the even rows displayed black. When scanning image n+1, the display data of the even rows remains unchanged, and the odd rows of image n+1 are filled with black pixels. During scanning, the odd and even rows are scanned line by line, with the even rows displayed normally and the odd rows displayed black.

[0067] As another example, when the scanning mode of the valid video display data is the line-by-line segmented scanning, the valid video display data corresponding to the odd lines of the odd frames and the valid video display data corresponding to the even lines of the adjacent even frames are interleaved and combined to convert the line-by-line segmented scanning into the line-by-line scanning.

[0068] Specifically, as shown in FIG. 1, in the line-by-line segmented scanning, the image n is divided into an odd field and an even field, the odd field includes the odd line display data of the image n, and the even field includes the even line display data of the image n. In the scanning, the odd lines of the odd field of the image n are scanned line by line first, and then the even lines of the even field of the image n are scanned line by line to complete the scanning of the image n. Figure 8

[0069] In the conversion of the line-by-line segmented scanning into the line-by-line scanning, the odd lines of the image n and the even lines of the image n are interleaved and combined, that is, the display data of the even lines of the even field of the image n is interleaved between the odd lines of the odd field, and in the scanning, the display data of the odd lines and the even lines are scanned line by line.

[0070] The above-mentioned video processor can convert different scanning modes into the line-by-line scanning, so that the output display picture is clear and flicker-free, the dynamic distortion is small, and the display effect can be improved.

[0071] In one of the embodiments, the preprocessing module 120 further includes a frame rate conversion unit 125, which is configured to uniformly copy the frame rate of the valid video display data by an integer multiple to convert the frame rate into a target frame rate.

[0072] Specifically, the frame rate uniformization is performed by frame rate conversion by an integer multiple, and the uniform frame copying is used to prevent the frame non-uniformity caused by the frame rate conversion, and to avoid the freezing of the video in the playing process. The corresponding relationship of the frame rate conversion is shown in the following table.

[0073] Input frame rate (fps) Transform mode Uniform output frame rate (fps) 24 2x frame uniform copy 48 24 / 1.001 2x frame uniform copy 48 / 1.001 25 2x frame uniform copy 50 30 2x frame uniform copy 60 30 / 1.001 2x frame uniform copy 60 / 1.001 50 Keep unchanged 50 60 Keep unchanged 60 60 / 1.001 Keep unchanged 60 / 1.001

[0074] The final frame rate is unified to 48 (48 / 1.001) fps, 50 fps and 60 (60 / 1.001) fps, and in the subsequent processing, the frame rate will not be converted again. Since the frame rate is uniformly copied by an integer multiple, the freezing of the playing picture caused by the non-uniform frame will not occur. In addition, increasing the frame rate to 48 (48 / 1.001) fps, 50 fps and 60 (60 / 1.001) fps can make the output video more smooth and clear. It can be understood that, in order to be able to receive and display videos with multiple frame rates, the display device in the later stage can support the frame rate input range of 45 fps to 75 fps.

[0075] ​In addition, the video preprocessing module 120 also unifies the color format and the pixel bit depth of the input effective video display data. The color format is unified as YCbCr444 or RGB. If the color format of the input effective video display data is YCbCr422 or YCbCr420, it is converted into YCbCr444. If the color format of the input effective video display data is YCbCr444 or RGB, it remains unchanged. The pixel bit depth is unified as 12 bits. If the pixel bit depth of the input effective video display data is 8 bits or 10 bits, it is converted into 12 bits by filling 0 in the low bit. If the pixel bit depth of the input effective video display data is 12 bits, it remains unchanged. If the pixel bit depth of the input effective video display data is 14 bits or 16 bits, the low bit is truncated to convert it into 12 bits.

[0076] The video processor converts the different resolutions, scanning modes, frame rates, color formats and pixel bit depths of the input video into a unified video format to meet the display requirements of the subsequent 4K display and improve the display effect.

[0077] In one embodiment, the first receiving unit 111 includes at least one sub-receiving unit connected to at least one group of SDI input interfaces. Each sub-receiving unit is used to convert four non-homogeneous source video display data into four non-homogeneous effective video display data. The preprocessing module 120 further includes a four-way display connector 126 connected to the at least one sub-receiving unit for converting the four non-homogeneous effective video display data received from the sub-receiving unit into effective video display data with a preset video format, and performing image splicing on the four effective video display data with the preset video format according to a preset rule.

[0078] Specifically, this embodiment is described by taking the four-way display connector 126 connected to one of the sub-receiving units as an example. The sub-receiving unit is connected to four SDI input interfaces, and is used to receive four channels of non-homologous source video display data and convert the four channels of source video display data into valid video display data. After the four channels of valid video display data are uniformly converted into the aforementioned video format, they have a unified resolution, frame rate, scanning mode, color format, and color bit depth. In this embodiment, the display screens corresponding to the four channels of valid video display data can be combined in the form of a "田" character, that is, the display part of the display is divided into two equal parts in the upper and lower parts, and then the display part of the display is divided into two equal parts in the left and right parts, and the display resolution of each part is 2048*1080. Then, the color format of the display screen corresponding to the four channels of effective video display data is unified as follows: the resolution is unified as 2048*1080; the frame rate is unified as 60fps, wherein the frame rate may have non-uniform frame replication, for example, when the frame rate of the source display data is 24fps or 25fps, it needs to be non-uniformly replicated to 60fps; the image scanning method is unified as line-by-line scanning; the color format is unified as YCbCr; and the pixel bit depth is unified as 12 bits. Then, as Figure 9 As shown, four images are spliced ​​together in a "田" (field) pattern. The resulting video resolution is 4096*2160, the frame rate is 60fps, the scanning mode is progressive scan, the color format is YCbCr, and the pixel depth is 12-bit. The final display shows the four-grid display image input from the four SDI input interfaces. The above-mentioned video processor, by using a four-display connector, can display four different video output sources on the same monitor. When used in a surveillance system, this video processor facilitates observation and comparison.

[0079] The image quality processing module 130 is used to adjust and optimize the video parameters of the input video. The adjustable video parameters include hue, chroma, contrast, brightness, color temperature, gamma correction parameters, color gamut, and color space conversion parameters. The color gamut adjustment function can use the color matrix of the 1D LUT (Look Up Table) and the 3D-LUT engine for adjustment.

[0080] In one embodiment, the post-processing module 140 includes an OSD menu overlay unit 141 , a state information generating unit 142 , a waveform overlay unit 143 , and a mark generating unit 144 .

[0081] The OSD menu superimposition unit 141 is configured to generate an OSD menu according to the OSD menu parameters and superimpose the OSD menu on the first video picture output by the picture processing module 130. The status information generation unit 142 is configured to extract a video format of the valid video display data and generate a blanking picture according to the video format of the valid video display data, so that the blanking picture is superimposed on the first video picture after picture processing. The waveform chart superimposition unit 143 is configured to obtain waveform chart information of the valid video display data and draw a waveform chart according to the waveform chart information, so that the waveform chart is superimposed on the first video picture. The mark generation unit 144 is configured to receive mark information and generate a mark according to the mark information, so that the mark is superimposed on the first video picture.

[0082] Specifically, the OSD menu superimposition unit 141 is connected to the fourth receiving unit and is responsible for generating an OSD menu image according to the OSD menu parameters input by the fourth receiving unit and superimposing the OSD menu image on the first video picture after picture processing, wherein the superimposition position and transparency can be adjusted.

[0083] The status information generation unit 142 is configured to identify status information of the video interface input video, wherein the status information can be a video format of the input video, and the video format includes resolution, frame rate, color space, bit depth, scanning mode, etc. The above status information is converted into text and displayed on the first video picture after OSD menu image superposition, and can be displayed at the upper right corner, upper left corner, etc. of the first video picture as long as it is not superimposed with the OSD menu image. The status information display has a blanking time, and the status information is automatically blanked after n seconds of display. When the format of the source video display data input by the input interface changes, the status information generation unit 142 identifies the video format according to the newly input source video display data and displays the status information again, and blanks again after the blanking time. In addition, when there is no video input by the input interface or the input video format is not supported, the status information will not be blanked, and no signal or not supported will be displayed.

[0084] The waveform chart superimposition unit 133 is configured to obtain waveform chart information and image the waveform chart information to obtain a waveform chart, and superimpose the waveform chart on the first video picture for display. Further, the post-processing module can further include a video analysis unit 145 connected to the waveform chart superimposition unit 133. The video analysis unit 145 is configured to read the valid video display data from the pre-processing module 120, extract the waveform chart information from the valid video display data, and then send the waveform chart information to the waveform chart superimposition unit 133. The waveform chart superimposition unit 133 images the waveform chart information to generate a waveform chart and superimposes the waveform chart on the first video picture for display to facilitate user observation and analysis. The waveform chart information can be a chrominance waveform chart, a luminance waveform chart, etc.

[0085] The marker generating unit 144 is configured to obtain marker information input by the user, and generate a marker graphic by visualizing the marker information, so as to overlay the marker graphic on the first video screen. The marker information may be a safety frame, a center point, or the like.

[0086] The post-processing module 140 further includes a second cache controller 146 . The second cache controller 146 is configured to read and write data from an external cache when the post-processing module 140 needs to cache data.

[0087] In one embodiment, the video processor further includes an audio sending module and an audio processing module (not shown in the figure). The audio sending module is used to receive audio data through the input interface, parse the audio data into valid audio data with a preset data format, and send the data to the audio processing module so that the audio processing module processes the valid audio data and outputs it to the external playback module.

[0088] Specifically, the audio sending module extracts audio signals from the SDI input interface, HDMI input interface and DP input interface, and then passes them to the audio processing module through the I2S interface. The audio processing module includes an encoder / decoder and an amplifier for processing the audio signals, and then outputs them through the headphone output interface and the speaker output interface.

[0089] The aforementioned video processor integrates multiple functions, including video reception, video preprocessing, video quality control, video post-processing, and video output, into a single system. Compared to distributed systems, the integrated video processor simplifies the connections between processing modules and reduces data exchange between them, improving system stability and reducing power consumption and the impact of electromagnetic compatibility issues on the system. Furthermore, the video processor includes at least one input interface capable of receiving source video display data using different communication protocols, processing this source video display data, and outputting it to an external display for display, thereby improving the compatibility of the video processor.

[0090] like Figure 10 As shown, another embodiment of the present application provides a display control system, comprising the aforementioned video processor 100. The display control system further comprises a controller 200, which is configured to control the video processor 100 to process the received source video display data and output the processed video display data to a display.

[0091] Specifically, in this embodiment, the controller 200 can be a SOC (System on Chip). The controller 200 can control and schedule the operation of the processing system of the video processor 100 through the I2C input interface of the video processor, and update and upgrade the program of the video processor 100 through the SPI input interface. The controller 200 can also deliver the drawn OSD menu to the video processor 100 through the LVDS input interface, and then the video processor 100 implements and inputs the superposition of the image.

[0092] The display control system described above comprises the video processor described above, so that various functions such as video receiving, video preprocessing, video quality processing, video post-processing, and video output can be integrated in one system. Compared with a distributed system, the integrated video processor reduces the connection and data interaction between processing cores, improves system stability, and reduces the impact of power consumption and electromagnetic compatibility problems on the system. Moreover, the video processor further comprises at least one input interface, which can receive source video display data with different communication protocols and process the source video display data with different communication protocols for output to an external display for display, thereby improving the compatibility of the video processor.

[0093] As shown in Figure 11 Another embodiment of the present application provides a video processing method based on the video processor described above, which comprises:

[0094] In step S101, source video display data with different communication protocols is received through at least one input interface, and the source video display data with different communication protocols is parsed into valid video display data.

[0095] In step S102, the video format of the valid video display data is preprocessed to generate valid video display data with a preset video format.

[0096] In step S103, the quality parameters in the valid video display data with the preset video format are adjusted to output a first video picture.

[0097] In step S104, the video parameters of the valid video display data are extracted, and a superimposed picture is generated according to the video parameters, and the superimposed picture is superimposed on the first video picture.

[0098] In step S105, the valid video display data of the first video picture and the valid video display data of the superimposed picture are subjected to data format conversion to be packaged into output video display data, and the output video display data is output to an external display through a video output interface, so that the superimposed picture is superimposed on the first video picture for display.

[0099] It should be noted that the description of the video processing method in the present application refers to the description of the working process of the video processor in the present application, which will not be repeated here.

[0100] The video processing method described above can integrate video receiving, video preprocessing, video quality processing, video post-processing and video output and other functions in one system, reduce the connection and data interaction between processing cores, improve the system stability, and can reduce the impact of power consumption and electromagnetic compatibility problems on the system. And through at least one input interface, source video display data with different communication protocols can be received, and source video display data with different communication protocols can be processed and output to an external display for display, improving data compatibility.

[0101] In addition, another embodiment of the present application provides a computer readable storage medium having a video processing program stored thereon, which is executed by a processor to implement the aforementioned video processing method.

[0102] The computer readable storage medium described above can integrate video receiving, video preprocessing, video quality processing, video post-processing and video output and other functions in one system, reduce the connection and data interaction between processing cores, improve the system stability, and can reduce the impact of power consumption and electromagnetic compatibility problems on the system. And through at least one input interface, source video display data with different communication protocols can be received, and source video display data with different communication protocols can be processed and output to an external display for display, improving data compatibility.

[0103] In addition, another embodiment of the present application provides an electronic device comprising a memory, a processor, and a video processing program stored on the memory and executable on the processor, wherein the processor executes the video processing program to implement the aforementioned video processing method.

[0104] The electronic device can integrate video receiving, video preprocessing, video quality processing, video post-processing and video output and other functions in one system through the video processing method, reduce the connection and data interaction between processing cores, improve the system stability, and reduce the influence of power consumption and electromagnetic compatibility problems on the system. And through at least one input interface, source video display data with different communication protocols can be received, and source video display data with different communication protocols can be processed and output to an external display for display, improving data compatibility.

[0105] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a list of executable instructions for implementing logic functions, which can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus or device, such as a computer-based system, a system including a processor or other system that can fetch the instructions from an instruction execution system, apparatus or device and execute the instructions, or in conjunction with these instruction execution systems, apparatus or devices. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transport programs for use by or in connection with an instruction execution system, apparatus or device, or in conjunction with these instruction execution systems, apparatus or devices. More specific examples (non-exhaustive list) of computer-readable medium include the following: electrical connections having one or more wires (electronic devices), portable computer diskette (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CD ROM). In addition, the computer-readable medium can even be paper or other suitable medium on which the program can be printed, because the program can be electronically obtained, for example, by optical scanning of the paper or other medium, followed by editing, interpretation or processing, if necessary, in other suitable ways, and then stored in the computer memory.

[0106] It should be understood that parts of the present application can be implemented in hardware, software, firmware or a combination thereof. In the above-described embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies known in the art or their combinations can be used: discrete logic circuit with logic gate circuit for implementing logic functions on data signals, application specific integrated circuit with suitable combination logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) and the like.

[0107] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0108] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified and limited.

[0109] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and other terms should be understood in a broad sense, for example, can be fixedly connected, can also be detachably connected, or integrated; can be mechanically connected, can also be electrically connected; can be directly connected, can also be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0110] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A video processor, characterized in that: include: a receiving module, configured to receive source video display data with different communication protocols through at least one input interface, and parse the source video display data with different communication protocols into valid video display data; A preprocessing module, connected to the receiving module, configured to preprocess the video format of the valid video display data to generate valid video display data having a preset video format; an image quality processing module, the image quality processing module being connected to the pre-processing module, and configured to adjust image quality parameters in the effective video display data having a preset video format to output a first video picture; a post-processing module connected to the pre-processing module and the image quality processing module, the post-processing module being configured to extract video parameters of the effective video display data, generate an overlay image based on the video parameters, and overlay the overlay image onto the first video image; a video output module connected to the post-processing module, configured to convert the valid video display data of the first video screen and the valid video display data of the overlay screen into data formats to encapsulate them into output video display data, and output the output video display data to an external display via a video output interface, so as to superimpose the overlay screen on the first video screen for display; The input interface includes: A first input interface module is used to receive source video display data having a 12G-SDI communication protocol, a 6G-SDI communication protocol, a 3G-SDI communication protocol, or an HD-SDI communication protocol; A second input interface for receiving source video display data having an HDMI 2.0 communication protocol; A third input interface is used to receive source video display data having a DP 1.2 communication protocol; A fourth input interface, for receiving source video display data of the OSD menu screen; the fourth input interface is an LVDS input interface; The pre-processing module includes a synchronization unit and a first buffer controller, wherein the synchronization unit is used to store valid video display data from different input interfaces into an external buffer and read the data from the external buffer using a synchronization clock through the first buffer controller to synchronize the valid video display data from the different input interfaces; The first input interface module includes at least one group of SDI input interfaces, each group of SDI input interfaces includes four SDI input interfaces for receiving four channels of non-same source video display data, the first receiving unit includes at least one sub-receiving unit, each of which is connected to the at least one group of SDI input interfaces, each of which is used to convert the four channels of non-same source video display data into four channels of non-same valid video display data; The pre-processing module further includes a four-way display connector, the four-way display connector being connected to the sub-receiving unit and configured to convert four channels of non-homologous valid video display data received from the sub-receiving unit into valid video display data having a preset video format, and perform image splicing on the four channels of valid video display data having the preset video format according to a preset rule; The post-processing module includes an OSD menu overlay unit, a status information generation unit, a waveform overlay unit, a mark generation unit and a video analysis unit, wherein: The OSD menu overlay unit is configured to form an OSD menu according to the OSD menu parameters received from the LVDS receiving unit, and overlay the OSD menu on the first video screen; The state information generating unit is used to identify the video format of the effective video display data, and generate a blanking picture according to the video format of the effective video display data, so that the blanking picture is superimposed on the first video picture after image quality processing; The video analysis unit is connected to the waveform graph superposition unit, the video analysis unit is used to read the valid video display data from the preprocessing module and extract the waveform graph information of the valid video display data, and the waveform graph superposition unit is used to draw a waveform graph according to the waveform graph information so that the waveform graph is superimposed on the first video screen; The marker generating unit is configured to obtain marker information and generate a marker graphic according to the marker information, so that the marker graphic is superimposed on the first video screen.

2. The video processor according to claim 1, wherein: The receiving module includes: a first receiving unit connected to the first input interface module, configured to parse source video display data having the 12G-SDI communication protocol, the 6G-SDI communication protocol, the 3G-SDI communication protocol, or the HD-SDI communication protocol into first valid video display data; a second receiving unit connected to the second input interface, configured to parse the source video display data having the HDMI 2.0 communication protocol into second valid video display data; a third receiving unit connected to the third input interface, configured to parse the source video display data having the DP 1.2 communication protocol into third valid video display data; a fourth receiving unit connected to the fourth input interface, configured to parse the source video display data of the OSD menu screen into fourth valid video display data; The first valid video display data, the second valid video display data, the third valid video display data and the fourth valid video display data have the same data format.

3. The video processor according to claim 1, wherein: The pre-processing module further includes a resolution conversion unit, which is used to perform resolution conversion on the effective video display data after data synchronization, so that the resolution of the effective video display data after data synchronization reaches the target resolution.

4. The video processor according to claim 3, wherein: The resolution conversion unit converts the resolution of the effective video display data after data synchronization by using a resolution multiplication conversion method, wherein: When the resolution of the effective video display data after the multiplication conversion is smaller than the target resolution, a corresponding number of black pixels are added on both sides of the display image so that the resolution of the display image reaches the target resolution.

5. The video processor according to claim 3 or 4, characterized in that: The pre-processing module further includes a scanning mode conversion unit, which is used to determine the scanning mode of the input effective video display data and convert the scanning mode of the effective video display data into a line-by-line scanning mode according to the determination result.

6. The video processor according to claim 5, wherein: When the scanning mode of the effective video display data is interlaced scanning, Interleaving and combining the valid video display data corresponding to the odd lines of the odd frames and the valid video display data corresponding to the even lines of the adjacent even frames to convert the interlaced scanning into the progressive scanning; or The valid video display data corresponding to the odd rows of the odd frame is kept unchanged, and the even rows of the odd frame are filled with black pixels. The valid video display data corresponding to the even rows of the adjacent even frame is kept unchanged, and the odd rows of the even frame are filled with black pixels, so as to convert the interlaced scanning into the progressive scanning.

7. The video processor according to claim 5, wherein: When the scanning mode of the effective video display data is line-by-line segmented scanning, the effective video display data corresponding to the odd lines of the odd field and the effective video display data corresponding to the even lines of the even field are interspersed and combined to convert the line-by-line segmented scanning into the line-by-line scanning.

8. The video processor according to claim 5, wherein: The pre-processing module further includes a frame rate conversion unit, which is used to uniformly copy the frame rate of the effective video display data in integer multiples to uniformly convert it into a target frame rate.

9. The video processor according to claim 1, wherein: The image quality parameters include hue, chroma, contrast, brightness, color temperature, color gamut, GAMMA correction parameters and color space conversion parameters.

10. The video processor according to claim 8, wherein: The post-processing module further includes a second cache controller, which is configured to read and write the external cache when the post-processing module caches the valid video display data.

11. The video processor according to claim 1, wherein: The video processor also includes an audio sending module and an audio processing module; The audio sending module is used to receive audio data through the input interface, parse the audio data into valid audio data with a preset data format and send it to the audio processing module, so that the audio processing module processes the valid audio data and outputs it to an external playback module.

12. The video processor according to claim 1, wherein: The input interface further includes an external controller interface, which is used to connect to an external controller so that the external controller can perform system upgrade and monitor the video processor respectively through the external controller interface.

13. A display control system, characterized in that: The display control system comprises the video processor according to any one of claims 1 to 12, and further comprises a controller, wherein the controller is used to control the video processor to process the received source video display data and output the processed video display data to the display.

14. A video processing method, characterized in that: include: receiving source video display data with different communication protocols through at least one input interface, and parsing the source video display data with different communication protocols into valid video display data; Preprocessing the video format of the effective video display data to generate effective video display data having a preset video format; Adjusting the image quality parameters of the effective video display data having the preset video format to output a first video picture; Extracting video parameters of the effective video display data, generating an overlay image according to the video parameters, and superimposing the overlay image onto the first video image; performing data format conversion on the effective video display data of the first video screen and the effective video display data of the overlay screen to encapsulate them into output video display data, and outputting the output video display data to an external display through a video output interface, so as to superimpose the overlay screen on the first video screen for display; receiving source video display data having a 12G-SDI communication protocol, a 6G-SDI communication protocol, a 3G-SDI communication protocol, or an HD-SDI communication protocol; receiving source video display data having an HDMI 2.0 communication protocol; Receiving source video display data having DP 1.2 communication protocol; Receive source video display data of the OSD menu screen; The fourth input interface is an LVDS input interface; The method further includes storing valid video display data from different input interfaces into an external buffer, and reading the data from the external buffer using a synchronous clock to synchronize the valid video display data from the different input interfaces; The method further includes: receiving four channels of non-homogeneous source video display data, converting the four channels of non-homogeneous source video display data into four channels of non-homogeneous valid video display data; converting the received four channels of non-homogeneous valid video display data into valid video display data having a preset video format, and performing image splicing on the four channels of valid video display data having the preset video format according to a preset rule; forming an OSD menu from the received OSD menu parameters, and superimposing the OSD menu on the first video picture; Identifying a video format of the effective video display data, and generating a blanking image according to the video format of the effective video display data, so that the blanking image is superimposed on the first video image after image quality processing; Reading valid video display data from a preprocessing module, extracting waveform information of the valid video display data, and drawing a waveform graph according to the waveform information so that the waveform graph is superimposed on the first video screen; Marking information is acquired, and a marking graphic is generated according to the marking information, so that the marking graphic is superimposed on the first video screen.

15. A computer-readable storage medium, characterized in that A video processing program is stored thereon, and when the video processing program is executed by the processor, the video processing method according to claim 14 is implemented.

16. An electronic device, characterized in that: The method comprises a memory, a processor, and a video processing program stored in the memory and executable on the processor. When the processor executes the video processing program, the video processing method according to claim 14 is implemented.

Images