Chip Pin Open / Short Circuit Test Device and Method Based on Positive and Negative Voltages

Abstract

This application relates to a short - circuit and open - circuit test device and method for chip pins based on positive and negative voltages. The device includes a chip under test, a constant - current and voltage - limiting source, a test diode, a switch matrix, and a voltage acquisition circuit. The constant - current and voltage - limiting source supplies appropriate voltage and current. The switch corresponding to the pin under test in the switch matrix is closed, and current flows. Since there is a test diode corresponding to the pin as a load, a voltage drop is generated. The voltage acquisition circuit acquires the voltage drop generated during the test, and judges the state of the pin through the voltage drop to determine whether the pin of the chip under test is open - circuited, short - circuited, or normal, enabling measurement of each pin of the chip under test to perform detection after the chip is packaged.

Description

Technical Field

[0001] This application relates to the field of chip packaging and testing, and in particular to a chip pin open / short circuit testing device and method based on positive and negative voltages. Background Art

[0002] The production process of a chip includes chip design, manufacturing, and packaging and testing. Among them, chip packaging and testing is to cut, wire bond, and plastic package the qualified wafers produced, so that the chip circuit is electrically connected to external devices, provide mechanical and physical protection for the chip, and perform functional and performance tests on the packaged chip.

[0003] Chip testing includes wafer testing (mid-test) and finished product testing (final test). Mid-test refers to testing the electrical capabilities and circuit functions of each chip on the wafer after wafer manufacturing is completed to ensure that the wafer can achieve the circuit functions of the chip. Mid-test is the last step before the wafer is sent to the packaging factory and directly determines the quality of the packaging raw materials. Final test is the final inspection after chip packaging, and the chip is tested by a dedicated test device based on the chip type. Summary of the Invention

[0004] In order to perform post-packaging inspection on the chip, this application provides a chip pin open / short circuit testing device and method based on positive and negative voltages.

[0005] The chip pin open / short circuit testing device and method based on positive and negative voltages provided by this application adopt the following technical solutions:

[0006] A chip pin open / short circuit testing device based on positive and negative voltages, comprising:

[0007] A chip under test, the chip under test includes a power pin, a ground pin, and pins to be tested. The power pin is set as point P, and the ground pin is set as point N;

[0008] A constant current and voltage limiting source, which is used to provide a limited voltage and a constant current during the test. The voltage limiting value of the voltage and the constant current value of the current can both be set for different chips under test;

[0009] A test diode, which connects the pins to be tested, point P, and point N of the chip under test, and is used as a load for measuring the pins to be tested;

[0010] A switch matrix, including switches corresponding to each test diode. Each switch is respectively connected to the constant current and voltage limiting source and the test diode. The on / off of different test diodes is realized through the combination of different switches. Point P of the chip under test is connected to the switch matrix, and point N of the chip under test is grounded;

[0011] A voltage acquisition circuit is used to acquire the voltage drop generated by the test diode as a load during the test process of the constant current and voltage limiting source, and determine the state of the pin to be tested through the voltage drop.

[0012] By adopting the above technical solution, when measuring a specific pin on the chip to be tested, the constant current and voltage limiting source supplies a suitable voltage and current. The switch corresponding to the pin to be tested in the switch matrix is closed, and the current flows. Since there is a test diode corresponding to the pin as a load, a voltage drop is generated. The voltage acquisition circuit acquires the voltage drop generated during the test process, and determines the state of the pin through the voltage drop, so as to determine whether the pin of the chip to be tested is open circuit, short circuit or normal, enabling measurement of each pin of the chip to be tested for detection after chip packaging.

[0013] Optionally, the test diode includes an upper diode, a lower diode and a power supply diode;

[0014] The upper diode is used as an upper load when measuring the chip to be tested, and both ends of the upper diode are respectively connected to the pin to be tested of the chip to be tested and the point P;

[0015] The lower diode is used as a lower load when measuring the chip to be tested, and both ends of the lower diode are respectively connected to the pin to be tested of the chip to be tested and the point N;

[0016] The power supply diode is used as a power supply end load when measuring the chip to be tested, and both ends of the power supply diode are connected to the point N and the point P.

[0017] By adopting the above technical solution, the upper diode is used as the load between the pin to be tested and the point P, the lower diode is used as the load between the pin to be tested and the point N, and the power supply diode is used as the load between the point P and the point N, making the measurement of the chip to be tested more comprehensive.

[0018] Optionally, the constant current and voltage limiting source includes:

[0019] A positive voltage constant current and voltage limiting source is used to supply power to the test diode from the pin to be tested to the point P;

[0020] A negative voltage constant current and voltage limiting source is used to supply power to the test diode from the pin to be tested to the point N, and also supply power to the test diode from the point P to the point N;

[0021] The G terminal of the positive voltage constant current and voltage limiting source is the negative terminal, and the G terminal of the negative voltage constant current and voltage limiting source is the positive terminal.

[0022] By adopting the above technical solution, the positive voltage constant current and voltage limiting source supplies power to the test diode from the pin under test to point P, and the negative voltage constant current and voltage limiting source supplies power to the test diode from the pin under test to point N and also supplies power to the test diode from point P to point N, enabling the test diode to be powered according to different functional positions of point P and point N, making the measurement more precise.

[0023] Optionally, the switch matrix includes a positive terminal matrix and a negative terminal matrix:

[0024] One ends of multiple switches in the positive terminal matrix are all connected to the positive terminal of the positive voltage constant current and voltage limiting source, and the other ends are respectively connected to the test diode between point P and the pin under test of the chip under test, for controlling the on / off of the test diode;

[0025] One ends of multiple switches in the negative terminal matrix are all connected to the negative terminal of the negative voltage constant current and voltage limiting source, and the other ends are respectively connected to the test diode between point N and the pin under test of the chip under test, for controlling the on / off of the test diode, and for controlling the on / off of the test diode between point P and point N.

[0026] By adopting the above technical solution, when measuring between point P and the pin under test, the on / off of the test diode is controlled by the opening and closing of the positive terminal matrix, so as to realize the measurement of point P and multiple pins under test respectively; when measuring between point N and the pin under test, the on / off of the test diode is controlled by the opening and closing of the negative terminal matrix, so as to realize the control of the test diode between point N and multiple pins under test respectively, and to control the on / off of the test diode between point P and point N.

[0027] Optionally, a positive terminal grounding switch connected to the G terminal is further provided on one side of the positive voltage constant current and voltage limiting source, and a negative terminal grounding switch connected to the G terminal is further provided on one side of the negative voltage constant current and voltage limiting source.

[0028] By adopting the above technical solution, the positive terminal grounding switch controls the on / off of the positive voltage constant current and voltage limiting source, and the negative terminal grounding switch controls the on / off of the negative voltage constant current and voltage limiting source, so as to control the positive voltage constant current and voltage limiting source and the negative voltage constant current and voltage limiting source respectively.

[0029] Optionally, when there are multiple chips under test to be measured, the N points of multiple chips under test are all connected and grounded.

[0030] By adopting the above technical solution, the N points of multiple chips under test are all connected and grounded. When performing test analysis on a certain chip under test, other chips under test can continue to perform other functional tests, so that the circuits for testing the chips under test do not affect each other.

[0031] A method for open - short circuit testing of chip pins based on positive and negative voltages, comprising:

[0032] A constant - current and voltage - limiting source provides a limited voltage and a constant current during the test. The voltage - limiting value of the voltage and the constant - current value of the current can be set for different chips under test. The chip under test includes a power pin, a ground pin, and a pin to be tested. The power pin is set as point P, and the ground pin is set as point N;

[0033] Test diodes connect the upper pin, the lower pin, point P, and point N of the chip under test, and are used to measure the state of the upper pin of the chip under test and the load of the lower pin;

[0034] A switch matrix is used to control the on - off of different test diodes. It includes switches corresponding to each test diode. Each switch is respectively connected to the constant - current and voltage - limiting source and the test diode. The on - off of different test diodes is realized through the combination of different switches. Point P of the chip under test is connected to the switch matrix, and point N of the chip under test is grounded;

[0035] A voltage acquisition circuit acquires the voltage drop generated by the test diode as a load during the test by the constant - current and voltage - limiting source, and judges the state of the pin to be tested through the voltage drop.

[0036] By adopting the above - mentioned technical solution, when a specific pin on the chip under test needs to be measured, the constant - current and voltage - limiting source supplies a suitable voltage and current. The switch corresponding to the pin to be tested in the switch matrix is closed, and the current flows. Since there is a test diode corresponding to the pin as a load, a voltage drop is generated. The voltage acquisition circuit acquires the voltage drop generated during the test, and judges the state of the pin through the voltage drop, so as to judge whether the pin of the chip under test is open - circuited, short - circuited or normal, enabling each pin of the chip under test to be measured for post - packaging detection of the chip.

[0037] Optionally, the test diodes include an upper diode, a lower diode, and a power diode. The test diodes connect the upper pin, the lower pin, point P, and point N of the chip under test, and measure the state of the upper pin and the state of the lower pin of the chip under test, including:

[0038] The upper diode serves as an upper load when measuring the chip under test, and both ends of the upper diode are respectively connected to the pin to be tested of the chip under test and point P;

[0039] The lower diode serves as a lower load when measuring the chip under test, and both ends of the lower diode are respectively connected to the pin to be tested of the chip under test and point N;

[0040] The power diode is used as a power terminal load when measuring the chip under test, and both ends of the power diode are connected to the N point and the P point.

[0041] Optionally, the constant current and voltage limiting source includes a positive voltage constant current and voltage limiting source and a negative voltage constant current and voltage limiting source. The constant current and voltage limiting source provides a limited voltage and a constant current during the test process, including:

[0042] The positive voltage constant current and voltage limiting source supplies power to the test diode from the pin under test to the P point;

[0043] The negative voltage constant current and voltage limiting source supplies power to the test diode from the pin under test to the N point, and also supplies power to the test diode from the P point to the N point. ]>

[0044] In summary, the present application includes at least one of the following beneficial technical effects:

[0045] 1. The constant current and voltage limiting source supplies a suitable voltage and current. The switch corresponding to the pin under test in the switch matrix is closed, and the current flows. Since there is a test diode corresponding to the pin as a load, a voltage drop is generated. The voltage acquisition circuit acquires the voltage drop generated during the test, and judges the state of the pin through the voltage drop, so as to judge whether the pin of the chip under test is open circuit, short circuit or normal, enabling each pin of the chip under test to be measured for post-packaging detection of the chip;

[0046] 2. Multiple chips can be tested simultaneously. When chip A is performing open / short circuit analysis, chip B and chip N can continue to perform other functional tests, and the circuits do not affect each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a schematic diagram of the chip under test in the chip pin open / short circuit test device based on positive and negative voltages of the present application;

[0048] Figure 2 is a circuit structure diagram of Embodiment 1 of the chip pin open / short circuit test device based on positive and negative voltages of the present application;

[0049] Figure 3 is the circuit structure of Embodiment 2 of the chip pin open / short circuit test device based on positive and negative voltages of the present application Figure 1 ;

[0050] Figure 4 is a multi-chip common ground model diagram of Embodiment 2 of the chip pin open / short circuit test device based on positive and negative voltages of the present application;

[0051] Figure 5 is a schematic flow chart of the chip pin open / short circuit test method based on positive and negative voltages of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] The following further describes the present application in detail with reference to the accompanying drawings.

[0053] In order to detect a chip after packaging, an embodiment of the present application discloses a short-circuit and open-circuit test device and method for chip pins based on positive and negative voltages.

[0054] Embodiment 1. Refer to Figure 1 And Figure 2 , a short-circuit and open-circuit test device for chip pins based on positive and negative voltages, includes:

[0055] A chip under test, which includes a power pin, a ground pin, and pins under test. Since different pins of the chip under test have different functions, there are multiple pins under test in the chip under test. For example, in a common power management chip, the pins usually include chip power pins, voltage and current output control, constant current management, current detection, and chip ground and other pins. For example, in this embodiment, refer to Figure 1 , the power pin of the chip under test is set as point P, the ground pin is set as point N, and the pins under test can be respectively set as pin A, pin B, and pin C.

[0056] And in this embodiment, the number of chips under test is one. When there is one chip under test, the state of the pins in one chip under test is measured at a time. In other embodiments, in order to increase the chip measurement rate, multiple chips under test are set, that is, multiple chips under test are measured simultaneously in the same measurement process, and the N points of multiple chips under test are all connected and grounded.

[0057] In order to supply power to the chip under test during the test, a constant current and voltage limiting source is also disclosed. The constant current and voltage limiting source is used to provide a limited voltage and a constant current during the test. The voltage limiting value of the voltage and the constant current value of the current can be set for different chips under test. The voltage of the chip during normal use is set by another power management chip (PMIC) on the PBC. In this embodiment, the voltage and current of the constant current and voltage limiting source are set to match the corresponding chip. Therefore, before the constant current and voltage limiting source matches the voltage for the chip under test, relevant current and voltage parameters of the chip under test need to be obtained from the chip supplier, and the applied voltage is the voltage required by the chip under test, and the supplied current is the rated current of the chip under test.

[0058] Test diodes, which are connected to the pins under test, point P, and point N of the chip under test, and are used as loads for measuring the pins under test. Refer to the figure, different test diodes are connected to different pins. For example, the test diode connecting point P and pin A can be named test diode AP. The naming order is according to the current flow order. For example, the current flow order between point N and pin A is from point N to pin A, then this test diode is named test diode NA.

[0059] The switch matrix includes switches corresponding to each test diode. Each switch is respectively connected to a constant current and voltage limiting source and a test diode. The on / off of different test diodes is realized through the combination of different switches. The P point of the chip under test is connected to the switch matrix, and the N point of the chip under test is grounded. For example, referring to Figure 1 In, the switches in the switch matrix can be respectively named SW_P0, SW_P1, SW_P2, SW_P3 and SW_N0, SW_N1, SW_N2, SW_N3. The on / off of the corresponding test diodes is realized through the cooperation between the switch matrices. In this embodiment, the switches of the switch matrix are set as MOS transistors, and the on / off of the diodes is controlled through the on / off of the MOS transistors.

[0060] Since each chip under test includes multiple different pins, different pins need to be measured separately to determine whether the status of the corresponding pins is normal. The test diodes also need to be set according to the number of pins of each pin, so as to measure the pins of the chip under test more comprehensively. Therefore, in this embodiment, the test diodes include upper diodes, lower diodes and power supply diodes.

[0061] The upper diode is used as an upper load when measuring the chip under test. The two ends of the upper diode are respectively connected to the pin under test of the chip under test and the P point. Referring to the figure, in this embodiment, the upper diodes can be AP, BP and CP respectively, so as to measure the pins connected to the P point in the chip under test. In other embodiments, if the number of pins connected to the P point in the chip under test is large, more upper diodes can also be set. For example, when the number of pins to be tested is two more than that in the figure, corresponding DP, EP and other pins can also be set. That is, in this embodiment, the number of upper diodes set is greater than or equal to the number of pins of the chip under test. Since the number of pins under test of the chip under test in this application is three, the number of upper diodes that play a role corresponds to three of the pins under test. If the number of pins under test of the chip under test is more, the number of upper diodes that play a role also increases accordingly.

[0062] The lower diode is used as a lower load when measuring the chip under test. The two ends of the lower diode are respectively connected to the pin under test of the chip under test and the N point. The principle of setting the lower diode is the same as that of setting the upper diode.

[0063] The power supply diode is used as a power supply terminal load when measuring the chip under test. The two ends of the power supply diode are connected to the N point and the P point. The number of each power supply diode is only set to one, or the diode that plays a role in measuring the power supply terminal is the power supply diode, and the setting principle is the same as that of the upper diode.

[0064] Embodiment 2:

[0065] The constant current and voltage limiting source includes:

[0066] A positive voltage constant current and voltage limiting source is used to supply power to the test diodes from the pins under test to point P. In this embodiment, the positive voltage constant current and voltage limiting source is set as OSP, that is, OSP is used to supply power to the upper diodes such as AP, BP, and CP for testing.

[0067] A negative voltage constant current and voltage limiting source is used to supply power to the test diodes from the pins under test to point N, and also to supply power to the test diodes from point P to point N. Among them, the negative voltage constant current and voltage limiting source is set as OSN, that is, OSN is used to supply power to the lower diodes such as NA, NB, and NC for testing, and at the same time supply power to the power diode NP for testing. The G terminal of the positive voltage constant current and voltage limiting source is the negative terminal, and the G terminal of the negative voltage constant current and voltage limiting source is the positive terminal. One side of the positive voltage constant current and voltage limiting source is also provided with a positive terminal grounding switch OSP_GND_S connected to the G terminal, and one side of the negative voltage constant current and voltage limiting source is also provided with a negative terminal grounding switch OSN_GND_S connected to the G terminal.

[0068] In order to control the on / off of the corresponding test diodes, the switch matrix includes a positive terminal matrix and a negative terminal matrix:

[0069] One ends of multiple switches in the positive terminal matrix are all connected to the positive terminal of the positive voltage constant current and voltage limiting source, and the other ends are respectively connected to the test diodes between point P and the pins under test of the chip under test to control the on / off of the test diodes; one ends of multiple switches in the negative terminal matrix are all connected to the negative terminal of the negative voltage constant current and voltage limiting source, and the other ends are respectively connected to the test diodes between point N and the pins under test of the chip under test to control the on / off of the test diodes, and are used to control the on / off of the test diodes between point P and point N.

[0070] Refer to Figure 3 And Figure 4 , in this embodiment, the switches in the positive terminal matrix include SW_P0, SW_P1, SW_P2, and SW_P3, and the switches in the negative terminal matrix include SW_N0, SW_N1, SW_N2, and SW_N3. Among them, the left end of SW_P0 in the positive terminal matrix is connected to the test source, and the right end is connected in parallel to point P of the chip under test and SW_N0 in the negative terminal matrix; the left end of SW_P1 in the positive terminal matrix is connected to the test source, and the right end is connected in parallel to pin A and SW_N1 in the negative terminal matrix; the left end of SW_P2 in the positive terminal matrix is connected to the test source, and the right end is connected in parallel to pin B and SW_N2 in the negative terminal matrix; the left end of SW_P3 in the positive terminal matrix is connected to the test source, and the right end is connected in parallel to pin C and SW_N3 in the negative terminal matrix.

[0071] The upper diode testing process, taking IOA as an example, the constant current and voltage limiting source OSP outputs a constant current that passes through the switch SW_P1 to point A. The current passes through the diode AP to point P, then through the switch SW_N0 to the node OSN, and then through the switch OSN_GND_S to point G (system ground), and then returns to the negative terminal of the test source OSP. This is the test current path. Since there is current passing through the diode AP, a voltage drop UAP will be generated. The potential at point P of the diode is 0V, and the potential at point A of the diode is VA = VOSP. UAP = VA - VP = UOSP, which is the voltage of the test source OSP. The voltage of the test source OSP can be collected through the ADC voltage acquisition circuit, that is, the voltage drop of the diode AP is collected. Then, the state of the pin (open circuit, short circuit, normal) can be judged according to the magnitude of the voltage drop of the diode.

[0072] Next, look at the lower diode testing process. Taking IOA as an example, the positive terminal of the constant current and voltage limiting source OSN passes through point G (system ground) to point N, then through the diode NA to point A, and then through SW_N0 back to the negative terminal of the test source OSN. This is the test current path. Since there is current passing through the diode NA, a voltage drop UNA will be generated. Because point N is grounded, VA = VOSN, that is, UNA = VN - VA = UOSN, which is the voltage of the test source OSN. The voltage of the test source OSN can be collected through the ADC voltage acquisition circuit, that is, the voltage drop of the diode NA is collected. Then, the state of the pin (open circuit, short circuit, normal) can be judged according to the magnitude of the voltage drop of the diode. Only one test source is turned on during the testing process of the test source OSP and the test source OSN, while the other test source is in the off state. The current loop of the power diode testing process is similar to the path of the lower diode loop.

[0073] The voltage acquisition circuit is used to collect the voltage drop generated by the constant current and voltage limiting source during the testing process due to the test diode acting as a load, and judge the state of the pin to be tested according to the voltage drop. In this embodiment, since the current output by the constant current and voltage limiting source is direct current, the voltage acquisition circuit can be a conventional direct current acquisition circuit. In this embodiment and the voltage acquisition circuit in Embodiment 1 are both set as the ADC voltage acquisition circuit.

[0074] Refer to Figure 4 In the multi-chip common ground model in, during the testing process of the chip to be tested, if there are multiple chips that need to be functionally tested at the same time, for example, when testing the registers inside a camera with image acquisition function to test whether the read function of the registers is normal. Since the number of registers is relatively large, it is necessary to test multiple chips where the registers are located at the same time. For example, when performing open / short circuit analysis on chip A, in order to enable chip B and chip N to continue to perform other function tests, it is necessary to connect and ground the grounding terminals (i.e., point N) of multiple chips.

[0075] For the open / short circuit test in Embodiment 1, when analyzing the lower diode, the switch SW_N4 between point N and GND needs to be disconnected. When performing single-chip testing or when the GNDs between chips are not connected together, it is similar to the positive / negative voltage open / short circuit test function. However, in the case of multi-chip common ground, when performing open / short circuit analysis, disconnecting SW_N4 means disconnecting the grounding of point N of all chips, that is, except for the chip under test, all other chips cannot perform other function tests. From the settings in Embodiment 2 combined with the principle of positive / negative voltage open / short circuit test, it can be known that when performing open / short circuit analysis on chip A, chip B and chip N can continue to perform other function tests, and the circuits do not affect each other.

[0076] The implementation principle of the chip pin open / short circuit test device based on positive / negative voltage in the embodiments of the present application is as follows: When measuring specific pins on the chip under test, the constant current and voltage limiting source supplies appropriate voltage and current. The switch corresponding to the pin to be measured in the switch matrix is closed, and the current flows. Since there is a test diode corresponding to the pin as a load, a voltage drop is generated. The voltage acquisition circuit acquires the voltage drop generated during the test, and judges the state of the pin through the voltage drop to determine whether the pin of the chip under test is open circuit, short circuit or normal, enabling measurement of each pin of the chip under test to perform detection after the chip is packaged.

[0077] Another embodiment of the present application also discloses a method for testing the open circuit of chip pins based on positive / negative voltage, including:

[0078] S110. The constant current and voltage limiting source provides a limited voltage and a constant current during the test. The voltage limiting value of the voltage and the constant current value of the current can be set for different chips under test. The chips under test include power pins, ground pins and pins to be measured. The power pin is set as point P, and the ground pin is set as point N.

[0079] S120. The test diodes are connected to the upper pins, lower pins, point P and point N of the chip under test, and are used as loads for measuring the states of the upper pins and lower pins of the chip under test.

[0080] S130. The switch matrix controls the on / off of different test diodes, including switches corresponding to each test diode. Each switch is respectively connected to the constant current and voltage limiting source and the test diode. The on / off of different test diodes is realized through the combination of different switches. Point P of the chip under test is connected to the switch matrix, and point N of the chip under test is grounded together.

[0081] S140. The voltage acquisition circuit acquires the voltage drop generated by the constant current and voltage limiting source during the test due to the test diode as a load, and judges the state of the pin to be measured through the voltage drop.

[0082] The implementation principle of the chip pin open - short circuit test method based on positive and negative voltages in the embodiments of this application is as follows: When measuring specific pins on a chip under test, a constant - current and voltage - limiting source supplies an appropriate voltage and current. The switch corresponding to the pin under test in the switch matrix closes, and current flows. Since there is a test diode corresponding to the pin as a load, a voltage drop is generated. The voltage acquisition circuit acquires the voltage drop generated during the test, and judges the state of the pin based on the voltage drop to determine whether the pin of the chip under test is open - circuited, short - circuited, or normal, enabling measurement of each pin of the chip under test for post - packaging detection of the chip.

[0083] The test diode includes an upper diode, a lower diode, and a power supply diode. The test diode is connected to the upper pin, lower pin, point P, and point N of the chip under test, and measures the states of the upper pin and the lower pin of the chip under test, including:

[0084] The upper diode serves as an upper load when measuring the chip under test. The two ends of the upper diode are respectively connected to the pin under test of the chip under test and point P.

[0085] The lower diode serves as a lower load when measuring the chip under test. The two ends of the lower diode are respectively connected to the pin under test of the chip under test and point N.

[0086] The power supply diode is used as a power - supply - end load when measuring the chip under test. The two ends of the power supply diode are connected to point N and point P.

[0087] The constant - current and voltage - limiting source includes a positive - voltage constant - current and voltage - limiting source and a negative - voltage constant - current and voltage - limiting source. The constant - current and voltage - limiting source provides a limited voltage and a constant current during the test, including:

[0088] The positive - voltage constant - current and voltage - limiting source supplies power to the test diode from the pin under test to point P.

[0089] The negative - voltage constant - current and voltage - limiting source supplies power to the test diode from the pin under test to point N, and also supplies power to the test diode from point P to point N.

[0090] The above are all preferred embodiments of this application. Without restricting the protection scope of this application accordingly, therefore: All equivalent changes made according to the structure, shape, and principle of this application should be covered within the protection scope of this application.

Claims

1. A short - circuit and open - circuit test device for chip pins based on positive and negative voltages, characterized in that, Comprising: A chip under test, the chip under test includes a power pin, a ground pin and a pin under test, the power pin is set as point P, and the ground pin is set as point N; A constant current and voltage limiting source, used to provide a limited voltage and a constant current during the test, and the voltage limiting value of the voltage and the constant current value of the current are both set for different chips under test; A test diode, connecting the pin under test, point P and point N of the chip under test, and used as a load for measuring the pin under test; A switch matrix, used to control the on-off of different test diodes, including switches corresponding to each test diode, each switch is respectively connected to the constant current and voltage limiting source and the test diode, and the on-off of different test diodes is realized through the combination of different switches. Point P of the chip under test is connected to the switch matrix, and point N of the chip under test is grounded; A voltage acquisition circuit, used to acquire the voltage drop generated by the test diode as a load during the test by the constant current and voltage limiting source, and judge the state of the pin under test through the voltage drop; Wherein, the test diode includes an upper diode, a lower diode and a power diode; The upper diode is used as an upper load when measuring the chip under test, and both ends of the upper diode are respectively connected to the pin under test of the chip under test and point P; The lower diode is used as a lower load when measuring the chip under test, and both ends of the lower diode are respectively connected to the pin under test of the chip under test and point N; The power diode is used as a power supply end load when measuring the chip under test, and both ends of the power diode are connected to point N and point P; Wherein, the constant current and voltage limiting source includes: A positive voltage constant current and voltage limiting source, used to supply power to the test diode from the pin under test to point P; A negative voltage constant current and voltage limiting source, used to supply power to the test diode from the pin under test to point N, and supply power to the test diode between point P and point N; The G end of the positive voltage constant current and voltage limiting source is the negative end, and the G end of the negative voltage constant current and voltage limiting source is the positive end.

2. The short - circuit and open - circuit test device for chip pins based on positive and negative voltages according to claim 1, wherein, The switch matrix includes a positive end matrix and a negative end matrix: One ends of multiple switches of the positive end matrix are all connected to the positive end of the positive voltage constant current and voltage limiting source, and the other ends are respectively connected to the test diodes between point P and the pin under test of the chip under test, and are used to control the on-off of the test diode; One ends of multiple switches of the negative end matrix are all connected to the negative end of the negative voltage constant current and voltage limiting source, and the other ends are respectively connected to the test diodes between point N and the pin under test of the chip under test, and are used to control the on-off of the test diode, and are used to control the on-off of the test diodes between point P and point N.

3. The short - circuit and open - circuit test device for chip pins based on positive and negative voltages according to claim 1, characterized in that, One side of the positive voltage constant current and voltage limiting source is also provided with a positive end grounding switch connected to the G end of the positive voltage constant current and voltage limiting source, and one side of the negative voltage constant current and voltage limiting source is also provided with a negative end grounding switch connected to the G end of the negative voltage constant current and voltage limiting source.

4. The short - circuit and open - circuit test device for chip pins based on positive and negative voltages according to claim 1, wherein, A plurality of chips to be tested are provided, and the N points of the plurality of chips to be tested are all connected and grounded.

5. A method for testing open and short circuits of chip pins based on positive and negative voltages, characterized in that, Applied to the device according to any one of claims 1-4, comprising: A constant current and voltage limiting source provides a limited voltage and a constant current during the test. The voltage limiting value and the constant current value are set for different chips to be tested. The chip to be tested includes a power pin, a ground pin, and a pin to be tested. The power pin is set as point P, and the ground pin is set as point N; The test diode is connected to the upper pin, the lower pin, point P, and point N of the chip to be tested, and is used as the load for measuring the upper pin and the lower pin of the chip to be tested; The switch matrix controls the on / off of different test diodes, including switches corresponding to each test diode. Each switch is respectively connected to the constant current and voltage limiting source and the test diode. The on / off of different test diodes is achieved through the combination of different switches. Point P of the chip to be tested is connected to the switch matrix, and point N of the chip to be tested is grounded; The voltage acquisition circuit acquires the voltage drop generated by the test diode as a load during the test by the constant current and voltage limiting source, and judges the state of the pin to be tested through the voltage drop; Wherein, the test diode includes an upper diode, a lower diode, and a power diode.

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