Instruction execution method and apparatus

Abstract

The present disclosure provides an instruction execution method and device. The method comprises: obtaining state information of an instruction; and storing an operand of the instruction read to a data cache device when the instruction is cancelled based on the state information. The instruction execution method improves the instruction execution speed.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of computer, and in particular, to an instruction execution method and device. BACKGROUND

[0002] During the execution of an instruction, the corresponding operands are read from the register according to the analysis of the instruction, and then the data processing unit performs the relevant operation. Due to resource conflicts or data dependencies, the data processing unit cannot complete the corresponding operation, at which time the instruction that has been transmitted needs to be canceled, and after the factors hindering the execution of the instruction are eliminated, the canceled instruction will be reactivated, and the reactivated instruction will be executed as a new instruction, plus the operation at the time of the last cancellation of the instruction, which affects the speed of instruction execution. SUMMARY

[0003] The present disclosure provides an instruction execution method and device to at least solve the above technical problems in the prior art.

[0004] According to a first aspect of the present disclosure, an instruction execution method is provided, the method comprising:

[0005] obtaining state information of an instruction;

[0006] based on the state information, determining that the operand of the instruction that has been read is stored in a data cache device when the instruction is canceled.

[0007] In an implementation, the method further comprises:

[0008] based on the storage of the operand in the data cache device, updating the operand address in the instruction, and the updated operand address is the position of the operand in the data cache device.

[0009] In an implementation, the method further comprises:

[0010] storing the instruction with the updated operand address to an instruction cache device or returning the instruction queue.

[0011] In an implementation, the method further comprises:

[0012] based on the reactivation of the instruction, obtaining the operand address of the instruction;

[0013] reading the corresponding operand from the data cache device according to the operand address.

[0014] In an implementation, the method further comprises:

[0015] Based on the reactivation of the instruction, an address of the instruction is obtained, and based on the address of the instruction, the instruction cache device is accessed to obtain the instruction from the instruction cache device.

[0016] According to a second aspect of the present disclosure, an instruction execution device is provided, the device comprising:

[0017] an obtaining module configured to obtain state information of an instruction;

[0018] a cache module configured to, based on the state information, determine that the instruction is cancelled, and store an operand of the instruction read to a data cache device.

[0019] According to a third aspect of the present disclosure, a chip is provided, the chip comprising:

[0020] an instruction queue unit configured to transmit an instruction in an instruction queue;

[0021] a data cache device configured to store an operand read by the cancelled instruction;

[0022] wherein, when the cancelled instruction is reactivated, the corresponding operand is read from the data cache device.

[0023] In an implementation manner, the chip further comprises:

[0024] an instruction cache device configured to store the cancelled instruction, the instruction stored in the instruction cache device updates an operand address, and the updated operand address is a position of the operand in the data cache device;

[0025] wherein, when the cancelled instruction is reactivated, the instruction is read from the instruction cache device.

[0026] According to a fourth aspect of the present disclosure, a processor is provided, when the processor executes an instruction, the method of the present disclosure can be implemented.

[0027] According to a fifth aspect of the present disclosure, an electronic device is provided, comprising:

[0028] at least one processor; and

[0029] a memory connected with the at least one processor in communication; wherein,

[0030] the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of the present disclosure.

[0031] According to a fifth aspect of the present disclosure, a non-transitory computer readable storage medium storing computer instructions is provided, the computer instructions being used to cause the computer to perform the method of the present disclosure.

[0032] In the instruction execution method of the present disclosure, the state information of the instruction is acquired, and based on the state information, the operand of the instruction read is stored to the data cache device when the instruction is canceled. When the instruction is activated again, the corresponding operand is read from the data cache device, which can improve the instruction execution speed, reduce the reading of the register, and reduce the power consumption.

[0033] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0034] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0035] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0036] Figure 1 An implementation flowchart of an instruction execution method according to an embodiment of the present disclosure is shown;

[0037] Figure 2 A component structure diagram of an instruction execution device according to an embodiment of the present disclosure is shown;

[0038] Figure 3 A component structure diagram of a chip according to an embodiment of the present disclosure is shown;

[0039] Figure 4 A component structure diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] In order to make the purposes, features and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present disclosure.

[0041] Referring to Figure 1 The present embodiment provides an instruction execution method, which comprises:

[0042] acquire state information of the instruction;

[0043] based on the state information, store the read operand of the instruction to the data cache device when the instruction is cancelled.

[0044] In the instruction execution method of the present disclosure, state information of the instruction is acquired, and based on the state information, the read operand of the instruction is stored to the data cache device when the instruction is cancelled. The operand stored to the data cache device is used for reading when the instruction is activated again, and the operand is read from the data cache device instead of being read from the register again, so that the instruction execution speed is improved, the reading of the register is reduced, and the power consumption is reduced.

[0045] In an implementation manner, the instruction execution method of the present disclosure further includes: based on the operand being stored to the data cache device, updating the operand address in the instruction, and the updated operand address is the position of the operand in the data cache device. In the present disclosure, after the operand is stored to the data cache device, the operand address of the corresponding instruction is updated with the address of the operand in the data cache device, so that when the instruction is activated again, the corresponding operand can be quickly read from the data cache device according to the updated operand address, and the instruction execution speed is improved.

[0046] In an implementation manner, the instruction execution method of the present disclosure further includes: storing the instruction with the updated operand address to the instruction cache device or returning the instruction queue. After the operand address of the cancelled instruction is updated, the instruction is returned to the instruction queue again or stored to the instruction cache device, so as to activate the instruction again. When the cancelled instruction is stored to the instruction cache device, the instruction is read from the instruction cache device when the instruction is activated again, and the instruction execution speed is improved.

[0047] In an implementation manner, the instruction execution method of the present disclosure further includes: updating the address of the instruction after the cancelled instruction is stored to the instruction cache device. When the instruction is activated again, the instruction can be read from the instruction cache device according to the address of the instruction, and the instruction execution speed is improved.

[0048] In an implementation manner, the instruction execution method of the present disclosure further includes: monitoring the execution condition of the cancelled instruction, and activating the cancelled instruction when the factor hindering the execution of the instruction is eliminated. In the present disclosure, the instruction is cancelled due to factors such as resource conflict or data dependency, and the cancelled instruction is activated when the factor hindering the execution of the instruction is eliminated, for example, the data relied on by the instruction execution is calculated, or other instructions causing the resource conflict are executed, so that the instruction can continue to be executed. When the instruction is cancelled due to the resource conflict, the cancelled instruction can be delayed for one beat, so as to avoid the conflict and re-launch the instruction.

[0049] In an implementation, the instruction execution method further comprises: based on the instruction being reactivated, obtaining an operand address of the instruction; and reading a corresponding operand from the data cache device according to the operand address. When the instruction is reactivated, the corresponding operand can be read according to the operand address by analyzing the instruction. Since the operand address is updated to the address in the data cache device, the corresponding operand can be directly read from the data cache device, which can improve the instruction execution speed, reduce register reading, and reduce power consumption.

[0050] In an implementation, the instruction execution method further comprises: based on the instruction being reactivated, obtaining an address of the instruction, and obtaining the instruction from the instruction cache device based on the address of the instruction. In the embodiment of the disclosure, after the cancelled instruction is stored in the instruction cache device, the instruction can be obtained from the instruction cache device according to the address of the instruction when the instruction is reactivated, and the instruction is entered into the data processing unit from the instruction cache device, which improves the instruction execution speed.

[0051] Referring to Figure 2 The embodiment of the disclosure provides an instruction execution device, which comprises an obtaining module and a cache module. The obtaining module is configured to obtain state information of an instruction. The cache module is configured to store an operand of the instruction read when the instruction is cancelled into a data cache device based on the state information.

[0052] In the instruction execution device of the disclosure, the obtaining module obtains state information of an instruction, and the cache module stores an operand of the instruction read when the instruction is cancelled into a data cache device based on the state information. The operand stored in the data cache device is used to be read when the instruction is reactivated, and the operand does not need to be read from a register again. The corresponding operand can be read from the data cache device, which can improve the instruction execution speed, reduce the reading of the register, and reduce power consumption.

[0053] In an implementation, the instruction execution device further comprises an updating module configured to update an operand address in the instruction based on the operand being stored in the data cache device, and the updated operand address is a position of the operand in the data cache device.

[0054] In an implementation, the cache module of the instruction execution device is further configured to store the instruction with the updated operand address into an instruction cache device or return the instruction to an instruction queue.

[0055] In an implementation, the updating module of the instruction execution device is further configured to update an address of the instruction after the cancelled instruction is stored into the instruction cache device.

[0056] In an implementation, the instruction execution apparatus further comprises an activation module, which is configured to monitor the execution condition of the cancelled instruction, and activate the cancelled instruction when the factor impeding the execution of the instruction is eliminated.

[0057] In an implementation, the instruction execution apparatus further comprises a reading module, which is configured to acquire the operand address of the instruction based on the reactivation of the instruction, and read the corresponding operand from the data cache apparatus according to the operand address.

[0058] In an implementation, the reading module is further configured to acquire the address of the instruction based on the reactivation of the instruction, and acquire the instruction from the instruction cache apparatus based on the address of the instruction.

[0059] The instruction execution apparatus can implement the method of the above-mentioned embodiments, and the description of the above-mentioned embodiments can be used to understand and explain the apparatus of the embodiments. For the purpose of brevity and saving space, the description is not repeated here.

[0060] Referring to Figure 3 The chip comprises an instruction queue unit and a data cache apparatus. The instruction queue unit is configured to transmit the instruction in the instruction queue. The data cache apparatus is configured to store the operand read by the cancelled instruction. When the cancelled instruction is reactivated, the corresponding operand is read from the data cache apparatus.

[0061] After the instruction queue unit of the chip transmits the instruction, the corresponding operand can be read from the register according to the instruction. When the instruction is cancelled due to resource conflict or data dependency, the corresponding operand is stored in the data cache apparatus. When the instruction is reactivated, the corresponding operand is read from the data cache apparatus, which can improve the execution speed of the instruction, reduce the reading of the register, and reduce the power consumption.

[0062] In an implementation, the chip of the embodiment of the present disclosure further comprises: an instruction cache device configured to store the cancelled instruction, and the instruction stored in the instruction cache device updates the operand address, and the updated operand address is the position of the operand in the data cache device; and when the cancelled instruction is activated again, the instruction is read from the instruction cache device. In the chip of the embodiment of the present disclosure, after the operand is stored in the data cache device, the operand address of the instruction is updated by the address of the operand in the data cache device, so that when the instruction is activated again, the corresponding operand can be read from the data cache device according to the updated operand address, thereby improving the instruction execution speed. The cancelled instruction is stored in the instruction cache unit, and when the instruction is activated again, the instruction can be directly read from the instruction cache device, thereby shortening the instruction reading time and improving the instruction execution speed.

[0063] The chip of the embodiment of the present disclosure may, for example, be a matrix operation chip, and the process of executing instructions by the chip of the embodiment of the present disclosure will be described below with reference to the matrix operation as an example.

[0064] Referring to FIG. 3, the chip of the embodiment of the present disclosure comprises an instruction queue unit, a register, a data cache device, an instruction cache device, a data processing unit and a register bus. The instruction queue unit transmits instructions, and according to the analysis of the instructions, the corresponding operands are read from the register according to the operand addresses. The data processing unit performs corresponding operation on the operands according to the operation code of the instruction, such as matrix operation. When the operation cannot be performed due to resource conflict or data dependency, the instruction is cancelled. The operand of the instruction is stored in the data cache device, the operand address of the instruction is updated by the address of the operand in the data cache device, and the instruction with the updated operand address is stored in the instruction cache device. When the instruction is activated again, the corresponding operand is read from the data cache device according to the updated operand address of the instruction, the corresponding instruction is read from the instruction cache device, and the data processing unit performs corresponding operation on the operands according to the operation code of the instruction.

[0065] The chip of the embodiment of the present disclosure can implement the methods of the above-mentioned embodiments, and the descriptions of the above-mentioned method embodiments can be used to understand and explain the chip of the embodiment of the present disclosure. For the purpose of brevity and saving space, no further description is given here.

[0066] According to the embodiment of the present disclosure, the present disclosure further provides an electronic device and a readable storage medium.

[0067] Figure 4A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0068] like Figure 4 As shown, the device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a storage unit 408 into a random access memory (RAM) 403. Various programs and data required for the operation of the device 400 can also be stored in the RAM 403. The computing unit 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0069] Various components in device 400 are connected to I / O interface 405, including an input unit 406, such as a keyboard, mouse, etc.; an output unit 407, such as various types of displays, speakers, etc.; a storage unit 408, such as a magnetic disk, optical disk, etc.; and a communication unit 409, such as a network card, modem, wireless communication transceiver, etc. Communication unit 409 allows device 400 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0070] The computing unit 401 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, and the like. The computing unit 401 performs various methods and processes described above, such as the instruction execution method. For example, in some embodiments, the instruction execution method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 400 via the ROM 402 and / or the communication unit 409. When the computer program is loaded onto the RAM 403 and executed by the computing unit 401, one or more steps of the instruction execution method described above can be performed. Alternatively, in other embodiments, the computing unit 401 can be configured to perform the instruction execution method by any other appropriate means, such as by means of firmware.

[0071] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (PLD), a computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0072] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0073] In the context of this disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0074] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0075] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0076] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0077] It should be understood that the various forms of flow shown above can be used to reorder, add, or delete steps. For example, the steps described in the present disclosure can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present disclosure can be achieved, which are not limited herein.

[0078] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0079] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for executing an instruction, characterized in that: The method comprises: Get status information of the instruction; When it is determined based on the status information that the instruction is cancelled, storing the read operand of the instruction in a data cache device; Upon reactivation of the instruction, an operand address of the instruction is acquired; and according to the operand address, a corresponding operand is read from the data cache device; The method further comprises: Based on the operand being stored in the data cache device, the operand address in the instruction is updated, and the updated operand address is the position of the operand in the data cache device.

2. The method according to claim 1, characterized in that The method further comprises: The instruction with the updated operand address is stored in the instruction cache device or returned to the instruction queue.

3. The method according to claim 2, characterized in that The method further comprises: Based on the instruction being activated again, an address of the instruction is obtained, and based on the address of the instruction, the instruction cache device is provided, and the instruction is obtained from the instruction cache device.

4. An instruction execution device, characterized in that: The device comprises: The acquisition module is used to obtain the status information of the instruction; a cache module, configured to store the operand of the instruction read into a data cache device when determining that the instruction is cancelled based on the status information; The device further includes a reading module, the reading module being configured to obtain an operand address of the instruction upon reactivation of the instruction; and read a corresponding operand from the data cache device according to the operand address; The device further includes an updating module for updating the operand address in the instruction based on the operand being stored in the data cache device, wherein the updated operand address is the position of the operand in the data cache device.

5. A chip, characterized in that: The chip includes: An instruction queue unit, for issuing instructions in an instruction queue; a data cache device for storing operands read by the cancelled instruction; When the cancelled instruction is activated again, the corresponding operand is read from the data cache device according to the operand address; The chip further includes: The instruction cache device is used to store the cancelled instruction, the instruction stored in the instruction cache device updates the operand address, and the updated operand address is the position of the operand in the data cache device.

6. The chip according to claim 5, characterized in that When the cancelled instruction is activated again, the instruction is read from the instruction cache device.

7. A processor, characterized in that: When the processor executes the instructions, it can implement the method according to any one of claims 1 to 3.

8. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 3.

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