Method and apparatus for shared access of memory addresses

Abstract

A method for shared access of a memory address is performed by a computing device including a TEE, a first application located outside the TEE and a second application located inside the TEE, the first application using a first address space. The method comprises: receiving an interrupt notification from a virtual machine monitor of the computing device, the interrupt notification being sent by the virtual machine monitor when the second application requests to access a first address in the first address space; obtaining address mapping information of the first address according to a page table of the first application; and sending the address mapping information to the virtual machine monitor, so that the virtual machine monitor sets a first page table entry in a page table of the second application according to the address mapping information, the first page table entry being used to support the second application to access the first address.

Description

Technical Field

[0001] The embodiments in this specification belong to the field of computer technology, and in particular relate to a method and apparatus for sharing memory addresses. Background Technology

[0002] Virtualization solutions offer the flexibility to host heterogeneous operating systems on the same hardware platform, while implementing robust reliability and fault control mechanisms to ensure secure isolation between untrusted applications. A virtualization-based trusted execution environment (TEE) is essentially a system that uses a trusted virtual machine monitor (VMM; or hypervisor) to measure trusted applications and isolate trusted applications from the memory of untrusted operating systems. Summary of the Invention

[0003] The purpose of this invention is to provide a method and apparatus for sharing memory addresses.

[0004] A first aspect provides a shared access method for memory addresses, executed by a computing device, the computing device including a Trusted Execution Environment (TEE), wherein a first application located outside the TEE and a second application located within the TEE are running on the computing device, the first application using a first address space. The method includes: receiving an interrupt notification from a virtual machine monitor of the computing device, the interrupt notification being sent by the virtual machine monitor when the second application requests access to a first address in the first address space; obtaining address mapping information of the first address according to the page table of the first application; and sending the address mapping information to the virtual machine monitor, causing the virtual machine monitor to set a first page table entry in the page table of the second application according to the address mapping information, the first page table entry being used to support the second application's access to the first address.

[0005] Secondly, a shared memory address access device is provided, deployed in a computing device, the computing device including a Trusted Execution Environment (TEE), on which a first application located outside the TEE and a second application located within the TEE run, the first application using a first address space. The device includes: an interrupt handler configured to receive an interrupt notification from a virtual machine monitor of the computing device, the interrupt notification being sent by the virtual machine monitor when the second application requests access to a first address in the first address space; obtaining address mapping information of the first address according to the page table of the first application; and sending the address mapping information to the virtual machine monitor, causing the virtual machine monitor to set a first page table entry in the page table of the second application according to the address mapping information, the first page table entry being used to support the second application accessing the first address.

[0006] Thirdly, a computing device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method described in the first aspect.

[0007] Fourthly, a computer-readable storage medium is provided having a computer program stored thereon, wherein when the computer program is executed in a computing device, the computing device performs the method described in the first aspect.

[0008] In the above embodiments, applications located in the TEE can directly access the address space used by applications located outside the TEE, thereby enabling communication between applications located in the TEE and applications located outside the TEE without modifying the applications located outside the TEE or without pre-establishing a communication buffer. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments in this specification, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a system framework diagram of an exemplary virtualization solution provided in the embodiments of this specification;

[0011] Figure 2 This is a schematic diagram illustrating the mapping of virtual address space to physical address space via page tables, as provided in the embodiments of this specification.

[0012] Figure 3This document describes the flowchart of a shared memory address access method provided in the embodiments of this specification.

[0013] Figure 4 This is a schematic diagram illustrating the process of obtaining address mapping information as exemplarily provided in the embodiments of this specification;

[0014] Figure 5 This is a schematic diagram of a shared memory address access device provided in the embodiments of this specification. Detailed Implementation

[0015] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0016] Figure 1 This is a system framework diagram of an exemplary virtualization solution provided in the embodiments of this specification. Please refer to [link / reference]. Figure 1 As shown, a hypervisor can directly manage the hardware resources of a computing device. Multiple operating systems, such as OS_A and OS_B, can run on a processor virtualized by the hypervisor, sharing the hardware resources virtualized by the hypervisor. Besides coordinating access to hardware resources, the hypervisor can also impose protection between different operating systems, achieving software-based security isolation; for example, it can securely isolate OS_A and its dependent application C1 from OS_B and its dependent application C2. In other words, unlike hardware-based security isolation technologies such as Software Guard Extensions (SGX) and Trustzones, the hypervisor essentially provides software-based security isolation. Therefore, to some extent, the execution environment of OS_A and its dependent application C1 can be described as a non-TEE, while the execution environment of OS_B, which is securely isolated from OS_A, and its dependent application C2 can be described as a TEE relative to the aforementioned non-TEE.

[0017] To enable applications located within a TEE, such as application C2, to communicate with applications outside the TEE, such as application C1, a communication buffer can be pre-set in the non-TEE, and pages belonging to this communication buffer can be set to not be swapped out by the operating system OS_A. When application C2 needs to communicate with application C1, it requests access to the aforementioned communication buffer. At this point, because the page table and / or EPT page table initially created by the Hypervisor for application C2 does not have a mapping relationship between the communication buffer and the physical address / machine address, the Hypervisor will interrupt the execution of application C2. Simultaneously, based on the page table entries of the pages belonging to the communication buffer, it will set page table entries in the page table and / or EPT page table used by application C2 to support application C2's access to the communication buffer, and allow the processor to continue executing application C2 to complete its access to the communication buffer, thereby completing the communication between application C2 and application C1.

[0018] This implementation requires a communication buffer to be pre-established in a specific way, and the application located outside the TEE needs to be modified so that it can access the communication buffer in an address space that is not originally used by itself, so that it can write the data that needs to be communicated into the communication buffer and read the data written by the application in the TEE from the communication buffer.

[0019] This specification also provides another method and apparatus for sharing memory addresses in the embodiments, in which an application located in the TEE can directly access the address space used by an application located outside the TEE, thereby enabling communication between an application located in the TEE and an application located outside the TEE without modifying the application located outside the TEE or without pre-establishing a communication buffer.

[0020] The following text will combine specific examples. Figure 1 The system framework described in this specification provides detailed technical solutions in the embodiments.

[0021] See Figure 1As shown, the shared memory address access device provided in any embodiment of this specification can first be installed in the non-TEE operating system OS_A. This device can also be described as a shared memory communication driver, so as to implement the shared memory address access method provided in any embodiment of this specification based on the device. During or after the installation of the device, the device can send a registration request to the memory management unit (MMU) of the operating system OS_A, so that the MMU can monitor the page table entries used by applications that depend on OS_A for changes. When the monitored page table entries detect changes such as a page being swapped out or a page being migrated, the MMU can actively return or receive a page table entry change notification from the device indicating that the corresponding page table entry has changed. For example, assuming OS_A is a Linux operating system, the registration request is actually used to trigger the MMU to enable the monitoring capability of change_pte in the Linux operating system's mmu_notifer mechanism. In addition, the device can register with the Hypervisor an interrupt handling function for receiving interrupt notifications from the Hypervisor. The purpose of registering the interrupt handling function, or the desired effect, will be described in detail later.

[0022] When application C1, which depends on operating system OS_A, is launched, OS_A can allocate the address space used by application C1; see also Figure 2 As shown, for example, OS_A can allocate pages 0 to N-1 in the virtual address space as the first address space for application C1, and then maintain the corresponding address space as follows: Figure 2 The page table a1 shown is used by application C1. Application C1 can also provide the mapping between application C1 and application C2 to the shared memory address access device, for example, by sending registration information containing the identifiers of application C1 and application C2 to the device. Furthermore, when application C1 starts, it can request the Hypervisor to reserve address space for application C2, which will be launched and corresponds to application C1. For example, application C1 or the shared memory address access device can request the Hypervisor to reserve pages N to 2N-1 in the virtual address space. When application C2, which depends on OS_B, is launched in a TEE (not a TEE), the Hypervisor allocates the reserved pages N to 2N-1 in the virtual address space to application C2. The Hypervisor can maintain the corresponding... Figure 2 Page table a2 shown is used by application C2.

[0023] It should be noted that page tables a1 and a2 in the aforementioned example are used to map the virtual address spaces allocated to applications C1 and C2 to their physical address spaces, respectively. In this case, the hypervisor also needs to maintain extended page tables (EPT) for applications C1 and C2, which are often referred to as EPT page tables, to map the corresponding physical addresses to real machine addresses. In some technical scenarios, it may also be possible to map the virtual address spaces used by applications C1 and C2 to real machine addresses through their respective page tables.

[0024] After completing the aforementioned process of launching application C1 (i.e., the first application) in a non-TEE environment and launching application C2 (i.e., the second application) in a TEE environment, see [link to relevant documentation]. Figure 3 As shown, the computing device can perform some or all of the following steps 31 to 34 through a shared access device for memory addresses deployed in, for example, the operating system OS_A, to complete the access of application C2 to the memory addresses in the first address space (e.g., page 0 to page N-1) used by application C1.

[0025] First, in step 31, an interrupt notification is received from the Hypervisor of the computing device, which is sent by the Hypervisor when application C2 requests access to a first address in the first address space.

[0026] When application C2 requests access to, for example, the first address in pages 0 through N-1, an MMU-related exception is triggered because the page tables and / or EPT page tables initially created by the Hypervisor do not support application C2's access to that first address. The Hypervisor's handling logic for this exception includes interrupting the execution of application C2, effectively rendering application C2 inoperable. Simultaneously, since the shared access device for the memory address installed in OS_A has registered its interrupt handler function for receiving interrupt notifications with the Hypervisor, the Hypervisor's exception handling logic also includes sending a corresponding interrupt notification to the shared access device for the memory address installed in OS_A. In other words, the shared access device for the memory address installed in OS_A can receive interrupt notifications from the Hypervisor through its registered interrupt handler function. Furthermore, it should be noted that the Hypervisor also records the identifier of the interrupted application C2 and the first address that application C2 requested to access.

[0027] Next, in step 32, the first address requested by application C2 is obtained from the Hypervisor.

[0028] The shared access device for the memory address installed in OS_A can send a query request corresponding to the interrupt notification to the Hypervisor, causing the Hypervisor to return the identifier of application C2 and the aforementioned first address, etc., which it has recorded. Alternatively, the identifier of application C2 and the aforementioned first address, etc., recorded by the Hypervisor, can be stored by the Hypervisor in a shared memory space. The shared access device for the memory address installed in OS_A can then read the identifier of application C2 and the first address requested by application C2, etc., written by the Hypervisor, from this shared memory space.

[0029] Next, in step 33, the address mapping information of the first address is obtained according to the page table of application C1.

[0030] Please see Figure 4 For example, the address mapping information of the first address can be obtained through the following steps 331 to 334.

[0031] Step 331: Based on the page number of the target page to which the first address belongs, determine the second page table entry corresponding to the target page from the page table of application C1.

[0032] Continuing with the example of applications C1 and C2 using address spaces ranging from pages 0 to 2N-1, with each page being 4KB in size, the page number P of the target page belonging to the first address can be calculated using the formula P = INT[A / L]. Here, A represents the first address, and L represents the page size, typically 4KB. Then, the second page table entry corresponding to the target page (i.e., page P) with page number P is retrieved from page table a1 maintained by OS_A for application C1.

[0033] Step 332: Determine whether the target page has been swapped in based on the valid bits in the table entries on the second page.

[0034] The second page table entry can include not only the page frame number of the target page frame corresponding to page P, but also a validity bit indicating whether the second page table entry is valid. For example, for a single page table entry of 32 bits, the high 20 bits may be used to store the page frame number, and one of the low 12 bits may be used as the validity bit. Furthermore, when the validity bit is 1, it indicates that the page table entry to which it belongs is valid; in this case, the high 20 bits may store a page frame number, indicating that the page corresponding to that page table entry has been swapped in. When the validity bit is 0, it indicates that the page table entry to which it belongs is invalid; in this case, regardless of whether the high 20 bits store a page frame number, it indicates that the page corresponding to that page table entry has not been swapped in. It should be noted that in some technical scenarios, the page table entry of the target page may not store the page frame number but directly indicate the actual machine address corresponding to the target page.

[0035] If the target page has been swapped in, proceed directly to step 334 below; otherwise, proceed to steps 333 and 344 below in sequence.

[0036] Step 333: A page swapping request is sent to the MMU of the operating system on which application C1 depends, causing the MMU to swap in the target page. After the target page is swapped in, the corresponding page frame number will be stored in the second page table entry, and the valid bit in that second page table entry will be set to a value indicating that the second page table entry is valid. For example, please continue to see... Figure 2 Assuming the target page P is page 1, the value of the valid bit in its corresponding page table entry may be 0. In this case, page 1 needs to be swapped in. That is, OS_A needs to select a page frame from the physical address space as the target page frame. The page frame number of the selected target page frame is stored in the high 20 bits of the page table entry corresponding to page 1, and the value of the valid bit is reset from 0 to 1.

[0037] Step 334: Obtain the address mapping information of the first address based on the second page table entry. This address mapping information may include, but is not limited to, the page frame number of the target page frame obtained from the second page table entry; for example, it may also include the page number P of the target page.

[0038] Back Figure 3 In step 34, address mapping information is sent to the Hypervisor.

[0039] As mentioned earlier, page table a2 of application C2 is managed by the Hypervisor. After receiving the address mapping information, the Hypervisor can add a first page table entry corresponding to the target page to page table a2. This first page table entry needs to store the page frame number included in the address mapping information, and the valid bit in the first page table entry needs to be set to a predetermined value indicating that the first page table entry is valid. Furthermore, it should be noted that the EPT page tables of both application C1 and application C2 are maintained by the Hypervisor. When page table a2 of application C2 changes, if an EPT page table exists for application C2, the Hypervisor also needs to update the EPT page table of application C2 accordingly. For example, if the page frame number included in the address mapping information is 3, and the EPT page table of application C1 records the machine address corresponding to the page frame with page frame number 3, then the Hypervisor also needs to add the machine address corresponding to the page frame with page frame number 3 to the EPT page table of application C2.

[0040] After the hypervisor completes updating the page tables and EPT page tables of application C2, it can continue executing application C2. For example, if the processor is executing instruction A belonging to application C1, and instruction A requests access to the first address in the virtual address space used by application C1, and the processor interrupts the execution of instruction A, then the hypervisor can continue executing instruction A belonging to application C2 from instruction A after completing updating the page tables and / or PT page tables of application C2.

[0041] Through the aforementioned process, applications located in the TEE can directly access the address space used by applications located outside the TEE, thereby enabling communication between applications located in the TEE and applications located outside the TEE without modifying the applications located outside the TEE or establishing a communication buffer in advance.

[0042] Based on steps 31 to 34 above, the target page to which the first address belongs may also be swapped out by OS_A or undergo page migration, allowing the target page frame originally corresponding to the target page to be used for other transactions. Referring to the preceding description, the shared access device for memory addresses sends a registration request to the MMU, enabling the MMU to proactively return or receive a page table entry change notification from the device when it detects a page being swapped out or migrated by monitoring changed page table entries. Therefore, to ensure that the target page frame originally corresponding to the target page can be effectively used for other transactions, the computing device can further execute steps 35 to 37 based on the shared access device for memory addresses.

[0043] In step 35, a page table entry change notification is received from the MMU of the operating system on which application C1 depends.

[0044] In step 36, it is determined whether the page table entry change notification is used to indicate a change to the second page table entry. For example, the page table entry change notification may include the page number of the page that was swapped out or migrated, the values ​​of the valid bits in the changed page table entry, and the page frame number in the changed page table entry, etc. The shared memory address access device can cache the address mapping information it has sent to the Hypervisor; furthermore, it can determine whether the page table entry change notification is used to indicate a change to the corresponding second page table entry by querying whether the cached address mapping information includes the page number included in the page table entry change notification.

[0045] If so, proceed to step 37, send a page table change notification to the Hypervisor, and cause the Hypervisor to update the first page table entry and refresh the translation back buffer of the page table of application C2 according to the page table entry change notification.

[0046] When the target page is swapped out by OS_A, the Hypervisor can, for example, set the valid bit in the first page table entry corresponding to the target page in page table a2 of application C2 to a value that indicates that the first page table entry is invalid, or directly delete the first page table entry corresponding to the target page from page table a2, thereby setting the first page table entry corresponding to the target page to invalid.

[0047] When a target page is migrated, the Hypervisor can, for example, update the page frame number in the first page table entry corresponding to the target page in page table a2 of application C2 to the page frame number included in the corresponding page table entry change notification.

[0048] Furthermore, by refreshing the translation back buffer of the first page table, application C2 can no longer access the page frame corresponding to the target page through page table a2, which was originally cached in the translation back buffer. It should also be noted that the Hypervisor can update application C2's EPT page table based on the settings of the first page table entries. For example, it can delete the mapping between page frame numbers and corresponding machine addresses in application C2's EPT page table, or modify the aforementioned mapping to the updated mapping between page frame numbers and corresponding machine addresses in the first page table entries.

[0049] Based on the same concept as the aforementioned method embodiments, this specification also provides a shared memory address access device deployed in a computing device, the computing device including a TEE, wherein a first application located outside the TEE and a second application located within the TEE are running in the computing device, the first application using a first address space. Figure 5 As shown, the device includes: an interrupt handling function 51 configured to receive an interrupt notification from the virtual machine monitor of the computing device, the interrupt notification being sent by the virtual machine monitor when the second application requests access to a first address in the first address space; obtain address mapping information of the first address according to the page table of the first application; send the address mapping information to the virtual machine monitor, causing the virtual machine monitor to set a first page table entry in the page table of the second application according to the address mapping information, the first page table entry being used to support the second application accessing the first address.

[0050] In one possible implementation, the interrupt handling function 51 is configured to determine a second page table entry corresponding to the target page from the page table of the first application based on the page number of the target page to which the first address belongs; determine whether the target page has been swapped in based on the valid bits in the second page table entry; and if the target page has been swapped in, obtain the address mapping information of the first address based on the second page table entry.

[0051] In one possible implementation, the interrupt handling function 51 is configured to send a page swapping request to the memory management unit of the operating system on which the first application depends if the target page has not been swapped in, so that the memory management unit swaps in the target page.

[0052] In one possible implementation, the apparatus further includes: a receiving unit 52 configured to receive a page table entry change notification from the memory management unit; a detection unit 53 configured to determine whether the page table entry change notification is used to indicate that the second page table entry has changed; and a notification unit 54 configured to send a page table change notification to the virtual machine monitor when the second page table entry has changed, so that the virtual machine monitor updates the first page table entry and refreshes the translation backup buffer of the page table of the second application according to the page table entry change notification.

[0053] In one possible implementation, the apparatus further includes: a registration unit 55, configured to send a registration request to the memory management unit, so that when the page table entry corresponding to a page belonging to the first address space is changed, the memory management unit returns a page table entry change notification indicating that the corresponding page table entry has been changed.

[0054] In one possible implementation, the address mapping information includes the page number of the target page to which the first address belongs, and the page frame number of the target page frame corresponding to the target page.

[0055] In one possible implementation, the apparatus further includes a registration unit 55 configured to register an interrupt handling function with the virtual machine monitor for receiving the interrupt notification from the virtual machine monitor.

[0056] In one possible implementation, the device is deployed within the operating system on which the first application depends.

[0057] While one or more embodiments of this specification provide the operational steps of the methods described in the embodiments or flowcharts, more or fewer operational steps may be included based on conventional or non-inventive means. The order of steps listed in the embodiments is merely one possible order of execution among many steps and does not represent the only possible order. In actual device or end product execution, the methods shown in the embodiments or drawings may be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment, or even a distributed data processing environment). The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, product, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, product, or apparatus. Without further limitations, the presence of other identical or equivalent elements in the process, method, product, or apparatus that includes the elements is not excluded. For example, the use of terms such as "first," "second," etc., is to denote names and does not indicate any particular order.

[0058] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0059] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0060] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0061] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0062] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0063] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage, graphene storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0064] Those skilled in the art will understand that one or more embodiments of this specification can be provided as a method, system, or computer program product. Therefore, one or more embodiments of this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0065] One or more embodiments of this specification can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a particular task or implement a particular abstract data type. One or more embodiments of this specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can reside in local and remote computer storage media, including storage devices.

[0066] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, system embodiments are basically similar to method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0067] The above description is merely an embodiment of one or more embodiments of this specification and is not intended to limit the scope of this specification. Various modifications and variations can be made to the one or more embodiments of this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims.

Claims

1. A method for shared access to memory addresses, the method being executed by a shared access device for memory addresses deployed in a computing device, the computing device including a Trusted Execution Environment (TEE), the computing device running a first application located outside the TEE and a second application located within the TEE, the device specifically deployed in a first operating system on which the first application depends, the first application using a first address space, the first address space not having a pre-configured communication buffer, the method comprising: Receive an interrupt notification from the virtual machine monitor of the computing device, the interrupt notification being sent by the virtual machine monitor when the second application requests access to a first address in the first address space; The address mapping information of the first address is obtained according to the page table of the first application; The address mapping information is sent to the virtual machine monitor, causing the virtual machine monitor to set a first page table entry in the page table of the second application according to the address mapping information. The first page table entry is used to support the second application to access the first address.

2. The method according to claim 1, wherein obtaining the address information of the first address according to the page table of the first application includes: Based on the page number of the target page to which the first address belongs, determine the second page table entry corresponding to the target page from the page table of the first application; Determine whether the target page has been swapped in based on the valid bits in the table entries on the second page; If the target page has been swapped in, obtain the address mapping information of the first address according to the second page table entry.

3. The method of claim 2, wherein obtaining address information of the first address according to the page table of the first application further comprises: If the target page is not swapped in, a page swapping request is sent to the memory management unit of the operating system on which the first application depends, so that the memory management unit swaps in the target page.

4. The method according to claim 2, after sending the address mapping information to the virtual machine monitor, the method further includes: Receive page table entry change notifications from the memory management unit of the operating system on which the first application depends; Determine whether the page table entry change notification is used to indicate that the second page table entry has been changed; If the second page table entry changes, a page table change notification is sent to the virtual machine monitor, causing the virtual machine monitor to update the first page table entry and refresh the translation backup buffer of the page table of the second application according to the page table change notification.

5. The method of claim 4, further comprising: A registration request is sent to the memory management unit, so that when the page table entry corresponding to a page belonging to the first address space is changed, the memory management unit returns a page table entry change notification indicating that the corresponding page table entry has been changed.

6. The method according to claim 1, wherein the address mapping information includes the page number of the target page to which the first address belongs, and the page frame number of the target page frame corresponding to the target page.

7. The method of any one of claims 1-6, further comprising: Register an interrupt handling function with the virtual machine monitor for receiving the interrupt notification from the virtual machine monitor.

8. A shared memory address access device deployed in a computing device, the computing device including a Trusted Execution Environment (TEE), wherein a first application located outside the TEE and a second application located within the TEE run in the computing device, the device being specifically deployed in a first operating system on which the first application depends, the first application using a first address space, the first address space not having a pre-configured communication buffer, the device comprising: An interrupt handler function is configured to receive an interrupt notification from the virtual machine monitor of the computing device, the interrupt notification being sent by the virtual machine monitor when the second application requests access to a first address in the first address space; and to obtain the address mapping information of the first address according to the page table of the first application. The address mapping information is sent to the virtual machine monitor, causing the virtual machine monitor to set a first page table entry in the page table of the second application according to the address mapping information. The first page table entry is used to support the second application to access the first address.

9. The apparatus of claim 8, the interrupt handling function is configured to determine a second page table entry corresponding to a target page to which the first address belongs from a page table of the first application according to a page number of the target page. Determine whether the target page has been swapped in based on the valid bits in the table entries on the second page; If the target page has been swapped in, obtain the address mapping information of the first address according to the second page table entry.

10. The apparatus of claim 9, wherein the interrupt handling function is configured to, if the target page has not been swapped in, send a page swapping request to the memory management unit of the operating system on which the first application depends, so that the memory management unit swaps in the target page.

11. The apparatus of claim 9, further comprising: The receiving unit is configured to receive page table entry change notifications from the memory management unit of the operating system on which the first application depends; The detection unit is configured to determine whether the page table entry change notification is used to indicate that the second page table entry has been changed; The notification unit is configured to send a page table change notification to the virtual machine monitor when the second page table entry is changed, so that the virtual machine monitor updates the first page table entry and refreshes the translation backup buffer of the page table of the second application according to the page table entry change notification.

12. The apparatus of claim 11, further comprising: The registration unit is configured to send a registration request to the memory management unit, so that when the page table entry corresponding to a page belonging to the first address space is changed, the memory management unit returns a page table entry change notification indicating that the corresponding page table entry has been changed.

13. The apparatus according to claim 8, wherein the address mapping information includes the page number of the target page to which the first address belongs, and the page frame number of the target page frame corresponding to the target page.

14. The apparatus of any one of claims 8-13, further comprising: The registration unit is configured to register an interrupt handling function with the virtual machine monitor for receiving the interrupt notification from the virtual machine monitor.

15. A computing device comprising a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program, implements the method of any one of claims 1-7.

16. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed in a computing device, the computing device performs the method of any one of claims 1-7.

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