Array substrate, display panel and display device

Abstract

The present invention discloses an array substrate, a display panel and a display device. The array substrate includes a display area and a non-display area, and at least a part of the non-display area surrounds the display area; the array substrate further includes a plurality of pixel circuits, the pixel circuits are located in the display area and are arranged in an array; at least two main power supply lines, the main power supply lines are located in the non-display area; a plurality of branch power supply lines, the branch power supply lines extend from the non-display area to the display area, and the branch power supply lines connect the pixel circuits and the main power supply lines for supplying the voltage signals provided by the main power supply lines to the pixel circuits; wherein, the main power supply lines connected by every two adjacent rows of pixel circuits are different. The technical solution provided by the embodiments of the present invention solves the problem of poor display between adjacent rows during the display of the display panel, and improves the display effect of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to an array substrate, a display panel, and a display device. Background Art

[0002] With the development of display technologies, display devices have been widely used, and people's requirements for display effects are also getting higher and higher. For a display panel, especially a large-sized display panel, there is a problem of poor display between adjacent rows during display, which affects the display effect of the display panel. Summary of the Invention

[0003] The present invention provides an array substrate, a display panel, and a display device to solve the problem of poor display between adjacent rows during display of the display panel, which affects the display effect of the display panel.

[0004] According to one aspect of the present invention, an embodiment of the present invention provides an array substrate, including a display area and a non-display area, and at least part of the non-display area surrounds the display area;

[0005] The array substrate further includes:

[0006] A plurality of pixel circuits, which are located in the display area and are arranged in an array;

[0007] At least two main power supply lines, which are located in the non-display area and are used to provide voltage signals for the pixel circuits;

[0008] A plurality of branch power supply lines, which extend from the non-display area to the display area, connect the pixel circuits and the main power supply lines, and are used to provide the voltage signals provided by the main power supply lines to the pixel circuits;

[0009] Wherein, the main power supply lines connected by every two adjacent rows of pixel circuits are different.

[0010] Optionally, the branch power supply lines include:

[0011] A plurality of first branch power supply lines, which are located in the display area and the pixel circuits are connected to the first branch power supply lines;

[0012] A plurality of second branch power supply lines, which are used to connect the first branch power supply lines and the main power supply lines.

[0013] Optionally, the first branch power supply lines extend along the row direction of the pixel circuits, the second branch power supply lines extend along the column direction of the pixel circuits, and the pixel circuits in the same row are connected to the same first branch power supply line;

[0014] Wherein, the main power supply lines connected by every two adjacent first branch power supply lines are different.

[0015] Optionally, the array substrate includes N first branch power lines and M power lines, where M < N, M is an integer greater than or equal to 2, and N is an integer greater than 2.

[0016] The n-th first branch power line is connected to the i-th power line, where 1 ≤ n ≤ N, 1 ≤ i ≤ M, n = aM + i, a is a non-negative integer, and a = 0, 1, ……, |N / M|.

[0017] Optionally, every two adjacent first branch power lines are parallel to each other.

[0018] Every two adjacent main power lines are parallel to each other.

[0019] Optionally, the extending direction of the main power line is the same as that of the first branch power line.

[0020] The main power line is perpendicular to the second branch power line.

[0021] Preferably, the voltage signals provided by each main power line are the same.

[0022] Optionally, the non-display area further includes a connection terminal setting area and a first non-display area disposed opposite to the connection terminal setting area.

[0023] All or part of the main power lines are located in the first non-display area; or

[0024] All or part of the main power lines are located in the connection terminal setting area.

[0025] Preferably, at least two main power lines are disposed in the connection terminal setting area.

[0026] Optionally, the main power line includes an initialization bus; the branch power line includes an initialization signal line.

[0027] According to the second aspect of the present invention, an embodiment of the present invention provides a display panel, including the array substrate arbitrarily proposed in the first aspect.

[0028] According to the third aspect of the present invention, an embodiment of the present invention provides a display device, including the array substrate arbitrarily proposed in the first aspect or the display panel proposed in the second aspect.

[0029] The technical solution provided by the embodiment of the present invention supplies voltage signals to the pixel circuits by providing at least two main power supply lines located in the non-display area. By providing a plurality of branch power supply lines extending from the non-display area to the display area and connecting between the pixel circuits and the main power supply lines, the main power supply lines connected to the adjacent two rows of pixel circuits are different, so that after one main power supply line transmits a voltage signal to the first row of pixel circuits, another main power supply line transmits a voltage signal to the third row of pixel circuits, and there is at least one empty row time for the main power supply line that transmits the voltage signal to the first row of pixel circuits. When the second row of pixel circuits is supplied with a voltage signal by another main power supply line, the main power supply line that supplies the voltage signal to the first row of pixel circuits can restore the amplitude of the voltage signal to the target voltage amplitude, so that after the same main power supply line transmits a voltage signal to the first row of pixel circuits, the amplitude of the voltage signal transmitted to the pixel circuits of non-adjacent rows is the target voltage amplitude. Such a setting makes the voltage signals of the adjacent two rows of pixel circuits as consistent as possible, reduces the difference in the received voltage signals of the adjacent two rows of pixel circuits, and further improves the display effect of the display panel.

[0030] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 is a schematic structural diagram of a display device provided in the prior art;

[0033] Figure 2 is a schematic structural diagram of a pixel circuit provided in the prior art;

[0034] Figure 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0035] Figure 4 is another schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0036] Figure 5 is another schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0037] Figure 6 is another schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0038] Figure 7 It is a schematic diagram of an initialization signal provided by an embodiment of the present invention;

[0039] Figure 8 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0040] Figure 9 It is a schematic structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0041] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0043] As mentioned in the background art, there are problems with poor display between adjacent rows when a display panel, especially a large-sized display panel, is displaying. Figure 1 It is a schematic structural diagram of a display device provided in the prior art. Figure 1 Exemplarily shows the setting situation of the array substrate 100 in the display panel 300. Figure 2 It is a schematic structural diagram of a pixel circuit provided in the prior art. Combining Figure 1 and Figure 2, the display panel 300 includes an array substrate 100 and a plurality of light-emitting units. The light-emitting units include light-emitting devices D1, and each light-emitting device corresponds to a pixel circuit 1. The array substrate 100 includes a first power supply line ELVDD, a second power supply line ELVSS, and an initialization line Vref. Each pixel circuit 1 is respectively connected to the first power supply line ELVDD, the second power supply line ELVSS, and the initialization line Vref. The pixel circuit 1 includes a plurality of thin-film transistors and a storage capacitor. The thin-film transistors may include a driving transistor T1 and a switching transistor. The driving transistor T1 and the light-emitting device D1 are sequentially connected between the first power supply line ELVDD and the second power supply line ELVSS. The driving transistor T1 can generate a driving current to drive the light-emitting device D1 connected to the pixel circuit 1 to emit light, and the switching transistor mainly functions as a switch.

[0044] See Figure 1 , the array substrate 100 may further include a plurality of scan signal lines Scan 1 - Scan n, a plurality of data signal lines Vdata 1 - Vdata n, a plurality of light-emitting control signal lines EM 1 - EM n, and a driving chip 30. The pixel circuit 1 is disposed in the area defined by the intersection of the scan signal lines Scan and the data signal lines Vdata. A scan signal is input to the corresponding pixel circuit 1 through the scan signal line Scan. Under the action of the scan signal input by the scan signal line Scan electrically connected thereto, the pixel circuit 1 connects to the corresponding data signal line Vdata electrically connected thereto. The driving chip 30 inputs a data signal to the corresponding pixel circuit 1 through the data signal line Vdata. The voltage of the data signal corresponds to the driving voltage and determines the light-emitting brightness of the light-emitting device D1, that is, determines the display gray scale of the light-emitting device D1. It should be noted that the driving transistor, the switching transistor, and the storage capacitor can form various forms of pixel circuits 1 in various connection relationships. Figure 2 The pixel circuit 1 shown is only an example, and it can also be other forms of pixel circuits, such as 3T1C pixel circuits, 7T1C pixel circuits, and 8T2C pixel circuits, etc. Among them, T represents a transistor and C represents a capacitor. Figure 2 The case of the 7T1C pixel circuit is exemplarily shown, which is not a limitation on the pixel circuit 1.

[0045] Combined with Figure 1 and Figure 2, the first power supply line ELVDD can be used to transmit the first power signal, and the second power supply line ELVSS is used to transmit the second power signal. The voltage on the first power supply line ELVDD is usually a high-level voltage, and the voltage on the second power supply line ELVSS is usually a low-level voltage. During the light-emitting stage, the first power signal on the first power supply line ELVDD is applied to the first pole of the driving transistor T1, and the second power signal on the second power supply line ELVSS is applied to the second pole of the light-emitting device D1. For example, the second pole is the cathode. The first power signal and the second power signal serve as the power supply for the driving transistor T1 to generate a driving current, so that the driving transistor T1 generates a driving current to drive the light-emitting device D1 to emit light. The first power supply line ELVDD can be a signal line directly connected to one pole (such as the drain or source) of the driving transistor T1 in the pixel circuit 1, or a signal line indirectly connected to one pole of the driving transistor T1 in the pixel circuit 1 through a switching transistor (such as a light-emitting control transistor). The second power supply line ELVSS can be a signal line connected to the cathode of the light-emitting device D1. The initialization line Vref can be used to transmit an initialization signal to the pixel circuit 1. For example, the initialization line Vref can be connected to the gate and the storage capacitor of the driving transistor T1 through a switching transistor. The initialization signal is written into the gate and the storage capacitor of the driving transistor T1 through the initialization line Vref and the connected switching transistor, and the gate and the storage capacitor Cst of the driving transistor T1 are initialized to clear the residual charge of the previous frame of the display screen and avoid affecting the next frame of the display screen. The initialization line Vref can also be connected to the anode of the light-emitting device D1 through a switching transistor. The initialization signal is written into the anode of the light-emitting device D1 through the initialization line Vref and the connected switching transistor, and the potential of the anode of the light-emitting device D1 is initialized to clear the residual charge of the previous frame of the display screen and avoid affecting the next frame of the display screen.

[0046] The inventors have found through research that inconsistent electrical signals received between pixel circuits in different rows will affect the driving voltages of the pixel circuits in different rows, resulting in uneven display between rows of the display panel and affecting the display effect of the display panel.

[0047] Figure 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention. Refer to Figure 3, the array substrate 100 provided by the present invention includes a display area 10 and a non-display area 20, and the non-display area 20 at least partially surrounds the display area 10. The array substrate 100 further includes a plurality of pixel circuits 1, and the pixel circuits 1 are located in the display area 10 and are arranged in an array; at least two main power supply lines 2, the main power supply lines 2 are located in the non-display area 20, and the main power supply lines 2 are used to provide voltage signals for the pixel circuits 1; a plurality of branch power supply lines 3, the branch power supply lines 3 extend from the non-display area 20 to the display area 10, and the branch power supply lines 3 are used to connect the pixel circuits 1 and the main power supply lines 2; wherein, the main power supply lines 2 connected to each adjacent two rows of pixel circuits 1 are different.

[0048] Specifically, the array substrate 100 provided in this embodiment is applied to a display panel, and the display panel can be used to display an image. Therefore, the display area 10 of the array substrate 10 corresponds to the area of the display panel for displaying the image, including the pixel circuit 1 and a light-emitting device ( Figure 3 not shown in the figure), etc., and the light-emitting device is driven to emit light through the pixel circuit 1; the non-display area 20 of the array substrate 10 corresponds to the area of the display panel where no image is displayed, including the main power supply line 2, etc., and the main power supply line 2 can be a signal line such as ELVDD, initialization bus, etc., and no limitation is made here. Figure 3 Exemplarily, 3 main power supply lines 2 are shown to be located in the non-display area 20, and the 3 main power supply lines 2 can be located on the same border or different borders of the non-display area 10. It should be noted that, Figure 3 Exemplarily, the case where 3 main power supply lines 2 are located on different borders of the non-display area is shown, and no limitation is made here. The first end of the branch power supply line 3 is connected to the pixel circuit 1, and the second end of the branch power supply line 3 is connected to the main power supply line 2, and the branch power supply line 3 is used to transmit the voltage signal on the main power supply line 2 to the pixel circuit 1.

[0049] During the display stage of the display panel 300, a voltage signal with a target voltage amplitude is transmitted from the main power supply line 2 to the pixel circuits 1 in the Nth row. After the voltage signal on the main power supply line 2 is transmitted to the pixel circuits 1 in the Nth row with the target voltage amplitude, since the voltage signal transmitted on the main power supply line 2 is transmitted to the pixel circuits 1 through the branch power supply line 3, there will be a voltage drop in the voltage signal transmitted on the main power supply line 2. By setting the main power supply lines 2 connected to each adjacent two rows of pixel circuits 1 to be different, when the main power supply line 2 transmits a voltage signal to the (N + 1)th row, a main power supply line 2 different from the main power supply line 2 that transmits a voltage signal with a target voltage amplitude to the pixel circuits 1 in the Nth row can be used. Such a setting enables the main power supply line 2 that transmits a voltage signal with a target voltage amplitude to the pixel circuits 1 in the Nth row to have sufficient time to recover to the target voltage amplitude.

[0050] This enables the pixel circuits 1 in the Nth row and the pixel circuits 1 in the (N + 1)th row to receive voltage signals with the target voltage amplitude, making the difference between the voltage signals received by adjacent rows of pixel circuits 1 relatively small, and making the voltage signals received by the pixel circuits 1 in different rows as consistent as possible. Such a setting makes the driving voltage signals output by the pixel circuits 1 in different rows as consistent as possible, making the emission brightness of the light-emitting devices in different rows as consistent as possible, improving the display uniformity between rows of the display panel, and improving the display effect of the display panel.

[0051] The technical solution provided in this embodiment supplies voltage signals to the pixel circuits by setting at least two main power supply lines located in the non-display area. By setting multiple branch power supply lines extending from the non-display area to the display area and connecting them between the pixel circuits and the main power supply lines, the main power supply lines connected to adjacent rows of pixel circuits are different. After a main power supply line transmits a voltage signal to the pixel circuits in the first row, another main power supply line transmits a voltage signal to the pixel circuits in the third row, so that there is at least one empty row time for the main power supply line that transmits the voltage signal to the pixel circuits in the first row. When the pixel circuits in the second row receive the voltage signal from another main power supply line, the main power supply line that transmits the voltage signal to the pixel circuits in the first row can restore the amplitude of the voltage signal to the target voltage amplitude, so that after the same main power supply line transmits a voltage signal to the pixel circuits in the first row, the amplitude of the voltage signals transmitted to the pixel circuits in non-adjacent rows is the target voltage amplitude. Such a setting makes the voltage signals of adjacent rows of pixel circuits as consistent as possible, reduces the difference between the voltage signals received by adjacent rows of pixel circuits, and further improves the display effect of the display panel.

[0052] Figure 4 It is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. On the basis of the above embodiment, refer to Figure 4 In this embodiment, the branch power supply line 3 may include: multiple first branch power supply lines 31 located in the display area 10, and the pixel circuit 1 is connected to the first branch power supply line 31; multiple second branch power supply lines 32 for connecting the first branch power supply line 31 and the main power supply line 2.

[0053] Specifically, the first branch power supply line 31 located in the display area 10 is connected to the pixel circuit 1. The second branch power supply line 32 extends from the non-display area 20 to the display area 10. The first end of the second branch power supply line 32 is connected to the first branch power supply line 31, and the second end of the second branch power supply line 32 is connected to a main power supply line 2. The second branch power supply line 32 may be connected to one or more first branch power supply lines 31. Such a setting can facilitate wiring and facilitate the connection between the branch power supply line 3 and the pixel circuit 1.

[0054] It should be noted that Figure 4Exemplarily, it is shown that the array substrate 100 includes two main power supply lines 2, and the two main power supply lines 2 are respectively disposed at opposite two borders of the non-display area 20 of the array substrate 100, but no limitation is made here.

[0055] Optionally, on the basis of the above embodiment, continue to refer to Figure 4 , the first branch power supply line 31 extends along the row direction of the pixel circuit 1, and the second branch power supply line 32 extends along the column direction of the pixel circuit 1. The pixel circuits 1 in the same row are connected to the same first branch power supply line 31; wherein, the main power supply lines 2 connected by every two adjacent first branch power supply lines 31 are different.

[0056] Specifically, the pixel circuits 1 arranged in an array may include multiple rows and multiple columns. The first branch power supply line 31 in the display area 10 extends along the row direction of the pixel circuit 1, which is convenient for transmitting the same voltage signal along the row direction of the pixel circuit 1 to the pixel circuits 1 in the same row connected to the same first branch power supply line 31. The second branch power supply line 32 extends along the column direction of the pixel circuit 1. Such a setting is convenient for connecting the first branch power supply lines 31 extending along the row direction of the pixel circuit 1 along the column direction of the pixel circuit 1, and connecting two adjacent first branch power supply lines 31 to different main power supply lines 2. Such a setting is convenient for wiring on the array substrate, and the process is simple. In addition, such a setting enables the voltage signal transmitted on the main power supply line 2 to have sufficient time to recover to the voltage signal of the target voltage amplitude, further improving the pixel driving effect of the pixel circuits 1 in adjacent rows, making the light emitting effects of the light emitting devices in adjacent rows as consistent as possible, and improving the display effect of the display panel.

[0057] Figure 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. On the basis of the above embodiment, refer to Figure 5 , the array substrate 100 includes N first branch power supply lines 31 and M main power supply lines 2; wherein, M < N; M is an integer greater than or equal to 2, and N is an integer greater than 2; the nth first branch power supply line 31 is connected to the ith main power supply line 2; wherein, 1 ≤ n ≤ N, 1 ≤ i ≤ M, n = aM + i, a is a non-negative integer, and a = 0, 1,..., |N / M|.

[0058] Specifically, a is the quotient of N / M, and the remainder is i. |N / M| represents the integer part of N / M. The first first-branch power line 31 is connected to the first main power line 2, the second first-branch power line 31 is connected to the second main power line 2, the third first-branch power line 31 is connected to the third main power line 2, and so on. The nth first-branch power line 31 is connected to the ith main power line 2. This setting can increase the recovery time of the main power line 2 as much as possible, further improve the stability of the voltage signal transmitted by the main power line 2, and further improve the display effect of the display panel.

[0059] Exemplarily, referring to Figure 5 , taking the array substrate 100 including one hundred first-branch power lines 31 and two main power lines 2 as an example for illustration. The first first-branch power line 31 is connected to the first main power line 2, the second first-branch power line 31 is connected to the second main power line 2, the third first-branch power line 31 is connected to the first main power line 2, the fourth first-branch power line 31 is connected to the second main power line 2, and so on. The one-hundredth first-branch power line 31 is connected to the second main power line 2. This setting enables the pixel circuits 1 in the odd rows to transmit voltage signals through the first main power line 2, and the pixel circuits 1 in the even rows to transmit voltage signals through the second main power line 2. This setting enables the pixel circuits 1 in the odd rows and the even rows to transmit voltage signals by different main power lines 2, so that both the first main power line 2 and the second main power line 2 have time to recover the voltage while transmitting a row of voltage signals, improving the display effect of the display panel.

[0060] It should be noted that Figure 5 Exemplarily, it is shown that the array substrate 100 includes two main power lines 2, and the two main power lines 2 are arranged on the same side frame of the non-display area 20 of the array substrate 100. There is no limitation in this regard.

[0061] Optionally, on the basis of the above embodiments, continue to refer to Figure 5 , two adjacent first-branch power lines 31 are parallel to each other; two adjacent main power lines 2 are parallel to each other.

[0062] Specifically, such a setting facilitates the reasonable routing of each first branch power line 31 on the array substrate 100. On the other hand, each first branch power line 31 can be arranged in parallel along the row direction of the pixel circuit 1, which is convenient for fabricating the first branch power lines 31 using the same process. Optionally, two first branch power lines 31 are parallel to each other, and each first branch power line 31 can be arranged on the same layer, which is convenient for thinning the thickness of the array substrate. Adjacent main power lines 2 are parallel to each other, which can make the lengths of the second branch power lines 32 led out from different positions of the same main power line 2 more uniform, further improving the uniformity of the voltage signals transmitted on the second branch power lines 32 and further improving the display effect of the display panel.

[0063] Optionally, on the basis of the above embodiments, continue to refer to Figure 5 , the extending direction of the main power line 2 is the same as that of the first branch power line 31; the main power line 2 is perpendicular to the second branch power line 32.

[0064] Specifically, setting the main power line 2 perpendicular to the second branch power line 32 can make the length of the second branch power line 32 connected to the main power line 2 shorter, reducing the voltage drop of the voltage signals transmitted on the second branch power line 32. The extending direction of the main power line 2 is the same as that of the first branch power line 31, which is convenient for connecting multiple second branch power lines 32 to the same first branch power line 31, reducing the voltage drop at different positions of the first branch power line 31 and improving the uniformity of the voltage signals received by the pixel circuits 1 connected to different positions of the first branch power line 31, and further improving the display effect of the display panel.

[0065] Figure 6 FIG. is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. On the basis of the above embodiments, refer to Figure 6 , the non-display area 20 of the array substrate 100 provided in this embodiment may further include: a connection terminal setting area 201 and a first non-display area 202 disposed opposite to the connection terminal setting area; all or part of the main power line 2 is located in the first non-display area 202; or, all or part of the main power line 2 is located in the connection terminal setting area 201. Preferably, at least two main power lines 2 are disposed in the connection terminal setting area 201.

[0066] Specifically, at least two main power supply lines 2 are disposed in the connection terminal setting area 201, so that the main power supply lines 2 are convenient for connecting with the connection terminals and obtaining voltage signals from the driving chip. On the other hand, in order to reduce the border of the array substrate 100, the connection terminal setting area 201 can be disposed on the non-light-emitting side of the array substrate. Since the connection terminal setting area 201 fabricated on the non-light-emitting side of the array substrate is not limited by the border size, multiple main power supply lines 2 can be disposed in the connection terminal setting area 201, so that the recovery time of the voltage signals of the main power supply lines 2 is longer, further improving the stability of the signals transmitted on the main power supply lines 2 and the display effect of the display panel.

[0067] It should be noted that all or part of the main power supply lines 2 can be disposed in the first non-display area 202 according to needs; or, all or part of the main power supply lines 2 are disposed in the connection terminal setting area 201. Figure 6 Exemplarily, a case where the array substrate 100 includes three main power supply lines 2 and all three main power supply lines 2 are disposed in the connection terminal setting area 201 is shown, and no limitation is made here.

[0068] Preferably, on the basis of the above embodiment, continue to refer to Figure 6 , the voltage signals provided by each main power supply line 2 are the same.

[0069] Specifically, such a setting makes the voltage signals received by the pixel circuits 1 of different rows connected to different main power supply lines 2 as consistent as possible, further improving the display effect of the display panel.

[0070] Figure 7 is a schematic diagram of an initialization signal provided by an embodiment of the present invention. On the basis of the above embodiment, in combination with Figure 6 and Figure 7 , the main power supply line 2 can include an initialization bus; the branch power supply line 3 includes an initialization signal line.

[0071] Specifically, after the initialization bus transmits an initialization voltage signal to a row of pixel circuits 1, it takes a certain amount of time for the initialization signal line to restore the amplitude of the initialization voltage signal. Since the interval between the transmission times of the initialization signals of adjacent rows of pixel circuits 1 is less than the time required for the initialization bus to recover. By setting the initialization buses connected to adjacent rows of pixel circuits 1 differently, after an initialization bus transmits an initialization voltage signal to the first row of pixel circuits, another initialization bus transmits an initialization voltage signal to the third row of pixel circuits, so that there is at least one empty row time for the initialization bus that transmits the initialization voltage signal to the first row of pixel circuits. When the second row of pixel circuits is transmitted an initialization voltage signal by another initialization bus, the initialization bus that transmits the initialization voltage signal to the first row of pixel circuits can restore the amplitude of the initialization voltage signal to the target voltage amplitude, so that after the same initialization bus transmits an initialization voltage signal to the first row of pixel circuits, the amplitude of the initialization voltage signal transmitted to the pixel circuits of non-adjacent rows is the target voltage amplitude. Such a setting makes the initialization states of adjacent rows of pixel circuits as consistent as possible, reduces the difference in the initialization voltage signals received by adjacent rows of pixel circuits, and further improves the display effect of the display panel.

[0072] It should be noted that Figure 7 An exemplary situation of the initialization voltage signal transmitted by the initialization line is shown. Refer to Figure 7 , when the initialization buses connected to adjacent rows of pixel circuits are the same, the amplitude of the voltage signal of the initialization voltage signal Vref0 transmitted by the initialization bus at time t0 is the target voltage amplitude, and the amplitude of the voltage signal in the initial stage of Vref0 at time t1 does not reach the target voltage amplitude.

[0073] By setting the initialization buses connected to adjacent rows of pixel circuits 1 differently, for example, setting two initialization buses, after the same first initialization bus transmits an initialization voltage signal Vref1 to the first row of pixel circuits 1, it transmits an initialization voltage signal Vref1 to the third row of pixel circuits 1, so that there is one empty row time in the middle of the first initialization bus. When the second row of pixel circuits 1 is transmitted an initialization voltage signal Vref2 by the second initialization bus, the first initialization bus can restore the amplitude of the initialization voltage signal Vref1 to the target voltage amplitude, so that the amplitude of the initialization voltage signal Vref1 transmitted by the first initialization bus to the third row of pixel circuits 1 is the target voltage amplitude.

[0074] Such a setting makes the initialization voltage signals of adjacent rows of pixel circuits 1 as consistent as possible, reduces the difference in the initialization of adjacent rows of pixel circuits 1, and further improves the display effect of the display panel.

[0075] An optional application scenario is that in a large-sized array substrate, due to the large size of the large-sized array substrate, the initialization line is longer, the RC delay of the initialization line is larger, and the time required for the initialization voltage transmitted on the initialization line of the large-sized array substrate to recover to the target voltage is longer. By setting the initialization lines connected to adjacent rows of pixel circuits 1 to be different, the initialization voltage signals of the pixel circuits 1 in adjacent rows are made as consistent as possible, which preferably reduces the initialization difference between adjacent rows of pixel circuits 1 and further improves the display effect of the large-sized display panel.

[0076] Figure 8 FIG. is a schematic structural diagram of a display panel provided by an embodiment of the present invention. On the basis of the above embodiment, referring to Figure 8 , the display panel 300 provided by the embodiment of the present invention includes the array substrate 100 proposed in any of the above embodiments, and has the beneficial effects of the array substrate 100 proposed in any of the above embodiments, which will not be elaborated here, thereby improving the display effect of the medium and large-sized display panels.

[0077] Optionally, Figure 9 FIG. is a schematic structural diagram of a display device provided by an embodiment of the present invention. On the basis of the above embodiment, referring to Figure 9 , the display device 200 provided by the embodiment of the present invention includes the array substrate proposed in any of the above embodiments, or includes the display panel 300 proposed in any of the above embodiments, and has the beneficial effects of the array substrate 100 or the display panel 300 proposed in any of the above embodiments, which will not be elaborated here. The display device 200 includes terminals such as mobile phones, tablet computers, and wearable devices. It should be noted that Figure 9 only exemplarily shows the situation where the display device 200 includes the display panel 300 proposed in any of the above embodiments, and no limitation is made here.

[0078] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0079] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. An array substrate, characterized in that, It includes a display area and a non-display area, and at least part of the non-display area surrounds the display area; The array substrate further includes: A plurality of pixel circuits, which are located in the display area and arranged in an array; At least two main power supply lines, which are located in the non-display area; A plurality of branch power supply lines, which extend from the non-display area to the display area, and the branch power supply lines connect the pixel circuits to the main power supply lines for supplying the voltage signals provided by the main power supply lines to the pixel circuits; Wherein, the main power supply lines connected to every two adjacent rows of the pixel circuits are different; When the voltage signal of the second row of pixel circuits in two adjacent rows of pixel circuits is transmitted by another main power supply line, the main power supply line transmitting the voltage signal for the first row of pixel circuits in two adjacent rows of pixel circuits restores the amplitude of the voltage signal to the target voltage amplitude.

2. The array substrate according to claim 1, wherein The branch power supply lines include: A plurality of first branch power supply lines, which are located in the display area, and the pixel circuits are connected to the first branch power supply lines; A plurality of second branch power supply lines, which are used to connect the first branch power supply lines to the main power supply lines.

3. The array substrate according to claim 2, wherein The first branch power supply lines extend along the row direction of the pixel circuits, the second branch power supply lines extend along the column direction of the pixel circuits, and the pixel circuits in the same row are connected to the same first branch power supply line; Wherein, the main power supply lines connected to every two adjacent first branch power supply lines are different.

4. The array substrate according to claim 2, wherein The array substrate includes N first branch power supply lines and M main power supply lines; wherein, M < N; M is an integer greater than or equal to 2, and N is an integer greater than 2; The nth first branch power supply line is connected to the ith main power supply line; wherein, 1 ≤ n ≤ N, 1 ≤ i ≤ M, n = aM + i, a is a non-negative integer, and a = 0, 1, ……, |N / M|.

5. The array substrate according to claim 2, wherein Every two adjacent first branch power supply lines are parallel to each other; Every two adjacent main power supply lines are parallel to each other.

6. The array substrate according to claim 2, wherein The extending direction of the main power supply lines is the same as the extending direction of the first branch power supply lines; The main power supply lines are perpendicular to the second branch power supply lines.

7. The array substrate according to claim 6, characterized in that, The voltage signals provided by each of the main power supply lines are the same.

8. The array substrate according to claim 1, wherein The non-display area further includes: a connection terminal setting area and a first non-display area oppositely arranged to the connection terminal setting area; All or part of the main power supply lines are located in the first non-display area; or All or part of the main power supply lines are located in the connection terminal setting area.

9. The array substrate according to claim 8, wherein At least two of the main power supply lines are arranged in the connection terminal setting area.

10. The array substrate according to claim 1, wherein The main power supply lines include an initialization bus; The branch power supply lines include initialization signal lines.

11. A display panel, characterized in that, It includes: The array substrate according to any one of claims 1-10.

12. A display device, characterized in that, It includes: The display panel according to claim 11, or the array substrate according to any one of claims 1-10.

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