A method for manufacturing a dual-gate oxide layer PES-LDMOS

Abstract

The invention relates to the field of integrated circuit technology, and in particular to a method for fabricating a dual-gate oxide layer PES-LDMOS, comprising the following steps: S1: ion implantation on a P-type substrate; S2: ion implantation to form a P+ region, an N+ source region, and an N+ drain region; S3: etching away excess portions through an etching process; S4: growing SiO2; S5: growing a gate dielectric layer above the channel region; and S6: depositing metal above the gate dielectric layer to form a gate electrode. This method reduces the fixed hole charge in the gate dielectric layer above the channel, weakening its ability to attract electrons, thereby reducing the threshold voltage V th offset; secondly, the P+ region of the channel can also effectively suppress the formation of parasitic channels in STI, suppress the leakage current path, and reduce the turn-off current I off .

Description

Technical Field

[0001] The invention relates to the field of integrated circuit technology, and in particular to a method for manufacturing a dual-gate oxide layer PES-LDMOS. Background Art

[0002] Strictly speaking, the total dose effect, also known as the "Total Ionizing Dose" (TID), occurs when a large number of radiation particles enter the interior of semiconductor device materials, ionizing the material's extranuclear electrons and generating additional charge. This charge then accumulates in the device's oxide layer or induces interface states at the Si / SiO2 interface, leading to gradual degradation and eventual loss of device performance. In high-voltage power devices, where the gate oxide layer must be thicker, the TID effect is even more severe. The TID effect can cause a number of adverse phenomena in transistor devices, including threshold voltage drift, increased leakage current, and decreased mobility, degrading chip performance and rendering them inoperable. Summary of the Invention

[0003] (1) Problems to be solved

[0004] The invention is mainly used to solve the problems of threshold voltage drift, leakage current increase, mobility decrease, etc., and provides a method for manufacturing a dual-gate oxide layer PES-LDMOS.

[0005] (2) Technical solution

[0006] The present invention is a method for manufacturing a dual-gate oxide layer PES-LDMOS, comprising the following steps:

[0007] S1: Ion implantation is performed on a P-type substrate to form a P-well and an N-well respectively;

[0008] S2: Ion implantation is performed above the P-well to form two P+ regions and an N+ source region. The two P+ regions are located on both sides of the N+ source region. Ion implantation is performed in the N-well to form an N+ drain region. The right P+ region and the region above the P-type substrate are called the channel region.

[0009] S3: Etching the left side of the P-well and the upper left and upper right parts of the N-well through an etching process;

[0010] S4: growing SiO2 on the etched portion;

[0011] S5: growing a SiO2 gate dielectric layer and a high-K gate dielectric layer above the channel region, wherein both oxides are used as gate dielectric layers;

[0012] S6: depositing metal on the gate dielectric layer to form a gate electrode.

[0013] As a preferred technical solution, in step S1, a double-well CMOS process is used for ion implantation.

[0014] As a preferred technical solution, in step S2, the N+ drain region is formed by implanting high-concentration N+ doped ions into a designated area of the N well through an ion implantation process.

[0015] As a preferred technical solution, in step S5, the high-K gate dielectric layer and the SiO2 gate dielectric layer are both grown by thin film growth technology. The high-K gate dielectric layer is located on the left and is thinner, and the SiO2 gate dielectric layer is located on the right and is thicker.

[0016] As a preferred technical solution, in step S5, the gate dielectric layer is an insulating layer under the gate.

[0017] (3) Beneficial effects

[0018] The beneficial effects of the present invention are:

[0019] (1) Using a thin gate dielectric layer reduces the fixed hole charge in the gate dielectric layer above the channel, weakening its ability to attract electrons, thereby reducing the threshold voltage V th offset; secondly, the P+ region of the channel can also effectively suppress the formation of parasitic channels in STI, suppress the leakage current path, and reduce the turn-off current I off .

[0020] (2) Dual-gate oxide layer PES-LDMOS is based on ordinary LDMOS. P+ regions are added on both sides of the source region, forming a P+ layer on the channel surface. A thin HfO2 gate oxide layer is used above it. Other than that, it is the same as ordinary LDMOS.

[0021] (3) Since a dual gate oxide structure is used, the corresponding threshold voltage should be different. In order to make the threshold voltage corresponding to the thin gate oxide layer and the thick gate oxide layer the same, the threshold voltage V of the device can be adjusted by adjusting the thickness of the high-K gate dielectric layer and the doping concentration of the channel P+ layer. th , making it the same as ordinary LDMOS devices. Ordinary LDMOS and double-gate oxide layer PES-LDMOS can use the same power supply circuit without adding additional voltage divider circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 It is a cross-sectional schematic diagram of the present invention;

[0024] Figure 2 It is a flow chart of the production method of the present invention;

[0025] Figure 3 It is the transfer characteristic curve of ordinary LDMOS;

[0026] Figure 4 This is the output characteristic curve of ordinary LDMOS;

[0027] Figure 5 is the transfer characteristic curve of the present invention;

[0028] Figure 6 is the output characteristic curve of the present invention;

[0029] Figure 7 This is the transfer characteristic curve of ordinary LDMOS under TID effect simulation;

[0030] Figure 8 is the transfer characteristic curve of the present invention under TID effect simulation;

[0031] Figure 9 is the threshold voltage variation ΔV of the present invention th Relationship curve with TID;

[0032] Figure 10 The turn-off current I of the conventional LDMOS and the present invention is off Relationship curve with TID.

[0033] 1-P well; 2-P-type substrate; 3-N well; 4-P+ region; 5-N+ source region; 6-N+ drain region; 7-channel region; 8-SiO2; 9-high-K gate dielectric layer; 10-SiO2 gate dielectric layer; 11-gate electrode; 12-gate dielectric layer. DETAILED DESCRIPTION

[0034] The manufacturing method of the dual-gate oxide layer PES-LDMOS of the present invention is further described with reference to the accompanying drawings.

[0035] As shown in the accompanying drawings, a method for manufacturing a dual-gate oxide layer PES-LDMOS comprises the following steps:

[0036] S1: Perform ion implantation on the P-type substrate 2 to form a P-well 1 and an N-well 3 respectively;

[0037] S2: Ion implantation is performed above the P-well 1 to form two P+ regions 4 and an N+ source region 5. The two P+ regions 4 are located on both sides of the N+ source region 5. Ion implantation is performed in the N-well 3 to form an N+ drain region 6. The area above the right P+ region 4 and the P-type substrate 2 is called the channel region 7.

[0038] S3: Etching the left side of the P-well 1 and the upper left and upper right parts of the N-well 3 through an etching process;

[0039] S4: growing SiO28 on the etched portion;

[0040] S5: growing a SiO2 gate dielectric layer 10 and a high-K gate dielectric layer 9 above the channel region 7. Both oxides are used as the gate dielectric layer 12.

[0041] S6: depositing metal on the gate dielectric layer 12 to form the gate electrode 11 .

[0042] Furthermore, in step S1, a double-well CMOS process is used for ion implantation.

[0043] Furthermore, in step S2 , the N+ drain region 6 is formed by implanting high-concentration N+ doped ions into a designated region of the N well 3 through an ion implantation process.

[0044] Furthermore, in step S5, the high-K gate dielectric layer 9 and the SiO2 gate dielectric layer 10 are both grown by thin film growth technology. The high-K gate dielectric layer 9 is located on the left and is thinner, and the SiO2 gate dielectric layer 10 is located on the right and is thicker.

[0045] Furthermore, in step S5 , the gate dielectric layer 12 is an insulating layer under the gate.

[0046] The principle of the anti-TID effect of PES-LDMOS with double gate oxide layer is: using a thin gate dielectric layer to reduce the fixed hole charge in the gate dielectric layer above the channel, weakening its ability to attract electrons, thereby reducing the threshold voltage V th offset; secondly, the P+ region of the channel can also effectively suppress the formation of parasitic channels in STI, suppress the leakage current path, and reduce the turn-off current I off .

[0047] In order to better demonstrate the superiority of the present invention, the following comparative experiments were conducted:

[0048] a. Static characteristics simulation:

[0049] To verify the correctness of the established conventional LDMOS and dual-gate oxide PES-LDMOS, their transfer and output characteristic curves were first simulated. When simulating the transfer characteristic curve, the drain voltage was fixed at 12V and the gate voltage was swept from 0V to 5V. When simulating the output characteristic curve, the gate voltage was first swept to several fixed voltages, and then the drain voltage was swept from 0V to 12V. The static characteristic simulation results of conventional LDMOS and dual-gate oxide PES-LDMOS are detailed in the attached figure. Figures 3 to 6 .

[0050] Using the fixed current method, the threshold voltage V of the ordinary LDMOS is obtained from the ordinary LDMOS transfer characteristic curve. th is 1.004V, the shutdown current I off is 2.128×10 -15 A; From the transfer characteristic curve of the dual-gate oxide PES-LDMOS, the threshold voltage V of the dual-gate oxide PES-LDMOS is obtained. th is 1.015V, the shutdown current I off 5.501×10 -15 A.

[0051] b. TID effect simulation: After adding fixed holes inside and on the interface of the oxide corresponding to different irradiation doses, the transfer characteristic curves of the ordinary LDMOS double-gate oxide layer PES-LDMOS under different TID were simulated. See the attached figure for details. Figures 7-8 .

[0052] From the attached Figures 7-8 It can be seen that the ordinary LDMOS device is turned on when TID is greater than or equal to 100krad(Si), while the turn-off current I off When TID is greater than 100krad(Si), due to the influence of thick gate oxide layer, the turn-off current I off It gradually increases, but it is still higher than the turn-off current I of ordinary LDMOS devices. off It is 2 to 5 orders of magnitude smaller, indicating that under a certain TID, the dual-gate oxide layer PES-LDMOS has good anti-TID effect capability. The simulation results are as follows.

[0053] Table 1-1 Static characteristics of ordinary LDMOS under different TIDs

[0054]

[0055] Table 1-2 Static characteristics of dual-gate oxide PES-LDMOS under different TIDs

[0056]

[0057] It can be seen that when TID is equal to 100krad(Si), the threshold voltage V th is 0.903V, the shutdown current I off 1.151×10 -14A, compared with the threshold voltage without irradiation, it shifts 0.112V in the negative direction, and the turn-off current is about 10 orders of magnitude smaller than that of ordinary LDMOS. When TID is equal to 200krad(Si), the threshold voltage V th is 0.885V, the shutdown current I off is 1.937×10 -9 A, compared with the threshold voltage without irradiation, it shifts 0.130V in the negative direction, and the turn-off current is about 5 orders of magnitude smaller than that of ordinary LDMOS. When TID is equal to 300krad(Si), the threshold voltage V th is 0.746V, the shutdown current I off is 1.783×10 -7 A, compared with the threshold voltage without irradiation, it shifts 0.269V in the negative direction, and the turn-off current is about 4 orders of magnitude smaller than that of ordinary LDMOS. When TID is equal to 400krad(Si) and 500krad(Si), the dual-gate oxide layer PES-LDMOS is in the on state, and its turn-off current I off are 2.985×10 -6 A and 1.067×10 -5 A, but it is still about 2 to 3 orders of magnitude smaller than ordinary LDMOS.

[0058] Attachment Figures 9-10 is the threshold voltage variation ΔV between ordinary LDMOS and dual-gate oxide PES-LDMOS th and the shutdown current I off The relationship curve between TID and CMOS is shown in Figure 2. The results show that under certain TID, the dual-gate oxide PES-LDMOS has a good ability to strengthen the TID effect.

[0059] The examples described above are merely descriptions of preferred embodiments of the present invention and are not intended to limit the concept and scope of the present invention. Without departing from the design concept of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary persons in this field should fall within the scope of protection of the present invention. The technical contents for which protection is sought in the present invention have all been recorded in the claims.

Claims

1. A method for manufacturing a dual-gate oxide layer PES-LDMOS, characterized in that : The preparation method comprises the following steps: S1: performing ion implantation on a P-type substrate (2) to form a P-well (1) and an N-well (3); S2: performing ion implantation above the P-well (1) to form two P+ regions (4) and an N+ source region (5), wherein the two P+ regions (4) are located on both sides of the N+ source region (5), and performing ion implantation in the N-well (3) to form an N+ drain region (6). The right side of the P+ region (4) and the region above the P-type substrate (2) are called a channel region (7); S3: etching the left side of the P-well (1) and the upper left and upper right parts of the N-well (3) through an etching process; S4: growing SiO2(8) on the etched portion; S5: growing a SiO2 gate dielectric layer (10) and a high-K gate dielectric layer (9) above the channel region (7), both of which serve as a gate dielectric layer (12); the high-K gate dielectric layer (9) and the SiO2 gate dielectric layer (10) are both grown using a thin film growth technique, the high-K gate dielectric layer (9) being located on the left and being thinner than the SiO2 gate dielectric layer (10) located on the right; S6: depositing metal on the gate dielectric layer (12) to form a gate electrode (11).

2. The method for manufacturing a dual-gate oxide PES-LDMOS according to claim 1, wherein: In step S1, a double-well CMOS process is used for ion implantation.

3. The method for manufacturing a dual-gate oxide PES-LDMOS according to claim 1, wherein: In step S2, the N+ drain region (6) is formed by implanting high-concentration N+ doped ions into a designated region of the N well (3) through an ion implantation process.

4. The method for manufacturing a dual-gate oxide PES-LDMOS according to claim 1, wherein: In step S5, the gate dielectric layer (12) is an insulating layer under the gate.

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