A dual-Fin ESD protection device with a parasitic SCR

Abstract

The present invention discloses a dual-Fin ESD protection device with a parasitic SCR, which includes a single-Fin PNP transistor, a single-Fin NPN transistor, a third field oxide isolation region, a fourth field oxide isolation region, a fifth field oxide isolation region, a sixth field oxide isolation region, a first anode metal electrode, a second anode metal electrode, a first cathode metal electrode, and a second cathode metal electrode. The first anode metal electrode is disposed above the first N-type heavily doped region, the second anode metal electrode is disposed above the first P-type heavily doped region, the first cathode metal electrode is disposed above the second N-type heavily doped region, and the second cathode metal electrode is disposed above the second P-type heavily doped region. The single-Fin PNP transistor and the single-Fin NPN transistor are arranged side by side along the Y-axis direction to form a parasitic SCR structure. The present invention can effectively improve the robustness of small-size devices and ensure that the devices can be quickly and efficiently turned on when ESD occurs.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit electrostatic discharge protection devices, and relates to a dual-Fin ESD (Electrostatic Discharge) protection device with a parasitic SCR (Silicon Controlled Rectifier). Background Art

[0002] Since the invention of MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) more than sixty years ago, with the progress of semiconductor manufacturing processes, the gate length of devices has been continuously reduced, gradually from the early 0.18-micron process to the latest 7-nanometer process. The reduction in size has increased the operating speed of the chip, reduced the volume of the packaged chip, and at the same time has put forward higher requirements for the design of MOSFETs. When the gate length is reduced to less than 28 nanometers, due to its weak gate control ability and large leakage current, the mature planar transistor technology can no longer meet the requirements of small-size devices. In order to enable the planar transistor to continue to be applied in the small-size field, scientists have proposed various optimization schemes, such as strained silicon technology, replacing SiO2 with high-K materials, etc. After failing to achieve ideal results, a new device architecture, FinFET (Fin Field-Effect Transistor), was proposed.

[0003] FinFET devices have a special Fin-shaped thin silicon structure, so they have extremely strong gate control ability and small leakage current, which also enables Moore's Law to be followed to a certain extent. However, this Fin-shaped structure also reduces the effective silicon volume of the device. When electrostatic discharge occurs, the silicon volume available for discharging is small, and a large amount of current will flow through the narrow Fin, and the serious current aggregation effect will deteriorate the device robustness.

[0004] In the prior art, a dual-Fin GGNMOS device usually includes a drain-end metal electrode, a thin gate oxide layer, a polysilicon gate electrode, a source-end metal electrode, a drain-end N-type heavily doped region, a source-end N-type heavily doped region, and a P-type substrate, as Figure 1The figure shows a common type. When an ESD signal comes, the drain metal electrode is connected to the ESD signal, and the polysilicon gate electrode and the source metal electrode are connected to ground in parallel. The parasitic NPN transistor in the GGNMOS is used to discharge a large current. Since the double-Fin GGNMOS device has a relatively thin gate oxide layer, it is extremely vulnerable to device damage due to gate oxide breakdown when facing electrostatic discharge. In addition, a large amount of current will accumulate in the narrow Fin structure of the double-Fin GGNMOS device, which reduces the robustness of the device. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the prior art and provide a double-Fin ESD protection device with a parasitic SCR, which can meet the ESD protection requirements of small-size FinFET devices, effectively improve the robustness of small-size devices, and ensure that the device can be quickly and efficiently turned on when ESD occurs.

[0006] To solve the above technical problems, the present invention adopts the following technical solutions.

[0007] A double-Fin ESD protection device with a parasitic SCR includes a single-Fin PNP transistor, a single-Fin NPN transistor, a third field oxide isolation region, a fourth field oxide isolation region, a fifth field oxide isolation region, a sixth field oxide isolation region, a first anode metal electrode, a second anode metal electrode, a first cathode metal electrode, and a second cathode metal electrode; the third field oxide isolation region is disposed above the P-type substrate and the N-type well region on the right side of the single-Fin NPN transistor, the fourth field oxide isolation region and the fifth field oxide isolation region are sequentially disposed above the P-type substrate and the N-type well region between the single-Fin NPN transistor and the single-Fin PNP transistor, and the sixth field oxide isolation region is disposed above the P-type substrate and the N-type well region on the left side of the single-Fin PNP transistor; the first anode metal electrode is disposed above the first N-type heavily doped region, the second anode metal electrode is disposed above the first P-type heavily doped region, the first cathode metal electrode is disposed above the second N-type heavily doped region, and the second cathode metal electrode is disposed above the second P-type heavily doped region; the single-Fin PNP transistor and the single-Fin NPN transistor are arranged side by side in the Y-axis direction in sequence to form a parasitic SCR structure.

[0008] The single-Fin PNP transistor includes a first P-type heavily doped region, an N-type well region, a second field oxide isolation region, a P-type substrate, and a second P-type heavily doped region; the N-type well region is disposed in the P-type substrate, the first P-type heavily doped region is disposed above the N-type well region, the second P-type heavily doped region is disposed above the P-type substrate, and the second field oxide isolation region is disposed between the first P-type heavily doped region and the second P-type heavily doped region.

[0009] The described single-Fin NPN transistor includes a first N-type heavily doped region, an N-type well region, a first field oxide isolation region, a P-type substrate, and a second N-type heavily doped region. The first N-type heavily doped region is disposed above the N-type well region, the second N-type heavily doped region is disposed above the P-type substrate, and the first field oxide isolation region is disposed between the first N-type heavily doped region and the second N-type heavily doped region.

[0010] Further, the dual-Fin ESD protection device with parasitic SCR of the present invention includes an equivalent circuit. When the device starts to discharge, the path of the current therein is as follows: a part of the current flows into the collector and out of the emitter of the single-Fin PNP transistor Q1, that is, current I E1 to current I C1 ; a part of the current flows into the emitter and out of the collector of the single-Fin NPN transistor Q2, that is, current I C2 to current I E2 ; and another part of the current forms a positive feedback current loop between the single-Fin PNP transistor Q1 and the single-Fin NPN transistor Q2, that is, current I B1 to current I C2 and current I C1 to current I B2 .

[0011] The first anode metal electrode and the second anode metal electrode are connected in parallel, and the first cathode metal electrode and the second cathode metal electrode are connected in parallel to form a metal interconnection during ESD discharge.

[0012] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0013] 1. The protection device of the present invention parasitically has an SCR structure in the Y-axis direction. By utilizing the positive feedback effect after the SCR is turned on, the discharge capacity of the device is improved.

[0014] 2. A dual-Fin layout is adopted in the Y-axis direction, which is beneficial to strengthening the longitudinal movement of the current, alleviating the current aggregation effect in the narrow Fin, and thus suppressing the formation of local hot spots in the narrow Fin.

[0015] 3. The STI (Shallow trench isolation) technology is adopted to change the current path during device discharge, increase the utilization rate of the bulk silicon, and improve the robustness of the device.

[0016] 4. The present invention can directly adjust the layout parameters of the device according to actual requirements to facilitate separate design for different target scenarios. Description of the Drawings

[0017] Figure 1It is a schematic diagram of a dual-Fin GGNMOS structure in the prior art.

[0018] Figure 2 It is a schematic diagram of a structure of an embodiment of the present invention.

[0019] Figure 3 It is an equivalent circuit diagram of an embodiment of the present invention.

[0020] Wherein: 01, P-type substrate; 02, N-type well region; 03, first N-type heavily doped region; 04, second N-type heavily doped region; 05, first P-type heavily doped region; 06, second P-type heavily doped region; 07, first field oxide isolation region; 08, second field oxide isolation region; 09, third field oxide isolation region; 10, fourth field oxide isolation region; 11, fifth field oxide isolation region; 12, sixth field oxide isolation region; 13, first anode metal electrode; 14, second anode metal electrode; 15, first cathode metal electrode; 16, second cathode metal electrode. Detailed implementation manners

[0021] The present invention will be further described in detail below with reference to the accompanying drawings.

[0022] As Figure 1 shown, a dual-Fin GGNMOS device in the prior art includes a drain-end metal electrode, a thin gate oxide layer, a polysilicon gate electrode, a source-end metal electrode, a drain-end N-type heavily doped region, a source-end N-type heavily doped region, and a P-type substrate. When an ESD signal comes, the drain-end metal electrode is connected to the ESD signal, and the polysilicon gate electrode and the source-end metal electrode are connected in parallel to ground, and the parasitic NPN transistor in the dual-Fin GGNMOS is used for large-current discharge. Since the dual-Fin GGNMOS device has a relatively thin gate oxide layer, it is extremely vulnerable to device damage due to gate oxide breakdown when facing electrostatic discharge. In addition, a large amount of current will accumulate in the narrow Fin structure of the dual-Fin GGNMOS device, which will reduce the robustness of the device.

[0023] As Figure 2As shown in the figure, a dual-Fin ESD protection device with a parasitic SCR according to the present invention includes: a single-Fin PNP transistor, a single-Fin NPN transistor, a third field oxide isolation region 09, a fourth field oxide isolation region 10, a fifth field oxide isolation region 11, a sixth field oxide isolation region 12, a first anode metal electrode 13, a second anode metal electrode 14, a first cathode metal electrode 15, and a second cathode metal electrode 16. The third field oxide isolation region 09 is disposed above the P-type substrate 01 and the N-type well region 02 on the right side of the single-Fin NPN transistor. The fourth field oxide isolation region 10 and the fifth field oxide isolation region 11 are sequentially disposed above the P-type substrate 01 and the N-type well region 02 between the single-Fin NPN transistor and the single-Fin PNP transistor. The sixth field oxide isolation region 12 is disposed above the P-type substrate 01 and the N-type well region 02 on the left side of the single-Fin PNP transistor. The first anode metal electrode 13 is disposed above the first N-type heavily doped region 03. The second anode metal electrode 14 is disposed above the first P-type heavily doped region 05. The first cathode metal electrode 15 is disposed above the second N-type heavily doped region 04. The second cathode metal electrode 16 is disposed above the second P-type heavily doped region 06. The first anode metal electrode 13 and the second anode metal electrode 14 are connected in parallel, and the first cathode metal electrode 15 and the second cathode metal electrode 16 are connected in parallel to form a metal interconnection during ESD discharge.

[0024] The single-Fin PNP transistor and the single-Fin NPN transistor are placed side by side in the width direction (i.e., along the Y-axis) of the device to form a parasitic SCR structure in combination.

[0025] The present invention adopts the STI technology to separate the first N-type heavily doped region 03 and the second N-type heavily doped region 04 by the first field oxide isolation region 07; and separates the first P-type heavily doped region 05 and the second P-type heavily doped region 06 by the second field oxide isolation region 08.

[0026] The single-Fin PNP transistor includes a first P-type heavily doped region 05, an N-type well region 02, a second field oxide isolation region 08, a P-type substrate 01, and a second P-type heavily doped region 06. The N-type well region 02 is disposed in the P-type substrate 01. The first P-type heavily doped region 05 is disposed above the N-type well region 02. The second P-type heavily doped region 06 is disposed above the P-type substrate 01. The second field oxide isolation region 08 is disposed between the first P-type heavily doped region 05 and the second P-type heavily doped region 06.

[0027] The described single-Fin NPN transistor includes a first N-type heavily doped region 03, an N-type well region 02, a first field oxide isolation region 07, a P-type substrate 01, and a second N-type heavily doped region 04. The first N-type heavily doped region 03 is disposed above the N-type well region 02, the second N-type heavily doped region 04 is disposed above the P-type substrate 01, and the first field oxide isolation region 07 is disposed between the first N-type heavily doped region 03 and the second N-type heavily doped region 04.

[0028] As Figure 3 shown, the equivalent circuit diagram of a dual-Fin ESD protection device with a parasitic SCR according to the present invention. When the device starts to discharge, its current path is as follows: A part of the current flows from the emitter of the single-Fin PNP transistor Q1 into the collector and out, that is, current I E1 to current I C1 ; A part of the current flows from the collector of the single-Fin NPN transistor Q2 into the emitter and out, that is, current I C2 to current I E2 ; Another part of the current will form a positive feedback current loop between the single-Fin PNP transistor Q1 and the single-Fin NPN transistor Q2, that is, current I B1 to current I C2 and current I C1 to current I B2 , which makes the on-resistance of the device drop significantly and effectively enhances the discharge ability of the device.

[0029] In summary, compared with the dual-Fin GGNMOS structure of the prior art, the dual-Fin ESD protection device with a parasitic SCR provided by the present invention, on the one hand, parasitizes an SCR structure in the Y-axis direction, and utilizes the positive feedback effect after the SCR is turned on to improve the discharge ability of the device; in addition, the dual-Fin layout in the Y-axis direction can enhance the longitudinal movement of the current, relieve the current aggregation effect in the narrow Fin, and suppress the formation of local hot spots of the device; on the other hand, the protection unit adopts the STI technology, changes the current path when the device discharges, increases the utilization rate of the bulk silicon, and effectively improves the robustness of the device. The present invention can meet the ESD protection requirements of small-size FinFET devices, effectively improve the robustness of small-size devices, and ensure that the device can be quickly and efficiently turned on when ESD occurs.

Claims

1. A dual-Fin ESD protection device with a parasitic SCR, characterized in that, it includes a single-Fin PNP transistor, a single-Fin NPN transistor, a third field oxide isolation region (09), a fourth field oxide isolation region (10), a fifth field oxide isolation region (11), a sixth field oxide isolation region (12), a first anode metal electrode (13), a second anode metal electrode (14), a first cathode metal electrode (15), and a second cathode metal electrode (16); the third field oxide isolation region (09) is disposed above the P-type substrate (01) and the N-type well region (02) on the right side of the single-Fin NPN transistor, the fourth field oxide isolation region (10) and the fifth field oxide isolation region (11) are sequentially disposed above the P-type substrate (01) and the N-type well region (02) between the single-Fin NPN transistor and the single-Fin PNP transistor, and the sixth field oxide isolation region (12) is disposed above the P-type substrate (01) and the N-type well region (02) on the left side of the single-Fin PNP transistor; the first anode metal electrode (13) is disposed above the first N-type heavily doped region (03), the second anode metal electrode (14) is disposed above the first P-type heavily doped region (05), the first cathode metal electrode (15) is disposed above the second N-type heavily doped region (04), and the second cathode metal electrode (16) is disposed above the second P-type heavily doped region (06); the single-Fin PNP transistor and the single-Fin NPN transistor are arranged side by side in sequence along the Y-axis direction to form a parasitic SCR structure; the first anode metal electrode (13) and the second anode metal electrode (14) are connected in parallel, and the first cathode metal electrode (15) and the second cathode metal electrode (16) are connected in parallel to form a metal interconnection during ESD discharge.

2. The dual-Fin ESD protection device with a parasitic SCR according to claim 1, characterized in that, the single-Fin PNP transistor includes a first P-type heavily doped region (05), an N-type well region (02), a second field oxide isolation region (08), a P-type substrate (01), and a second P-type heavily doped region (06); the N-type well region (02) is disposed in the P-type substrate (01), the first P-type heavily doped region (05) is disposed above the N-type well region (02), the second P-type heavily doped region (06) is disposed above the P-type substrate (01), and the second field oxide isolation region (08) is disposed between the first P-type heavily doped region (05) and the second P-type heavily doped region (06).

3. The dual-Fin ESD protection device with a parasitic SCR according to claim 1, characterized in that, The described single-Fin NPN transistor includes a first N-type heavily doped region (03), an N-type well region (02), a first field oxide isolation region (07), a P-type substrate (01), and a second N-type heavily doped region (04); the first N-type heavily doped region (03) is disposed above the N-type well region (02), the second N-type heavily doped region (04) is disposed above the P-type substrate (01), and the first field oxide isolation region (07) is disposed between the first N-type heavily doped region (03) and the second N-type heavily doped region (04).

4. The dual-Fin ESD protection device with parasitic SCR according to claim 1, characterized in that, It includes an equivalent circuit. When the device starts to discharge, the path of the current inside it is as follows: a part of the current flows from the emitter of the single-Fin PNP transistor Q1 into the collector and out, that is, current I E1 to current I C1 ; a part of the current flows from the collector of the single-Fin NPN transistor Q2 into the emitter and out, that is, current I C2 to current I E2 ; and another part of the current forms a positive-feedback current loop between the single-Fin PNP transistor Q1 and the single-Fin NPN transistor Q2, that is, current I B1 to current I C2 and current I C1 to current I B2 .

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