High-efficiency vertical-cavity surface-emitting laser (VCSEL) chip with microlens

Abstract

The application discloses a high-efficiency vertical-cavity surface-emitting laser (VCSEL) chip with a microlens, which comprises a VCSEL unit, an oxidation isolation layer, a modulation unit and a microlens, wherein the oxidation isolation layer is arranged between the VCSEL unit and the modulation unit and is used for preventing the potential at the contact position of the two units from affecting the working current in the respective unit; and the microlens is arranged above the modulation unit and is used for shaping the light beam of the VCSEL unit so as to reduce the light beam divergence angle. The application breaks through the conventional technology by arranging the oxidation isolation layer with an electrical insulation effect between the VCSEL unit and the modulation unit to isolate the high-frequency modulation signal applied to the modulation unit, so that the VCSEL unit and the modulation unit are relatively independent, the high-frequency modulation signal is prevented from affecting the current in the VCSEL unit, and the stable output of the VCSEL unit is ensured. The microlens of the application can shape the modulated light beam, thereby optimizing the light beam quality, reducing the threshold current and the insertion loss, overcoming the problems caused by the additional coupling lens, reducing the packaging and assembling difficulty of the chip and effectively saving the production cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronics technology, and in particular to a high-efficiency vertical cavity surface EML chip with microlenses. Background Technology

[0002] With the rapid development of the data communication era, Vertical Cavity Surface Emitting Laser (VCSEL) chips have been widely used in optical communication fields, such as optical interconnects, optical sensing, and optical storage, due to their excellent characteristics, including small chip size, circular output spot, low operating threshold, high coupling efficiency, and ease of integration. Applications include short-range communication in data centers, 5G base stations, and HDMI ultra-high-definition video transmission. VCSEL chips offer excellent economic efficiency, practicality, and reliability, greatly facilitating information exchange across various industries.

[0003] With the increasing volume of data, higher demands are being placed on the rate and quality of data transmission. Currently, most VCSEL chips use direct modulation for signal transmission, that is, direct modulation with high-speed radio frequency electrical signals. As the modulation rate increases, direct modulation VCSEL chips are prone to chirp during operation. This phenomenon limits the transmission rate of the laser chip, and with increasing transmission distance, it also causes crosstalk and optical power attenuation, reducing signal transmission quality. To achieve a higher modulation rate without changing the modulation method, the current density needs to be increased exponentially, which in turn leads to increased chip power consumption and shortened lifespan.

[0004] Similar to edge-emitting EML chips, which are monolithically integrated edge-emitting laser chips consisting of a light-emitting unit (DFB) and a modulation unit, existing vertical-cavity surface-emitting (VCSEL) EML chips are monolithically integrated vertical-emitting laser chips consisting of a light-emitting unit (VCSEL unit) and a modulation unit (EOM unit). They typically have a structure of "NDBR-active region-oxide confinement layer-PDBR-absorption region-NDBR". The VCSEL unit and the modulation unit share a PDBR to achieve optical resonance of the VCSEL unit and enhance the light absorption of the modulation unit, respectively. However, because there is no electrical isolation between the VCSEL unit and the modulation unit, when a high-frequency modulation signal is applied to the modulation unit, the current in the VCSEL unit is affected, thus impacting the stable output of the VCSEL unit.

[0005] Furthermore, in practical applications, vertical-plane emitting laser chips are generally not used alone, but are integrated into optical modules to provide optical signal transmission. Therefore, the optical modules are designed with corresponding coupling methods for optical signal transmission before transmitting to external optical paths. However, this requires more space and increases the cost and complexity of packaging and assembly. In the process of coupling with external optical paths, transmission noise is also introduced, increasing absorption loss and reducing signal transmission quality.

[0006] Based on this, we provide a high-efficiency vertical cavity surface EML chip with microlenses. Summary of the Invention

[0007] This invention provides a high-efficiency vertical cavity surface EML chip with microlenses, the main purpose of which is to solve the problems existing in the prior art.

[0008] The present invention adopts the following technical solution:

[0009] A high-efficiency vertical cavity surface mount technology (VCSEL) chip with a microlens includes a VCSEL unit, an oxide isolation layer, a modulation unit, and a microlens. The VCSEL unit, from bottom to top, includes a substrate, a buffer layer, a first damped beam resonator (DBR), a resonant cavity, and a second DBR. The modulation unit, from bottom to top, includes a third DBR, an absorption region, and a fourth DBR. The oxide isolation layer is disposed between the VCSEL unit and the modulation unit to prevent the potential at the contact point between the two units from affecting the operating current within each unit. The microlens is disposed above the modulation unit to shape the beam from the VCSEL unit, thereby reducing the beam divergence angle.

[0010] This invention innovatively incorporates an electrically insulating oxide layer between the VCSEL unit and the modulation unit to isolate the high-frequency modulation signal applied to the modulation unit. This makes the VCSEL unit and the modulation unit relatively independent, preventing the high-frequency modulation signal from affecting the current in the VCSEL unit and thus ensuring stable output from the VCSEL unit. Compared to the direct contact between the VCSEL unit and the modulation unit in existing technologies, electrical isolation reduces RC delay during high-frequency signal transmission, helping to improve transmission performance and achieve superior modulation effects.

[0011] In the VCSEL unit plus modulation unit design of this invention, the fourth DBR at the top absorbs light particularly strongly, especially long wavelengths (1310 and 1550 nm), resulting in high threshold current and high insertion loss. This invention integrates a microlens above the modulation unit. The microlens can shape the modulated beam, thereby optimizing beam quality, reducing threshold current and insertion loss. This overcomes the problems associated with additional coupling lenses, reduces chip packaging and assembly complexity, and effectively saves production costs.

[0012] The microlens can be made of polymer, dielectric, or semiconductor materials. Specifically, the polymer material can be PI or BCB, the dielectric material can be silicon nitride, silicon oxide, or aluminum oxide, and the semiconductor material can be GaAs or AlGaAs. The appropriate design can be chosen based on specific application requirements and is not limited here.

[0013] The substrate is made of GaAs, and the thickness of the oxide isolation layer is 5-5000 nm. The GaAs material system has higher reliability. When both the resonant cavity of the VCSEL unit and the absorption region of the modulation unit are made of GaAs, the material properties of the two units are similar, which can greatly improve the stability of chip epitaxial deposition and reduce the difficulty of mass production.

[0014] In the GaAs-based material system, the oxide isolation layer is made of Al2O3, which is composed of Al... x Ga 1-x The As prefabricated layer is formed by wet oxidation, where x ≥ 0.97. Al2O3 has excellent electrical insulation properties, making it an ideal material for the oxide isolation layer. The oxide isolation prefabricated layer material is AlGaAs, which matches the crystal lattice of the GaAs substrate system, enabling continuous epitaxial growth, reducing the difficulty of epitaxial production, and facilitating mass production. It also ensures the epitaxial crystal quality of the VCSEL unit and modulation unit, improving device reliability.

[0015] The first DBR, the second DBR, the third DBR, and the fourth DBR are made of Al i Ga 1-i As / Al j Ga 1-j The periodic structure is composed of As material, and both i and j are not greater than 0.92. This is because the oxide isolation prefabrication layer uses Al with a high aluminum content. x Ga 1-x As materials, on the one hand, to prevent the first, second, third, and fourth DBRs from being over-oxidized, and on the other hand, because a higher aluminum content leads to a higher device resistance, it should be ensured that the aluminum content of the materials constituting the first, second, third, and fourth DBRs does not exceed 92%. In addition, the use of aluminum arsenide materials should be avoided in applications.

[0016] Based on the GaAs material system, the microlens is made of GaAs and has a diameter of 5-15 μm and a radius of curvature of 30-80 μm, which can produce a good beam shaping effect.

[0017] The resonant cavity has a sandwich structure of a lower waveguide, an active region, and an upper waveguide, and uses a buried tunnel junction for optical and electrical confinement. The cavity length is an integer multiple of the half-laser wavelength. The gain structure of the quantum well in the resonant cavity can be a single quantum well, multiple quantum wells, tunnel junction cascaded quantum wells, or quantum dots. Specifically, the quantum well can be one of InGaAs / GaAs, InGaAs / AlGaAs, InGaAs / GaAsP, GaAs / AlGaAs, AlInGaAs / AlGaAs, InGaAsP / AlGaAs, and AlGaInP / GaAs.

[0018] For the same resonant cavity quantum well, the quantum well material of the absorption region can also be one of InGaAs / GaAs, InGaAs / AlGaAs, InGaAs / GaAsP, GaAs / AlGaAs, AlInGaAs / AlGaAs, InGaAsP / AlGaAs, and AlGaInP / GaAs. However, in order to achieve modulation, the quantum well wavelength of the absorption region should be controlled to be 5-99 nm shorter than the quantum well wavelength of the resonant cavity.

[0019] The absorption region can be a single quantum well or a multi-quantum well structure. When the absorption region is a single quantum well structure, a third waveguide layer is provided between the absorption region and the third DBR, and a fourth waveguide layer is provided between the absorption region and the fourth DBR. This is because the single quantum well structure requires the formation of the same FP resonant cavity as the VCSEL unit, but the FP resonant cavity in the absorption region is a passive FP used to enhance absorption, rather than an active FP like in the VCSEL unit.

[0020] When the absorption region employs a pair of quantum wells, the modulation unit modulates the light intensity of the VCSEL cell based on the quantum confined Stark effect (QCSE). By modulating the bias voltage of the modulation unit, the absorption sideband of the absorption region is directly shifted, thereby indirectly achieving high-speed modulation of the VCSEL output light intensity. Compared to traditional direct modulation methods, the efficient modulation using the EOM modulation unit reduces the design limitations of the VCSEL cell, thus improving photoelectric conversion efficiency and optimizing the structural design of the VCSEL cell.

[0021] When the absorption region employs a multi-pair quantum well structure, the modulation unit modulates the light intensity of the VCSEL unit based on the reflectivity difference between the top and bottom mirrors. By modulating the bias voltage of the modulation unit, the absorption state of the absorption region is directly affected, thereby controlling the overall reflectivity of the top mirror and indirectly achieving high-speed modulation of the VCSEL output light intensity.

[0022] Regarding the specific structure of the resonant cavity, the present invention provides the following two specific implementation schemes for selection:

[0023] As a first embodiment: the resonant cavity includes, from bottom to top, a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer, a P-type confinement layer, and a buried tunnel junction; the first DBR is a first N-type doped DBR; the second DBR is a second N-type doped DBR; the third DBR is a third N-type doped DBR; and the fourth DBR is a P-type doped DBR.

[0024] The reasons for setting up a buried tunnel junction are as follows: First, because PDBR has high free carrier absorption and resistance, it increases light absorption loss and heat loss, reducing the electrical conversion efficiency of VCSEL cell. The VCSEL cell of this invention uses a buried tunnel junction to reverse the polarity of PDBR, thereby avoiding the increased light absorption loss and heat loss caused by the high free carrier absorption and resistance of PDBR, which is beneficial to improving the light extraction efficiency of VCSEL cell. Second, in terms of process technology, in the oxidation process of oxide confinement layer, point defects and dislocations will be generated at the oxide layer and semiconductor interface. Moreover, the thermal expansion coefficients of oxide layer and semiconductor are different, which makes the oxidation process usually very difficult to control, the process window is extremely narrow, and the oxide layer-semiconductor interface is prone to cracking or peeling after the oxidation process. This invention uses buried tunnel junctions to replace the oxide confinement layer of VCSEL units in the prior art to achieve electrical and optical confinement. This can avoid the yield loss problem that traditional oxide-confined VCSELs often face in the key process of wet oxidation, reduce production difficulty, simplify the production process, and the buried tunnel junctions prepared by photolithography have good uniformity, which greatly improves the yield.

[0025] Specifically, the buried tunneling junction comprises a P-type heavily doped layer and an N-type heavily doped layer from bottom to top, and the pore size of the buried tunneling junction is 2-100 μm. Specifically, the material of the P-type heavily doped layer is GaInP, GaAs, or AlGaAs, and the material of the N-type heavily doped layer is GaInP, GaAs, or AlGaAs; the thickness of the P-type heavily doped layer ranges from 8-50 nm, and the thickness of the N-type heavily doped layer ranges from 10-50 nm; the doping atoms of the P-type heavily doped layer can be C, Mg, Zn, or Be, and the doping atoms of the N-type heavily doped layer can be Te or Se; the doping concentration of the P-type and N-type heavily doped layers is 10. 19 -10 20 cm -3 Order of magnitude.

[0026] The epitaxial structure of this invention adopts the NP-TJ-NO-NP structure. However, in practical applications, the epitaxial structure can be adjusted to NP-TJ-NO-PN, PN-TJ-PO-NP, or PN-TJ-PO-PN structures as needed. Here, N refers to the N-type confinement layer or N-type doped DBR, P refers to the P-type confinement layer or P-type doped DBR, TJ refers to the buried tunnel junction, and O refers to the oxide isolation layer.

[0027] As a second embodiment: the resonant cavity comprises, from bottom to top, a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer, and an oxide confinement layer; the first DBR is a first N-type doped DBR; the second DBR is a first P-type doped DBR; the third DBR is a second N-type doped DBR; and the fourth DBR is a second P-type doped DBR. It can be seen that the epitaxial structure provided by this invention is an NP-O-NP structure. However, in practical applications, the epitaxial structure can be adjusted to an NP-O-PN, PN-O-NP, or PN-O-PN structure as needed, where N refers to an N-type doped DBR, P refers to a P-type doped DBR, and O refers to an oxide isolation layer.

[0028] When the substrate material is GaAs, the thickness of the oxide confinement layer is 5-5000 nm. The oxide confinement layer is formed by a wet oxidation process from an oxide confinement pre-layer. The oxidized region forms Al₂O₃ with optical and electrical confinement functions, and the pore size of the unoxidized region ranges from 2-100 μm. The oxide confinement pre-layer is doped or undoped Al₂O₃. y Ga 1-y As, where 0.92 < y < x. Since the oxidation processes of the oxidation-confined preform and the oxidation-isolated preform are performed simultaneously, and the oxidation-confined preform needs to undergo partial oxidation to form the photoelectric confinement aperture, the Al used in the oxidation-confined preform... y Ga 1-y The aluminum content of the As material should be between that of the DBR and the oxide isolation prefabricated layer, therefore it is set to 0.92 < y < x. It is evident that the prefabricated materials of both the oxide confinement layer and the oxide isolation layer are AlGaAs materials, which match the lattice of the GaAs substrate system, ensuring the epitaxial crystal quality of the VCSEL unit and the modulation unit, and improving the reliability of the device. Furthermore, this invention innovatively pioneers a differential oxidation method. By precisely designing the aluminum content deviation between the oxide isolation prefabricated layer and the oxide confinement prefabricated layer, the oxide isolation layer and the oxide confinement layer can be formed in the same oxidation process, greatly simplifying the chip manufacturing process and reducing production costs.

[0029] The high-efficiency vertical cavity surface EML chip also includes a first electrode, a second ring electrode, a third ring electrode, and a fourth ring electrode, wherein: the first electrode is a first planar electrode disposed on the lower surface of the substrate or a first ring electrode disposed on the upper surface of the first DBR; the second ring electrode is disposed on the upper surface of the second DBR; the third ring electrode is disposed on the upper surface of the third DBR; and the fourth ring electrode is disposed on the upper surface of the fourth DBR.

[0030] Because an oxide isolation layer with electrical isolation effect is set between the VCSEL unit and the modulation unit, electrodes cannot be shared, and a four-electrode structure is required. In practical applications, the first electrode can be set as a first planar electrode or a first ring electrode as needed to meet different application scenarios, such as TOP-TOP contact type and TOP-BOTTOM contact type applications.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0032] This invention innovatively incorporates an electrically insulating oxide layer between the VCSEL unit and the modulation unit to isolate the high-frequency modulation signal applied to the modulation unit. This makes the VCSEL unit and the modulation unit relatively independent, preventing the high-frequency modulation signal from affecting the current in the VCSEL unit and thus ensuring stable output from the VCSEL unit. Compared to the direct contact between the VCSEL unit and the modulation unit in existing technologies, electrical isolation reduces RC delay during high-frequency signal transmission, helping to improve transmission performance and achieve superior modulation effects.

[0033] 2. The present invention integrates a microlens above the modulation unit. The microlens can shape the modulated beam, thereby optimizing the beam quality, reducing the threshold current and insertion loss. This overcomes the problems associated with additional coupling lenses, reduces the packaging and assembly difficulty of the chip, and effectively saves production costs. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the cross-sectional structure of the chip provided in Embodiment 1 of the present invention.

[0035] Figure 2 This is a schematic diagram of the resonant cavity structure of the VCSEL unit provided in Embodiment 1 of the present invention.

[0036] Figure 3 This is a schematic diagram of the modulation principle provided in Embodiment 1 of the present invention.

[0037] Figure 4 This is a schematic diagram illustrating the beam shaping effect achieved by the microlens provided in Embodiment 1 of the present invention.

[0038] Figure 5 This is a schematic diagram illustrating the principle of beam shaping achieved by the microlens provided in Embodiment 1 of the present invention.

[0039] Figure 6 This is a schematic diagram of the resonant cavity structure of the VCSEL unit provided in Embodiment 2 of the present invention.

[0040] Figure 7 This is a schematic diagram of the modulation principle provided in Embodiment 2 of the present invention.

[0041] In the picture:

[0042] 10. Substrate; 11. Buffer layer

[0043] 12. First N-type doped DBR 13. Resonant cavity

[0044] 14. Second N-type doped DBR 15. Oxide isolation layer

[0045] 16. Third N-type doped DBR 17. Third waveguide layer

[0046] 18. Absorption region 19. Fourth waveguide layer

[0047] 110. P-type doped DBR 111. First planar electrode

[0048] 111', First annular electrode 112, Second annular electrode

[0049] 113. Third ring electrode; 114. Fourth ring electrode

[0050] 117. Microlenses

[0051] 21. First confinement layer; 22. First waveguide layer

[0052] 23. Quantum well layer 24. Second waveguide layer

[0053] 25. Second limiting layer; 26. Buried tunnel penetration joint

[0054] 27. P-type confinement layer; 28. Oxidation confinement layer

[0055] 20. Top reflector; 30. Bottom reflector Detailed Implementation

[0056] Specific embodiments of the present invention will now be described with reference to the accompanying drawings. Many details are described below to provide a comprehensive understanding of the invention; however, those skilled in the art will be able to implement the invention without these details. Example

[0057] like Figure 1 and Figure 4As shown, this embodiment provides a high-efficiency vertical-cavity surface mount technology (VCSEL) chip with a microlens, including a VCSEL unit, an oxide isolation layer 15, a modulation unit, and a microlens 117. The oxide isolation layer 15 is disposed between the VCSEL unit and the modulation unit to prevent the potential at the contact point between the two units from affecting the operating current within each unit. The microlens 117 is disposed above the modulation unit to shape the beam from the VCSEL unit, thereby reducing the beam divergence angle.

[0058] like Figure 1 As shown, the VCSEL unit, from bottom to top, includes a substrate 10, a buffer layer 11, a first DBR 12, a resonant cavity 13, and a second DBR 14. The modulation unit, from bottom to top, includes a third DBR 16, a third waveguide layer 17, an absorption region 18, a fourth waveguide layer 19, and a fourth DBR 110.

[0059] like Figure 1 As shown, the chip also includes a first electrode, a second ring electrode 112, a third ring electrode 113, and a fourth ring electrode 114. Specifically, in this embodiment, the first electrode is a first planar electrode 111 disposed on the lower surface of the substrate 10. In other embodiments, the first electrode may also be a first ring electrode 111' disposed on the upper surface of the first DBR; the second ring electrode 112 is disposed on the upper surface of the second DBR 14; the third ring electrode 113 is disposed on the upper surface of the third DBR 16; and the fourth ring electrode 114 is disposed on the upper surface of the fourth DBR 110.

[0060] Preferably, the substrate 10 is a Si-doped GaAs substrate with a doping concentration of 1.5e. 18 cm -3 .

[0061] Preferably, the buffer layer 11 is a Si-doped GaAs layer with a doping concentration of 2e⁻. 18 cm -3 The thickness is 200nm.

[0062] Preferably, the first DBR12 is a first N-type doped DBR, the second DBR14 is a second N-type doped DBR, and the third DBR16 is a third N-type doped DBR. Furthermore, the first, second, and third N-type doped DBRs form a high refractive index / low refractive index / high refractive index / low refractive index… / high refractive index structure, with the high refractive index material being Si-doped Al. 0.12 Ga 0.88 The As layer is made of Si-doped Al. 0.9 Ga 0.1 As layer. Si-doped Al 0.12 Ga 0.88 The As layer is 60 nm thick and has a doping concentration of 2e. 18 cm -3Si-doped Al 0.9 Ga 0.1 The As layer is 69.4 nm thick and has a doping concentration of 2e. 18 cm -3 .

[0063] like Figure 2 As shown, the optical thickness of the resonant cavity 13 is one wavelength, and the resonant cavity 13 includes, from bottom to top, a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, a P-type confinement layer 27, and a buried tunnel junction 26.

[0064] Preferably, the first confinement layer 21 is Si-doped Al. 0.6 Ga 0.4 As, with a thickness of 22 nm and a doping concentration of 2e 17 cm -3 .

[0065] Preferably, the first waveguide layer 22 is Al 0.45 Ga 0.55 As, with a thickness of 18nm.

[0066] Preferably, the quantum well layer 23 is composed of a barrier layer Al with a thickness of 10 nm. 0.35 Ga 0.65 The structure consists of a well / barrier / well / barrier / well structure composed of As and a GaAs well layer with a thickness of 8nm, and the lasing wavelength is 850nm.

[0067] Preferably, the second waveguide layer 24 is Al 0.45 Ga 0.55 As, the thickness is 30nm.

[0068] Preferably, the second confining layer 25 is Si-doped Al. 0.6 Ga 0.4 As, with a thickness of 62.5 nm and a doping concentration of 2e 18 cm -3 .

[0069] Preferably, the p-type confinement layer 27 is C-doped AlGaAs or 1-2 pairs of p-type doped DBRs with a doping concentration of 2e⁻¹. 18 cm -3 .

[0070] Preferably, the buried tunnel junction 26 includes Al from bottom to top. 0.2 Ga 0.8 As heavily doped C layer and Al 0.2 Ga 0.8 As heavily doped Te layer. Among them, Al 0.2 Ga 0.8The thickness of the heavily As-doped C layer is 15 nm, and the doping concentration is 1.5 eE. 20 cm -3 Al 0.2 Ga 0.8 The thickness of the As-doped Te layer is 15 nm, and the doping concentration is 2e⁻¹. 19 cm -3 The pore size of the buried tunnel is 8μm.

[0071] Preferably, the oxide isolation layer 15 is composed of undoped Al with a thickness of 30 nm. 0.98 Ga 0.02 The oxide isolation prefabricated layer of As is formed by a wet oxidation process to form an Al2O3 isolation layer with electrical insulation effect. This effectively prevents the potential at the contact point between the VCSEL unit and the modulation unit from affecting the current in the VCSEL unit, thereby further improving the performance of the VCSEL.

[0072] Preferably, the third waveguide layer 17 is Si-doped Al. 0.45 Ga 0.55 As, with a thickness of 77 nm and a doping concentration of 2e 17 cm -3 .

[0073] Preferably, the absorption region 18 is a pair of Al 0.35 Ga 0.65 A quantum well with As as the barrier and GaAs as the well, Al 0.35 Ga 0.65 The thickness of the As barrier layer is 5 nm, the thickness of the GaAs well layer is 6 nm, the thickness of the absorption region 18 is 450 nm, and the quantum well wavelength of the absorption region 18 is 830 nm.

[0074] Preferably, the fourth waveguide layer 19 is C-doped Al. 0.45 Ga 0.55 As, with a thickness of 77 nm and a doping concentration of 2e 17 cm -3 The third waveguide layer 17 and the fourth waveguide layer 19 are N-type and P-type doped, respectively, forming a PN junction, and the absorption region 18 is formed between the PN junctions.

[0075] Preferably, the fourth DBR110 is a p-type doped DBR, and the p-type doped DBR is a periodically stacked high refractive index / low refractive index / high refractive index / low refractive index… / high refractive index structure, wherein the high refractive index material is C-doped Al. 0.12 Ga 0.88 The As layer, with the low refractive index material being C-doped Al. 0.9 Ga 0.1 As layer. C-doped Al 0.12 Ga 0.88The As layer is 60 nm thick and has a doping concentration of 2e. 18 cm -3 C-doped Al 0.9 Ga 0.1 The As layer is 69.4 nm thick and has a doping concentration of 2e. 18 cm -3 .

[0076] The working principle of the buried tunneling junction 26 is as follows: buried in a degenerate, heavily doped semiconductor, the Fermi level of the n-type semiconductor enters the conduction band, and the Fermi level of the p-type semiconductor enters the valence band. Due to the quantum mechanical tunneling effect, electrons in the n-region conduction band may pass through the gap to the p-type valence band, and electrons in the p-region valence band may also pass through the gap to the n-region conduction band, thus generating a tunneling current. Here, the buried tunneling junction 26 is used instead of the oxide confinement layer to achieve electrical and optical confinement. On the one hand, the buried tunneling junction 26 reverses the polarity of the PDBR, thereby avoiding the increased light absorption loss and heat loss caused by the higher free carrier absorption and resistance of the PDBR, which is beneficial to improving the light extraction efficiency of the VCSEL cell. On the other hand, in terms of process technology, during the oxidation process of the oxide confinement layer, point defects and dislocations are generated at the interface between the oxide layer and the semiconductor. Moreover, the thermal expansion coefficients of the oxide layer and the semiconductor are different, which makes the oxidation process very difficult to control, the process window is extremely narrow, and the oxide layer-semiconductor interface is prone to cracking or peeling after the oxidation process. Replacing the oxide confinement layer of the VCSEL cell with a buried tunnel junction helps improve manufacturing yield. Therefore, using a buried tunnel junction to replace the oxide confinement layer for optical and electrical confinement is beneficial for improving the light extraction efficiency and manufacturing yield of VCSELs.

[0077] like Figure 3 As shown, the modulation principle of this embodiment is as follows: When no bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114, or when a low bias voltage is applied, the absorption curve of the modulation unit is in the blue-shift direction compared to the emission wavelength of the VCSEL unit. In this case, the beam emitted by the VCSEL unit will not suffer absorption loss after passing through the modulation unit. When a higher bias voltage is applied to the modulation unit, due to the quantum confinement Stark effect (QCSE), its absorption spectrum sideband will rapidly drift to a longer wavelength, covering the emission wavelength of the VCSEL unit. Therefore, the high-speed electrical modulation signal applied to the modulation unit directly affects the shift of its absorption sideband, achieving high-speed modulation of the emitted light intensity of the VCSEL. In this embodiment, the modulation unit and the VCSEL unit are separated by an oxide isolation layer 15, making them relatively independent and contributing to a better modulation effect.

[0078] like Figure 4 and Figure 5As shown, in this embodiment, a microlens 117 with a certain thickness and size is provided on the top of the EOM modulation unit. Preferably, the material of the microlens 117 is GaAs, and the diameter of the microlens 117 is 10μm and the radius of curvature is 40μm, thereby producing a good beam shaping effect to improve the signal transmission quality. Other parameters of the microlens are detailed in the table below.

[0079] Table 1. Relevant parameters of the microlens

[0080] item target Wavelength (nm) 850nm Mirror shape Plano-convex mirror Field of view 0 degrees Solution method Sequence pattern light source Point light source curved surface spherical radius of curvature -40nm (± only represents the direction) Edge thickness 2μm Lens aperture distance 10μm Object distance 30μm (from the light-emitting area to the lens) Coupling distance 50μm (lens to light-receiving surface)

[0081] The preparation method of this embodiment includes the following steps:

[0082] 1. A buffer layer 11, a first N-type doped DBR and a resonant cavity 13 are sequentially deposited on a substrate 10 using MOCVD. The resonant cavity 13 includes a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, a P-type confinement layer 27 and a tunnel junction layer.

[0083] 2. A tunneling junction etching mask SiNx is formed on the surface of the tunneling junction layer by enhanced plasma chemical vapor deposition, photolithography and reactive ion etching. Then, a buried tunneling junction 26 with an 8μm aperture is formed by inductively coupled plasma etching of the tunneling junction layer. Finally, the tunneling junction etching mask SiNx is removed by BOE.

[0084] 3. Using MOCVD, a second N-type doped DBR and an oxide isolation prefabricated layer (Al) are sequentially grown on the surface of the buried tunnel junction. 0.98 Ga 0.02 As), third N-type doped DBR, third waveguide layer 17, absorption region 18, fourth waveguide layer 19 and P-type doped DBR.

[0085] 4. ICP etching is used to etch the substrate 10 to expose the buffer layer 11, and a first planar electrode 111 is fabricated on the buffer layer 11 away from the surface of the first N-type doped DBR.

[0086] 5. First, a contact layer selected area mask SiNx is formed on the top of the second N-type doped DBR using enhanced plasma chemical vapor deposition (PECVD), photolithography, and reactive ion etching (RIE) processes. Then, selective edge etching is performed by ICP etching to etch the epitaxial structure above the top of the second N-type doped DBR to the upper surface of the second N-type doped DBR. Next, the contact layer selected area mask SiNx is removed by BOE. Finally, a second ring electrode 112 is formed on the upper surface of the second N-type doped DBR using photolithography, electron beam evaporation of metal layers, and lift-off processes.

[0087] 6. A wet oxidation process is used for Al-containing compounds. 0.98 Ga0.02 The As oxide isolation prefabricated layer is oxidized to form an oxide isolation layer 15 with the composition Al2O3.

[0088] 7. Following the method in step 5, fabricate the third annular electrode 113 on the upper surface of the third N-type doped DBR. However, it should be noted that during ICP etching, selective edge etching must be performed on the epitaxial structure at least 200 nm from the bottom of the third N-type doped DBR to prevent the oxide isolation layer 15 from being etched through, which would cause the oxide isolation layer 15 to fail. Then, fabricate the fourth annular electrode 114 on the upper surface of the P-type doped DBR using existing technology.

[0089] 8. Microlenses are fabricated on the surface of a P-type doped DBR by wet etching of the semiconductor material using a confined diffusion chemical process, or by inkjet printing polymer material followed by photopolymerization. Specifically, this embodiment uses a confined diffusion chemical process to fabricate microlenses. On the surface of the P-type DBR, after photolithography, a photoresist with a certain thickness and a centrally located hole is fabricated to expose the semiconductor material layer with the aperture diameter. The hole diameter essentially determines the size of the microlens, and the remaining portion is covered by the photoresist. This photoresist serves as a mask for fabricating the surface microlenses. The sample with the photoresist pattern is immersed in a wet etching solution (H2O2, HBr, CH3OH, H2O mixed in a ratio of 1:1:1:10). Due to the regional difference in etching rates between the center and the edge of the hole area, the edge etching reaction rate is faster, while the center is slower. By adjusting the etching rate and solution ratio and composition, the microlens morphology can be formed.

[0090] It is important to note that in step 6, the oxidation process of the oxide isolation prefabrication layer is performed after the first planar electrode 111 and the second annular electrode 112 are chosen for the following reasons: First, the oxidation process can fully utilize the advantage of more accurate alignment of the metal layers (i.e., the first planar electrode 111 and the second annular electrode 112), ensuring that the oxidation process is precise and controllable; Second, the etching process of the first planar electrode 111 and the second annular electrode 112 will reduce the oxidation area of ​​the oxidation process, which can significantly save oxidation time and also help improve the uniformity of oxidation; Third, the oxide isolation prefabrication layer will generate stress after oxidation, which will have a certain impact on the etching steps of the metal electrode part, so it is necessary to fabricate the metal electrode part first.

[0091] The reason for choosing to prepare the third annular electrode 113 and the fourth annular electrode 114 after the oxidation process is that during the oxidation process, it is necessary to observe under an infrared microscope whether the oxide isolation prefabricated layer has been fully oxidized to form the oxide isolation layer 15. If the upper metal layer is prepared before oxidation, it will be difficult to observe the morphology of the oxide isolation layer 15. Example

[0092] like Figure 1and 4 As shown, the structural design of this embodiment is basically the same as that of Embodiment 1, but the structure of the resonant cavity 13, the modulation principle of the modulation unit, and the fabrication method of the VCSEL chip are different. First, the structure of the resonant cavity 13 in this embodiment will be described:

[0093] like Figure 6 As shown, the resonant cavity 13 includes, from bottom to top, a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, and an oxide confinement layer 28.

[0094] Preferably, the oxide confinement layer 28 is composed of undoped Al with a thickness of 30 nm. 0.93 Ga 0.07 The oxidation-confined preform of As is formed by a wet oxidation process. The pore size of the unoxidized area is retained at 8 μm, while the oxidized area forms Al2O3 with optical and electrical confinement functions.

[0095] like Figure 1 As shown, based on the different resonant cavity 13, the first to fourth DBRs in this embodiment are also different from those in Embodiment 1:

[0096] The first DBR12 is a first N-type doped DBR, and the third DBR16 is a second N-type doped DBR. Furthermore, the first and second N-type doped DBRs exhibit a high refractive index / low refractive index / high refractive index / low refractive index… / high refractive index structure, with the high refractive index material being Si-doped Al. 0.12 Ga 0.88 The As layer is made of Si-doped Al. 0.9 Ga 0.1 As layer. Si-doped Al 0.12 Ga 0.88 The As layer is 60 nm thick and has a doping concentration of 2e. 18 cm -3 Si-doped Al 0.9 Ga 0.1 The As layer is 69.4 nm thick and has a doping concentration of 2e. 18 cm -3 .

[0097] The second DBR14 is the first p-type doped DBR, and the fourth DBR110 is the second p-type doped DBR. The first and second p-type doped DBRs form a periodically superimposed high refractive index / low refractive index / high refractive index / low refractive index… / high refractive index structure, with the high refractive index material being C-doped Al. 0.12 Ga 0.88 The As layer, with the low refractive index material being C-doped Al. 0.9 Ga 0.1 As layer. C-doped Al 0.12Ga 0.88 The As layer is 60 nm thick and has a doping concentration of 2e. 18 cm -3 C-doped Al 0.9 Ga 0.1 The As layer is 69.4 nm thick and has a doping concentration of 2e. 18 cm -3 .

[0098] The modulation method in this embodiment will be described in detail below:

[0099] In this embodiment, the third waveguide layer 17 and the fourth waveguide layer 19 are not provided, and the absorption region 18 consists of multiple pairs of Al 0.35 Ga 0.65 A quantum well with As as the barrier and GaAs as the well, Al 0.35 Ga 0.65 The thickness of the As barrier layer is 5 nm, the thickness of the GaAs well layer is 6 nm, and the thickness of the absorption region is 450 nm. Increasing the number of quantum well cycles in absorption region 18 can reduce the number of cycles in the top P-type doped DBR110.

[0100] like Figure 1 As shown, the bottom reflector 30 comprises the entire portion below the resonant cavity 13, and the top reflector 20 comprises the entire portion above the resonant cavity 13. For the lasing wavelength of 850nm in the resonant cavity 13, the overall reflectivity of the bottom reflector 30 can be designed to be 99.995%, and the overall reflectivity of the top reflector 20 can be designed to be 99.89%. The absorption region 18 of the modulation unit is placed at the point of maximum light intensity of the top reflector 20.

[0101] like Figure 7 As shown, the modulation principle of this embodiment is as follows: When no bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114 or a low bias voltage is applied, the absorption region 18 in the modulation unit is in a non-absorption state. At this time, the reflectivity of the bottom reflector 30 is 99.995%, and the reflectivity of the top reflector 20 is 99.89%. The photons emitted by the quantum well 23 can form a continuous and stable back-and-forth oscillation in the resonant cavity 13. After the gain reaches a certain value, they can pass through the top reflector 20 to form light output. When a higher bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114, the absorption effect of the absorption region 18 in the modulation unit is enhanced, and the reflectivity of the top reflector 20 drops to 99.68%. At this time, the photons emitted by the quantum well 23 cannot form a continuous and stable oscillation in the resonant cavity 13, or the gain is insufficient, and the light intensity cannot penetrate the top reflector 20 to stably output light, or it will cause a reduction in the output laser power. Therefore, by modulating the bias level of the modulation unit and changing the working state of the absorption region 18, the reflectivity of the top DBR can be affected, thereby achieving high-speed modulation of the light intensity emitted by the VCSEL unit.

[0102] The following is a detailed description of the fabrication method of the VCSEL chip in this embodiment, which includes the following steps:

[0103] 1. A buffer layer 11, a first N-type doped DBR, a resonant cavity 13, a first P-type doped DBR, an oxide isolation prefabricated layer, a second N-type doped DBR, an absorption region 18, and a second P-doped DBR are sequentially grown on a substrate 10 using MOCVD. The resonant cavity 13 includes a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, and an oxide confinement prefabricated layer.

[0104] 2. The substrate 10 is etched by ICP to expose the buffer layer 11, and a first planar electrode is fabricated on the buffer layer 11 away from the surface of the first N-type doped DBR.

[0105] 3. First, a contact layer selected area mask SiNx is formed on the upper surface of the first P-type doped DBR using enhanced plasma chemical vapor deposition (PECVD), photolithography, and reactive ion etching (RIE). Then, selective edge etching is performed by ICP etching to etch the epitaxial structure above the top of the first P-type doped DBR onto the upper surface of the first P-type doped DBR. Next, the contact layer selected area mask SiNx is removed by BOE. Finally, a second ring electrode 112 is formed on the upper surface of the first P-type doped DBR using photolithography, electron beam evaporation of metal layers, and lift-off processes.

[0106] 4. A wet oxidation process is used for Al-containing compounds. 0.98 Ga 0.02 The oxide isolation pre-layer of As and its composition are Al. 0.93 Ga 0.07 The As oxidation-limiting prefabricated layer is oxidized to form an Al2O3 oxidation isolation layer 15 and an oxidation-limiting layer 28.

[0107] 5. Following the method in step 4, fabricate the third annular electrode 113 on the upper surface of the second N-type doped DBR. However, it should be noted that during ICP etching, selective edge etching must be performed on the epitaxial structure at least 200 nm from the bottom of the second N-type doped DBR to prevent the oxide isolation layer 15 from being etched through, which would cause the oxide isolation layer 15 to fail. Then, fabricate the fourth annular electrode 114 on the upper surface of the second P-type doped DBR using existing technology.

[0108] 6. On the surface of the second P-type doped DBR, a microlens 117 is formed by wet etching of semiconductor material using a confined diffusion chemical process, or by printing polymer material by inkjet printing followed by photopolymerization.

[0109] The above are merely specific embodiments of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept shall be considered as infringing upon the protection scope of the present invention.

Claims

1. A high-efficiency vertical-cavity surface-emitting laser (VCSEL) chip with a microlens, characterized in that: the high-efficiency VCSEL chip comprises a VCSEL unit, an oxidation isolation layer, a modulation unit, and a microlens, wherein: the VCSEL unit comprises, from bottom to top, a substrate, a buffer layer, a first distributed Bragg reflector (DBR), a resonant cavity, and a second DBR; the modulation unit comprises, from bottom to top, a third DBR, an absorption region, and a fourth DBR; the microlens is arranged above the modulation unit and is used to shape the light beam of the modulated VCSEL unit to reduce the beam divergence angle, thereby optimizing the beam quality, reducing the threshold current, and reducing the insertion loss; the resonant cavity has one of the following two parallel structures: in a first structure, the resonant cavity comprises, from bottom to top, a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer, a P-type confinement layer, and a buried tunnel junction; the first DBR is a first N-type doped DBR, the second DBR is a second N-type doped DBR, the third DBR is a third N-type doped DBR, and the fourth DBR is a P-type doped DBR; and a preparation method of the high-efficiency VCSEL chip comprises the following steps: (1) depositing, on the substrate, the buffer layer, the first N-type doped DBR, and the resonant cavity in sequence by using a metal-organic chemical vapor deposition (MOCVD) method; (2) forming a tunnel junction etching mask SiNx on the surface of the tunnel junction layer by using an enhanced plasma chemical vapor deposition (EPCVD) method, a photolithography process, and a reactive ion etching (RIE) process, then forming a buried tunnel junction by using an inductively coupled plasma (ICP) etching method, and finally removing the tunnel junction etching mask SiNx by using a buffered oxide etch (BOE) method; (3) continuing to grow, on the surface of the buried tunnel junction, the second N-type doped DBR, an oxidation isolation pre-layer, the third N-type doped DBR, a third waveguide layer, the absorption region, a fourth waveguide layer, and the P-type doped DBR in sequence by using the MOCVD method; (4) etching the substrate by using the ICP etching method to expose the buffer layer, and preparing a first planar electrode on the surface of the buffer layer away from the first N-type doped DBR; (5) first forming a contact layer selection mask SiNx on the top of the second N-type doped DBR by using the EPCVD method, the photolithography process, and the RIE process, then performing selective edge etching by using the ICP etching method to etch the epitaxial structure above the top of the second N-type doped DBR to the upper surface of the second N-type doped DBR, and then removing the contact layer selection mask SiNx by using the BOE method; finally, forming a second ring-shaped electrode on the upper surface of the second N-type doped DBR by using a photolithography process, an electron beam evaporation metal layer process, and a stripping process; (6) oxidizing the oxidation isolation pre-layer by using a wet oxidation process to form the oxidation isolation layer; (7) preparing a third ring-shaped electrode on the upper surface of the third N-type doped DBR and a fourth ring-shaped electrode on the upper surface of the P-type doped DBR by referring to the method of step (5); and (8) preparing the microlens on the upper surface of the P-type doped DBR by using a diffusion-limited chemical wet etching semiconductor material or by using an inkjet printing polymer material and then performing photo-curing to form the microlens. ​ ​ ​ The oxidation isolation layer is arranged between the VCSEL unit and the modulation unit, for preventing the potential at the contact of the two units from affecting the working current in the respective unit; the material of the substrate is GaAs; the material of the oxidation isolation layer is Al2O3, which is formed by wet oxidation process of a pre-prepared layer with material of Al x Ga 1-x As, wherein x≥0.97; the first DBR, the second DBR, the third DBR and the fourth DBR are periodic structures composed of Al i Ga 1-i As / Al j Ga 1-j As materials, and i and j are both not greater than 0.

92. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The second structure: the resonant cavity comprises from bottom to top a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer and an oxidation confinement layer; the first DBR is a first N-type doped DBR, the second DBR is a first P-type doped DBR, the third DBR is a second N-type doped DBR, and the fourth DBR is a second P-type doped DBR; the oxidation confinement layer is formed by wet oxidation process of an oxidation confinement pre-prepared layer, the aperture range of the unoxidized area is 2-100 μm, and the oxidation confinement pre-prepared layer is doped or undoped Al y Ga 1-y As, wherein 0.92 The preparation method of the high-efficiency vertical cavity surface EML chip comprises the following steps: (1) growing a buffer layer, a first N-doped DBR, a resonant cavity, a first P-doped DBR, an oxidation isolation pre-preparation layer, a second N-doped DBR, an absorption region, and a second P-doped DBR on a substrate by MOCVD; (2) etching the substrate by ICP to expose the buffer layer, and preparing a first planar electrode on a surface of the buffer layer away from the first N-doped DBR; (3) first, forming a contact layer selected mask SiNx on the upper surface of the first P-doped DBR by enhanced plasma chemical vapor deposition, photolithography and reactive ion etching process, then performing selective edge etching by ICP etching to etch the epitaxial structure above the top of the first P-doped DBR to the upper surface of the first P-doped DBR, and then removing the contact layer selected mask SiNx by BOE; finally, forming a second ring-shaped electrode on the upper surface of the first P-doped DBR by photolithography process, electron beam evaporation metal layer process and stripping process; (4) oxidizing the oxidation isolation pre-preparation layer and the oxidation limiting pre-preparation layer by wet oxidation process to form an oxidation isolation layer and an oxidation limiting layer; (5) referring to the method of step (3), preparing a third ring-shaped electrode on the upper surface of the second N-doped DBR, and preparing a fourth ring-shaped electrode on the upper surface of the second P-doped DBR; (6) on the upper surface of the second P-doped DBR, preparing a microlens by limiting diffusion chemical wet etching of semiconductor material, or preparing a microlens by inkjet printing of polymer material and then photo-curing.

2. The high efficiency vertical cavity surface EML chip with microlens of claim 1, wherein: The quantum well wavelength of the absorption region is 5-99nm shorter than the quantum well wavelength of the resonant cavity.

3. The high efficiency vertical cavity surface EML chip with microlens of claim 1, wherein: The microlens is a polymer material or a semiconductor material.

4. The high efficiency vertical cavity surface EML chip with microlens of claim 3, wherein: The polymer material is PI or BCB; the semiconductor material is GaAs or AlGaAs.

5. The high efficiency vertical cavity surface EML chip with microlens of claim 4, wherein: The material of the microlens is GaAs, and the diameter of the microlens is 5-15μm, and the range of the radius of curvature is 30-80μm.

Images