A low-noise dual-loop undersampling phase-locked loop and its working method

Abstract

The present invention provides a low-noise dual-loop undersampling phase-locked loop and a working method, including a type-II undersampling loop, a type-I undersampling loop, and a frequency-locked loop. Among them, the components included in the frequency-locked loop are a frequency divider, a dead-zone frequency discriminator and phase detector, and charge pump II; the reference signal input terminal is connected to the dead-zone frequency discriminator and phase detector, the dead-zone frequency discriminator and phase detector is connected to charge pump II, charge pump II is connected to a voltage-controlled oscillator, the voltage-controlled oscillator is connected to the frequency divider, and the frequency divider is connected to the dead-zone frequency discriminator and phase detector. Compared with the traditional circuit structure, the present invention breaks the bandwidth limitation of one-tenth of the reference frequency of the type-II phase-locked loop and can suppress the phase noise exceeding one-tenth of the reference frequency.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and particularly relates to a low-noise dual-loop undersampling phase-locked loop and a working method thereof. Background Art

[0002] The phase noise of a PLL is divided into two parts, one is in-band noise and the other is out-of-band noise. For a classical charge-pump phase-locked loop, its in-band noise is mainly contributed by the reference signal and the charge pump, and the deterioration of both noises is proportional to the division ratio N. Its out-of-band noise is mainly contributed by the voltage-controlled oscillator. In a phase-locked loop structure optimized for noise, the undersampling phase-locked loop is very effective in optimizing in-band noise. In the phase-domain model of the undersampling phase-locked loop, there is no N-division as feedback, so its in-band noise is at least deteriorated by N times the reference signal level.

[0003] As Figure 2 shown, this structure mainly includes five parts: SSPD / CP, LF, VCO, and FLL.

[0004] 1. SSPD / CP: Undersampling phase detector / charge pump, the core part of the undersampling phase-locked loop. Different from a general charge-pump phase-locked loop, it converts the phase difference between the reference signal and the output signal into a voltage signal instead of a pulse-width signal. Then, the up and down pull currents are controlled by the voltage and converted into the voltage on the filter.

[0005] 2. LF: Loop filter, which converts the current generated by the charge pump into the control voltage of the VCO, and at the same time filters out the high-frequency components on the control voltage to reduce the ripple.

[0006] 3. VCO: Voltage-controlled oscillator, which generates a corresponding frequency signal according to the control voltage generated by the filter.

[0007] 4. FLL: Frequency-locked loop. Due to the special structure of the undersampling phase detector, the phase-locking condition can be satisfied when the output frequency of the VCO is any integer multiple of the reference frequency. Therefore, the frequency-locked loop is used to pull the output frequency of the VCO to near N times the reference frequency and then stop working, which can not only make the output frequency meet the conditions but also not contribute noise and power consumption during the locking process.

[0008] The main idea of this structure is to use an undersampling phase detector and a charge pump to move the frequency divider in the feedback part of the phase-domain model outside the feedback part, so that the charge pump noise is no longer deteriorated by N times and the loop gain is higher, making it easier to implement a phase-locked loop with a large bandwidth.

[0009] Conventional type-II undersampling phase-locked loops have made great optimizations for charge pump noise. However, at the same bandwidth, the noise of the VCO is not better suppressed. At this time, the in-band noise is dominated by the crystal oscillator, and the out-of-band noise is dominated by the VCO. At the offset frequency near the bandwidth, the contributions of the two cross each other. When the phase noise performance of the VCO is not very good, a convex hull will appear in the total phase noise of the loop outside the bandwidth. Such a situation is obviously not desirable. Therefore, other methods need to be adopted to suppress the out-of-band VCO noise to obtain a relatively flat phase noise spectrum. Summary of the Invention

[0010] The purpose of the present invention is to solve the defects existing in the above-mentioned prior art, and to provide a low-noise dual-loop undersampling phase-locked loop and a working method. Compared with the traditional circuit structure, the present invention breaks through the bandwidth limitation of one-tenth of the reference frequency of the type-II phase-locked loop, and can suppress the phase noise exceeding one-tenth of the reference frequency.

[0011] In the present invention, by adding a type-I undersampling loop, a loop with a bandwidth exceeding one-tenth of the crystal oscillator frequency is realized. At the same time, better suppression of the out-of-band noise of the voltage-controlled oscillator (VCO) is achieved, and the K of the type-I undersampling loop is controlled VCO to be one order of magnitude lower than that of the type-II undersampling loop, reducing the spurs brought by the addition of the extra loop. The total transfer function of the system is determined by the type-II undersampling loop, and the type-I undersampling loop only plays an auxiliary role and has little impact on other performances, realizing an undersampling phase-locked loop with low phase noise.

[0012] The present invention adopts the following technical solutions:

[0013] A low-noise dual-loop undersampling phase-locked loop includes a type-II undersampling loop, a type-I undersampling loop, and a frequency locking loop.

[0014] Among them, the components included in the frequency locking loop are a frequency divider, a dead-zone frequency discriminator and phase detector, and charge pump II; the reference signal input terminal is connected to the dead-zone frequency discriminator and phase detector, the dead-zone frequency discriminator and phase detector is connected to charge pump II, charge pump II is connected to the voltage-controlled oscillator, the voltage-controlled oscillator is connected to the frequency divider, and the frequency divider is connected to the dead-zone frequency discriminator and phase detector;

[0015] The type-II undersampling loop includes an undersampling phase detector I, charge pump I, loop filter I, and pulse generator; the reference signal input terminal is connected to the undersampling phase detector I and the pulse generator, the undersampling phase detector I is connected to charge pump I, charge pump I is connected to the pulse generator and loop filter I, and loop filter I is connected to the voltage-controlled oscillator;

[0016] The type-I undersampling loop includes an undersampling phase detector II, a buffer, and a loop filter II; the reference signal input terminal is connected to the undersampling phase detector II, the undersampling phase detector II is connected to the buffer, the buffer is connected to the loop filter II, and the loop filter II is connected to the voltage-controlled oscillator.

[0017] The voltage-controlled oscillator is composed of multiple ring oscillators connected in series.

[0018] The dead-zone frequency and phase detector includes two D flip-flops and two D flip-flops controlled by reference and divided-by-frequency inverted signals. After the two D flip-flops are coupled, they are then connected to two D flip-flops controlled by divided-by-frequency inverted signals.

[0019] The undersampling phase detector I is composed of a buffer and a sampler connected in series. The number of buffers is multiple stages.

[0020] In the type-I undersampling loop, in order to reduce the influence of charge sharing between capacitors on the sampling process, the value of the sampling capacitor C1 should be much larger than the value of C2, and an isolation buffer buffer is added between the loop filter II and C2, which can not only provide gain and increase the loop bandwidth, but also avoid charge sharing between two capacitors with too large a capacitance difference.

[0021] The undersampling phase detector II is composed of a buffer, a first-stage sampler, and a second-stage sampler connected in series. The buffer is multiple stages.

[0022] A working method of a low-noise dual-loop undersampling phase-locked loop includes the following steps:

[0023] When starting to work, the frequency-locked loop takes the lead. The reference signal is input to the dead-zone frequency and phase detector. After the output signal of the voltage-controlled oscillator VCO passes through the dead-zone frequency and phase detector, the phase error between the frequency of the voltage-controlled oscillator VCO and the frequency of the reference signal is output. The dead-zone frequency and phase detector transmits it to the charge pump II to charge and discharge the loop filter I (the frequency-locked loop and the type-II undersampling loop share a loop filter I). The loop filter pulls the frequency of the voltage-controlled oscillator VCO to near the reference signal frequency, and then the frequency-locked loop stops working;

[0024] The output signal of the voltage-controlled oscillator VCO is voltage-sampled through the type-I undersampling loop and the type-II undersampling loop respectively. The sampled voltage of the type-I undersampling loop is input to the loop filter II (filter capacitor) through the buffer buffer to obtain the control voltage. The type-II undersampling loop controls the magnitude of the up and down pull currents with the sampled differential sampling voltage, charges and discharges the loop filter I, obtains the control voltage, makes the control voltage tend to be stable, the loop is locked, and the N-fold crystal oscillator output frequency is output.

[0025] The voltage of the type-I undersampling loop and the type-II undersampling loop simultaneously controls the output frequency of the VCO, but in essence, it is still dominated by the type-II loop.

[0026] Specifically, the differential output of the voltage-controlled oscillator has two signals, VCON and VCOP. VCOP is the positive-phase signal, and VCON is the anti-phase signal. After passing through buffers with the same number of stages, the rising edge of the reference signal is used for sampling to obtain the phase information of the voltage-controlled oscillator.

[0027] The specific process is as follows: when REF is at a low level and REFB is at a high level, the NMOS / PMOS of the undersampling phase detector are both turned on. The voltage on the sampling capacitor C1 changes with VCON / P. When REF changes from a low level to a high level, that is, when the rising edge arrives, the NMOS / PMOS are both turned off, resulting in no discharge path for the charge on the sampling capacitor C1. Therefore, the voltage on C1 will remain unchanged at the moment of turning off. This process is called sampling.

[0028] When REF is at a high level, the NMOS / PMOS are both turned off, and at this time, the voltage on C1 remains unchanged. This process is called holding.

[0029] When the positive sampling voltage Vsamp is greater than the negative sampling voltage Vsamn, it indicates that there are less than an integer number of voltage-controlled oscillator VCO cycles within one period. Then, the voltage-controlled oscillator VCO lags behind the crystal oscillator in phase. After that, the charge pump I charges and discharges the loop filter I to adjust the control voltage.

[0030] Although the addition of the type-I undersampling loop can suppress out-of-band noise, it also introduces additional spurs. Therefore, the gain of the type-I undersampling loop that controls the oscillation frequency of the voltage-controlled oscillator VCO cannot be too large. So, in the present invention, K vco1 The ratio is K vco2 is one order of magnitude smaller.

[0031] When the time difference between the divided signal and the reference signal is greater than half of the clock period, that is, there is still a certain distance between the output frequency and the target frequency. At this time, the frequency-locked loop works and outputs a large current to quickly adjust the output frequency to near the target frequency. When the time difference between the divided signal and the reference signal is less than half of the clock period, the frequency discriminator and phase detector enter the dead zone, and the frequency-locked loop stops working.

[0032] The beneficial effects of the present invention:

[0033] 1. In the prior art, both of the dual loops are type-I loops. The defect of this kind of loop is that the noise suppression in the flicker noise region of the VCO is not sufficient, which has an impact on the phase noise in the near end. The main loop of the present invention, that is, the type-II loop, does not have this shortcoming.

[0034] 2. Existing phase-locked loops do not use a frequency divider, so they cannot multiply the reference signal, i.e., the crystal oscillator, and the output signal noise is approximately equal to the superposition of the reference signal and the VCO noise. The advantage of the undersampling structure of the present invention is that it can effectively suppress the in-band noise, making it approximately n times worse than the reference signal. In addition, it can also perform frequency multiplication.

[0035] 3. If a frequency divider is used, the output frequency of the VCO is an integer multiple of the reference signal. At this time, the structure of the frequency converter needs to change. Assuming that the output frequency of the VCO is n times that of the crystal oscillator, then in addition to the output of the VCO, the frequency converter also needs an input with a frequency of (N - 1) times the reference frequency, which requires an additional structure.

[0036] 4. The type-II loop can effectively suppress the noise in the VCO flicker noise region, but the bandwidth is limited by one-tenth of the reference frequency. The type-I loop is not subject to this limitation, but it has insufficient noise suppression for the VCO flicker noise region. The present invention combines the two loops to effectively reduce the noise contributed by the VCO. The in-band noise of the charge pump type phase-locked loop is affected by the charge pump noise. In order to achieve better phase noise in the full frequency band, the present invention adopts an undersampling structure to realize a phase-locked loop with better phase noise in the full frequency band. Description of the Drawings

[0037] Figure 1 It is a schematic diagram of the phase domain model of the undersampling phase-locked loop of the present invention;

[0038] Figure 2 It is a structural diagram of a typical undersampling phase-locked loop;

[0039] Figure 3 It is a principle block diagram of the undersampling dual-loop PLL proposed by the present invention;

[0040] Figure 4(a) and Figure 4(b) are schematic circuit diagrams of the type-II loop undersampling phase detector;

[0041] Figure 5 It is a relationship diagram of the sampling voltage and the phase lead or lag;

[0042] Figure 6(a) and Figure 6(b) are schematic circuit diagrams of the type-I undersampling phase detector;

[0043] Figure 7(a) is a dead zone frequency discriminator phase detector;

[0044] Figure 7(b) is the output waveform of the dead zone frequency discriminator phase detector;

[0045] Figure 8(a) is the phase noise of each part and the total of the present invention;

[0046] Figure 8(b) is the VCO and the total phase noise with and without the type-I loop;

[0047] Figure 9 This is the structural circuit diagram of the present invention;

[0048] In the figure, 1 - frequency-locked loop;

[0049] 101 - dead-zone frequency discriminator and phase detector, 102 - frequency divider, 103 - charge pump II;

[0050] 2 - type-II undersampling loop;

[0051] 201 - undersampling phase detector I, 202 - charge pump I, 203 - loop filter I;

[0052] 3 - type-I undersampling loop;

[0053] 301 - undersampling phase detector, 302 - loop filter II, 303 - buffer;

[0054] 4 - voltage-controlled oscillator;

[0055] 401 - ring oscillator. Detailed implementation manners

[0056] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0057] PLL: Phase-locked loop

[0058] SSPD / CP: Undersampling phase detector / Charge pump

[0059] FLL: Frequency-locked loop

[0060] DZPFD: Dead-zone frequency discriminator and phase detector

[0061] Buffer: Buffer

[0062] The frequency synthesizer based on the phase-locked loop (PLL) is an important part in various applications, especially in communication systems. The frequency synthesizer needs to have good phase noise, jitter and spurious performance. For the classical charge pump phase-locked loop (CPPLL), there is a trade-off relationship between phase noise and spurious, and under fixed specifications, it is impossible to optimize both of them simultaneously. For example Figure 1As shown, the undersampling phase-locked loop (SSPLL) optimizes the in-band noise and can achieve good in-band noise performance. However, due to its own bandwidth limitation, it cannot further suppress the out-of-band noise. The present invention will further suppress the out-of-band noise of the undersampling phase-locked loop by adding an additional loop, so that the phase-locked loop has better noise performance.

[0063] As Figure 9 shown, a low-noise dual-loop undersampling phase-locked loop of the present invention includes a type-II undersampling loop 2, a type-I undersampling loop 3, and a frequency-locked loop 1.

[0064] Among them, the components included in the frequency-locked loop 1 are a frequency divider 102, a dead-zone frequency discriminator and phase detector 101, and a charge pump II 103; the reference signal input terminal is connected to the dead-zone frequency discriminator and phase detector 101, the dead-zone frequency discriminator and phase detector 101 is connected to the charge pump II 103, the charge pump II 103 is connected to the voltage-controlled oscillator 4, the voltage-controlled oscillator 4 is connected to the frequency divider 102, and the frequency divider 102 is connected to the dead-zone frequency discriminator and phase detector 101;

[0065] The type-II undersampling loop 2 includes an undersampling phase detector I 201, a charge pump I 202, a loop filter I 203, and a pulse generator 204; the reference signal input terminal is connected to the undersampling phase detector I 201 and the pulse generator 204, the undersampling phase detector I 201 is connected to the charge pump I 202, the charge pump I 202 is connected to the pulse generator 204 and the loop filter I 203, and the loop filter I 203 is connected to the voltage-controlled oscillator 4.

[0066] The undersampling phase detector I 3 is composed of a buffer and a sampler connected in series. The number of buffers is multiple.

[0067] The voltage-controlled oscillator 4 outputs two differential signals VCON and VCOP, which are sampled by the sampler in the undersampling phase detector I 201 to obtain a voltage signal with half of the oscillation waveform and half of the sampling voltage. The type-II undersampling loop 2 can directly use this signal to control the UP and DN currents of the charge pump I.

[0068] The type-I undersampling loop 3 includes an undersampling phase detector II 301, a buffer 302, and a loop filter II 303;

[0069] The reference signal input terminal is connected to the undersampling phase detector II 301, the undersampling phase detector II 301 is connected to the buffer 302, the buffer 302 is connected to the loop filter II 303, and the loop filter II 303 is connected to the voltage-controlled oscillator 4.

[0070] The undersampling phase detector II 301 is composed of a buffer, a first-stage sampler, and a second-stage sampler connected in series. The buffer is multiple.

[0071] The voltage-controlled oscillator 4 outputs two differential signals VCON and VCOP. The signals are sampled by a first-stage sampler in the undersampling phase detector I 201 to obtain a voltage signal with half of the oscillation waveform and half of the sampling voltage. Then, the signal is sampled by a second-stage sampler to obtain a signal of the full-cycle sampling voltage. After being input into a buffer, a control voltage is obtained to control the voltage-controlled oscillator with the control voltage.

[0072] Compared with the type-II undersampling loop 3, the reason why the type-I undersampling loop 2 requires one more sampler (circuit) is that it directly uses voltage for control. Due to pulse control, it only needs to be a DC voltage when it is turned on.

[0073] Among them, the voltage-controlled oscillator 4 is composed of a plurality of ring oscillators 401 connected in series.

[0074] The dead zone frequency discriminator and phase detector 101 includes two D flip-flops and two D flip-flops controlled by reference and frequency-divided reverse signals. After the two D flip-flops are coupled, they are then connected to two D flip-flops controlled by frequency-divided reverse signals.

[0075] When the rising edge of the reference signal or the frequency-divided signal is input into the D flip-flop, the D flip-flop will output a rising edge simultaneously. When the rising edge of the other signal arrives, the other D flip-flop will also output a rising edge. At this time, both the UP and DN signals are at a high level, and the RESET signal becomes a high level. At this time, both D flip-flops are reset, and the output becomes a low level. The width difference of the UP and DN pulse signals output during this process represents the phase difference between the two. This is the working principle of a conventional frequency discriminator and phase detector. However, the dead zone frequency discriminator and phase detector adds two other D flip-flops controlled by reference and frequency-divided reverse signals. When the phase difference between the two is small, the signal of the previous-stage flip-flop will not be transmitted to the charge pump, so the control voltage cannot be changed.

[0076] A working method of a low-noise dual-loop undersampling phase-locked loop includes the following steps:

[0077] When starting to work, the frequency-locked loop 1 plays a leading role. The reference signal is input into the dead zone frequency discriminator and phase detector 101. After the output signal of the voltage-controlled oscillator 4 VCO passes through the dead zone frequency discriminator and phase detector 101, the phase error between the frequency of the voltage-controlled oscillator 4 VCO and the frequency of the reference signal is output. The dead zone frequency discriminator and phase detector 101 transmits it to the charge pump II 103 to charge and discharge the loop filter I 203 (the frequency-locked loop 1 and the type-II undersampling loop 2 share a loop filter I 203), pulling the frequency of the voltage-controlled oscillator 4 VCO near the frequency of the reference signal. Then, the frequency-locked loop in the charge pump II 103 stops working;

[0078] The output signals of the voltage-controlled oscillator 4VCO are respectively voltage-sampled through the type-I undersampling loop 3 and the type-II undersampling loop 2. The sampled voltage of the type-I undersampling loop 3 is input to the loop filter II 303 (filter capacitor) through the buffer 302Buffer to obtain the control voltage. The type-II undersampling loop 201 controls the magnitude of the up / down pull current of the sampled differential sampling voltage, charges and discharges the loop filter I 203, obtains the control voltage, makes the control voltage tend to be stable, locks the loop, and outputs N times the crystal oscillator output frequency.

[0079] The voltages of the type-I undersampling loop 3 and the type-II undersampling loop 2 simultaneously control the output frequency of the VCO, but in essence, it is still dominated by the type-II loop.

[0080] The present invention proposes a low-noise dual-loop undersampling phase-locked loop, which is a dual-loop undersampling phase-locked loop with an auxiliary type-I undersampling loop 3 added. An additional sampling branch is added to the type-II undersampling phase detector 201 to form the type-I undersampling loop 3, and then it is connected to the loop filter II 303 of the type-I undersampling through the isolation buffer 302Buffer. This structure mainly consists of the type-II undersampling loop 2, the type-I undersampling loop 3, and the frequency-locked loop 1.

[0081] (1) Type-II undersampling loop

[0082] The type-II undersampling loop 2 of the present invention is basically the same as the classical undersampling phase-locked loop. The circuit schematic diagram of the undersampling phase detector 201 is as Figure 4(a) - Figure 4(b) shown. The differential output of the voltage-controlled oscillator 4 has two signals, VCON and VCOP. VCOP is the positive-phase signal, and VCON is the anti-phase signal. After passing through the buffer Buffer of the same number of stages, the rising edge of the reference signal is used for sampling to obtain the phase information of the voltage-controlled oscillator 4.

[0083] The specific process is as follows: When REF is at a low level, REFB is at a high level, and the NMOS / PMOS of the sampler are both turned on. The voltage on the sampling capacitor C1 changes with VCON / P. When REF changes from a low level to a high level, that is, when the rising edge arrives, the NMOS / PMOS are both turned off, resulting in no discharge path for the charge on the sampling capacitor C1. Therefore, the voltage on C1 will remain unchanged at the moment of turning off. This process is called sampling. When REF is at a high level, the NMOS / PMOS are both turned off, and at this time, the voltage on C1 remains unchanged. This process is called holding. So the essence of the undersampling phase detector is a sample-and-hold circuit.

[0084] The output waveforms of the undersampling phase detector I 201 and the charge pump I 202 circuits are as Figure 5As shown, when the positive sampling voltage Vsamp is greater than the negative sampling voltage Vsamn, it indicates that there are less than an integer number of voltage-controlled oscillator 4VCO cycles within one period. Then, the voltage-controlled oscillator 4VCO lags behind the crystal oscillator in phase. Subsequently, the undersampling charge pump I 201 charges and discharges the loop filter I 203 to adjust the control voltage, ultimately achieving the locking effect.

[0085] (2) Type-I undersampling loop

[0086] The advantage of the Type-I undersampling loop 3 compared to the Type-II loop is that it is not affected by the charge pump continuity assumption. The loop bandwidth can exceed one-tenth of the reference frequency. The larger the bandwidth, the stronger the suppression of the voltage-controlled oscillator 4VCO noise. Therefore, adding a Type-I undersampling loop with a large bandwidth helps reduce the out-of-band noise of the phase-locked loop.

[0087] As Figure 6(a) - Figure 6(b) shown, the sampling process of the Type-I undersampling loop 3 is similar to that of the Type-II undersampling loop 2. However, since the sampled voltage signal needs to continuously act on the loop filter II 303, one more level of sample and hold is required to achieve a DC signal for the voltage throughout the entire period. At the same time, to reduce the impact of charge sharing between capacitors on the sampling process, the value of the sampling capacitor C1 should be much larger than that of C2, and an isolation buffer 302Buffer is added between the loop filter II 303 and C2, which can not only provide gain and increase the loop bandwidth but also avoid charge sharing between two capacitors with significantly different capacitance values.

[0088] Although the addition of the Type-I undersampling loop 3 can suppress out-of-band noise, it also introduces additional spurs. Therefore, the gain for controlling the oscillation frequency of the voltage-controlled oscillator 4VCO in the Type-I undersampling loop cannot be too large. So, in the present invention, K vco1 The ratio is K vco2 is one order of magnitude smaller.

[0089] (3) Frequency locking loop

[0090] The characteristic of the undersampling phase detector is that frequencies that are any integer multiple of the reference frequency can satisfy the locking condition. To obtain the desired frequency, an additional frequency locking loop 1 is needed to pull the output frequency near the desired frequency and then turn off the frequency locking loop 1, which can avoid the influence of the frequency locking loop on the main loop and additional power consumption. The structure of the frequency locking loop 1 is similar to that of a general Type-II charge pump phase-locked loop. The biggest difference is that its frequency discriminator and phase detector have a dead zone, as Figure 7(a) - Figure 7(b)As shown, when the time difference between the divided signal and the reference signal is greater than half of the clock period, that is, there is still a certain distance between the output frequency and the target frequency. At this time, the frequency locking loop works, outputs a large current, and quickly adjusts the output frequency to near the target frequency. When the time difference between the divided signal and the reference signal is less than half of the clock period, the frequency discriminator and phase detector enter the dead zone, the frequency locking loop 1 stops working, and the main loop works.

[0091] Embodiment

[0092] As shown in FIGS. 8(a) and 8(b), FIG. 8(a) shows the overall noise of the undersampling phase-locked loop. Its in-band noise is basically equivalent to the crystal oscillator noise, which conforms to the properties of the traditional undersampling phase-locked loop. Its out-of-band noise is dominated by the voltage-controlled oscillator 4VCO. FIG. 8(b) shows the noise comparison with and without the type-I undersampling loop 301 added, which is the key innovation point of the present invention. It can be seen that the out-of-band noise is optimized by nearly 10 dB in the case of adding the type-I undersampling loop 301 compared with the case without adding the type-I undersampling loop 301. Therefore, compared with the traditional SSPLL, in the region dominated by the voltage-controlled oscillator 4VCO noise, the phase noise of the PLL of the present invention has been significantly improved.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-noise dual-loop undersampling phase-locked loop, characterized in that , including a type-II undersampling loop, a type-I undersampling loop, and a frequency locking loop; among them, the components included in the frequency locking loop are a frequency divider, a dead-zone frequency discriminator and phase detector, and charge pump II; the reference signal input terminal is connected to the dead-zone frequency discriminator and phase detector, the dead-zone frequency discriminator and phase detector is connected to charge pump II, charge pump II is connected to a voltage-controlled oscillator, the voltage-controlled oscillator is connected to the frequency divider, and the frequency divider is connected to the dead-zone frequency discriminator and phase detector; The type-II undersampling loop includes an undersampling phase discriminator I, charge pump I, loop filter I, and pulse generator; the reference signal input terminal is connected to the undersampling phase discriminator I and the pulse generator, the undersampling phase discriminator I is connected to charge pump I, charge pump I is connected to the pulse generator and loop filter I, and loop filter I is connected to the voltage-controlled oscillator; The type-I undersampling loop includes an undersampling phase discriminator II, a buffer, and loop filter II; the reference signal input terminal is connected to the undersampling phase discriminator II, the undersampling phase discriminator II is connected to the buffer, the buffer is connected to loop filter II, and loop filter II is connected to the voltage-controlled oscillator; The undersampling phase discriminator I is composed of a buffer and a sampler connected in series; the undersampling phase discriminator II is composed of a buffer, a first-stage sampler, and a second-stage sampler connected in series; The value of the sampling capacitor C1 in the undersampling phase discriminator II is much larger than the value of the sampling capacitor C2 in the undersampling phase discriminator II; Undersampling phase discriminator II: After the VCON signal is driven and amplified, it enters the first-stage NMOS / PMOS switch pair transistor. The output terminal of the first-stage NMOS / PMOS switch pair transistor is connected to the sampling capacitor C1 and the second-stage NMOS / PMOS switch pair transistor. The output terminal of the second-stage switch pair transistor is connected to the sampling capacitor C2 and the isolation buffer. The isolation buffer outputs the Vctrl 1 signal. The Vctrl signal is connected to the control voltage and capacitance terminal of the voltage-controlled oscillator. One end of the three capacitors is connected to the output signal, and the other end is connected to the ground; After the VCOP signal is driven and amplified, it enters the first-stage NMOS / PMOS switch pair transistor. The output terminal of the first-stage NMOS / PMOS switch pair transistor is connected to the sampling capacitor C1 and the second-stage NMOS / PMOS switch pair transistor. The output terminal of the second-stage switch pair transistor is connected to the sampling capacitor C2 and the isolation buffer. The isolation buffer outputs the Dummy signal. The Dummy signal is connected to the control voltage and capacitance terminal of the voltage-controlled oscillator. One end of the three capacitors is connected to the output signal, and the other end is connected to the ground.

2. The low-noise dual-loop undersampling phase-locked loop according to claim 1, characterized in that, Among them, the voltage-controlled oscillator is composed of multiple ring oscillators connected in series.

3. The low-noise dual-loop undersampling phase-locked loop according to claim 1, characterized in that The dead-zone frequency discriminator and phase detector includes two D flip-flops and two D flip-flops controlled by reference and frequency-divided reverse signals. After the two D flip-flops are coupled, they are then connected to two D flip-flops controlled by frequency-divided reverse signals.

4. The working method of the low-noise double-loop undersampling phase-locked loop according to claim 1, characterized in that, It includes the following steps: Step 1. The reference signal is input to the dead-zone frequency discriminator and phase detector. After the output signal of the voltage-controlled oscillator passes through the dead-zone frequency discriminator and phase detector, the phase error between the voltage-controlled oscillator frequency and the reference signal frequency is output. The dead-zone frequency discriminator and phase detector transmits it to charge pump II to charge and discharge loop filter I, pulling the VCO frequency of the voltage-controlled oscillator near the reference signal frequency. After that, the frequency locking loop stops working; Step 2. The output signal of the voltage-controlled oscillator is subjected to voltage sampling through a type-I undersampling loop and a type-II undersampling loop respectively. The sampled voltage of the type-I undersampling loop is input to loop filter II through a buffer to obtain a control voltage. Step 3. The type-II undersampling loop controls the magnitude of the up / down pull current with the sampled differential sampled voltage, charges and discharges loop filter I, obtains a control voltage, makes the control voltage tend to be stable, locks the loop, and outputs N times the crystal oscillator output frequency.

5. The working method of the low-noise double-loop undersampling phase-locked loop according to claim 4, characterized in that, Specifically for Step 3, when REF is at a low level in the type-II undersampling loop, REFB is at a high level, and the NMOS / PMOS of the undersampling phase detector are turned on simultaneously. The voltage on sampling capacitor C1 changes with VCON / P. When REF changes from a low level to a high level, that is, when the rising edge arrives, the NMOS / PMOS are turned off simultaneously, resulting in no discharge path for the charge on sampling capacitor C1. Therefore, the voltage on C1 will remain unchanged at the moment of turning off. This process is called sampling. When REF is at a high level, the NMOS / PMOS are turned off simultaneously, and at this time the voltage on C1 remains unchanged. This process is called holding.

6. The operating method of the low-noise dual-loop undersampling phase-locked loop according to claim 4 or 5, characterized in that It also includes that when the positive sampled voltage is greater than the negative sampled voltage, it indicates that there are less than an integer number of voltage-controlled oscillator cycles in one period. Then the phase of the voltage-controlled oscillator lags behind that of the crystal oscillator, and then charge pump II charges and discharges loop filter to adjust the control voltage.

7. The working method of the low-noise double-loop undersampling phase-locked loop according to claim 4, characterized in that The gain of the type-I undersampling loop for controlling the oscillation frequency of the voltage-controlled oscillator is one order of magnitude smaller than that of the type-II undersampling loop for controlling the oscillation frequency of the voltage-controlled oscillator.

8. The operating method of the low-noise dual-loop undersampling phase-locked loop according to claim 4, characterized in that, Specifically for Step 1: When the time difference between the signal after frequency division by the frequency divider and the reference signal is greater than half of the clock period, that is, there is still a certain distance between the output frequency and the reference frequency. At this time, the frequency-locked loop works and outputs a large current to quickly adjust the output frequency to near the target frequency. When the time difference between the signal after frequency division and the reference signal is less than half of the clock period, the frequency discriminator and phase detector enter the dead zone, and the frequency-locked loop stops working.

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