Channel coding method and processing device, communication method and device

Abstract

A channel coding method and processing device, a communication method and device. The channel coding method includes: using a QC-LDPC code generator matrix or a check matrix to perform channel coding or channel decoding on a code stream, wherein the code rate of the generator matrix or the check matrix is ​​1 / 6, 1 / 4 or 1 / 3. The method can be used in low signal-to-noise ratio and long-distance transmission environments.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to a channel coding method and processing device, and a communication method and device. Background Art

[0002] In communication systems, in order to combat interference caused by channels and improve the reliability of information transmission, forward error correction code (FEC) technology is often used, that is, the redundancy of information is increased at the sending end, and the receiving end uses this redundant information for error correction.

[0003] like Figure 1 As shown in FIG. 1 , a typical coding process includes source, source coding, channel coding, modulation, channel, demodulation, channel decoding, source decoding and destination, wherein channel coding can use forward error correction technology. Current channel coding technologies mainly include block code, convolutional code, Turbo code, LDPC code, etc.

[0004] The basic principle of channel coding is to take binary coding as an example, Figure 2 As shown in the figure, some redundant bit sequences p are added to the end of the information bit sequence u to obtain the codeword sequence c = [u, p]. Then, the codeword sequence is modulated and sent to the channel. At the receiving end, the redundant information p is used to perform error correction and error detection on the information bit sequence part u. This error correction and error detection operation is called decoding.

[0005] LDPC codes are widely used in various communication systems due to their performance close to the Shannon limit and high throughput brought by parallel decoding, such as 5G NR (fifth-generation mobile communication network air interface standard), WiFi (wireless Fidelity), DVB (digital video broadcasting) or optical communication systems. Summary of the invention

[0006] At least one embodiment of the present disclosure provides a channel coding method, comprising: using a generator matrix or a check matrix of a QC-LDPC code to channel encode or channel decode a code stream, wherein the code rate of the generator matrix or the check matrix is ​​1 / 6, 1 / 4 or 1 / 3.

[0007] At least one embodiment of the present disclosure provides a processing device for channel coding, comprising: a receiving unit, configured to receive a code stream; a processing unit, configured to use a generator matrix or a check matrix of a QC-LDPC code to perform channel coding or channel decoding on the code stream, wherein the code rate of the generator matrix or the check matrix is ​​1 / 6, 1 / 4 or 1 / 3.

[0008] At least one embodiment of the present disclosure provides a processing device for channel coding, including: a processing unit and a memory, wherein one or more computer program modules are stored in the memory; wherein when the one or more computer program modules are configured to be executed by the processing unit, the channel coding method described in at least one embodiment of the present disclosure is implemented.

[0009] At least one embodiment of the present disclosure provides a non-transitory readable storage medium, wherein the non-transitory readable storage medium stores computer instructions, wherein when the computer instructions are executed by a processor, the channel coding method as described above is implemented.

[0010] At least one embodiment of the present disclosure provides a communication method, including using the above-mentioned channel coding method for processing.

[0011] At least one embodiment of the present disclosure provides a communication device, including the above-mentioned processing device for channel coding. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0013] Figure 1 is a schematic diagram of an exemplary encoding and decoding process;

[0014] Figure 2 Schematic diagram of obtaining a codeword sequence c through an information bit sequence u and a redundant bit sequence p;

[0015] Figure 3 is a schematic diagram of a Tanner graph of an exemplary check matrix;

[0016] Figure 4 is a schematic diagram of a prototype diagram of an exemplary basis matrix;

[0017] Figure 5A A schematic diagram of the Tanner graph of a permutation matrix;

[0018] Figure 5B Schematic diagram of interlacing and replacing the original model;

[0019] Fig. 6A , Figure 6B and Figure 6C The permutation matrix forms are 1 / 6, 1 / 4 and 1 / 3 code rates respectively;

[0020] Figure 7A schematic diagram of a method for constructing a base matrix of a permutation matrix for a QC-LDPC code according to an embodiment of the present disclosure;

[0021] Figure 8 is a schematic diagram of a process of designing a base matrix according to an embodiment of the present disclosure;

[0022] Fig. 9 A schematic diagram of a method for constructing a permutation matrix for a QC-LDPC code according to an embodiment of the present disclosure;

[0023] Fig.10 is a schematic diagram of a short ring in the Tanner graph of an exemplary permutation matrix;

[0024] Fig.11 is a schematic diagram of a short ring in the Tanner graph of an exemplary permutation matrix;

[0025] Fig.12 is a schematic diagram of an exemplary tree expanded with the variable node of the base matrix as the root node;

[0026] Fig.13 A flowchart for performing a tree search;

[0027] Fig.14 A schematic diagram showing the performance of permutation matrices corresponding to three code lengths of 1 / 6 code rate;

[0028] Fig.15 A schematic diagram showing the performance of permutation matrices corresponding to three code lengths of 1 / 4 code rate;

[0029] Fig.16 A schematic diagram showing the performance of permutation matrices corresponding to three code lengths of 1 / 3 code rate;

[0030] Fig.17 A schematic diagram of a processing device provided according to at least one embodiment of the present disclosure is shown;

[0031] Fig.18 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] LDPC code is essentially a linear block code, but the proportion of "1" in the check matrix is ​​relatively low. Each LDPC code can be identified by a generator matrix G, and the codeword can be generated by the product of the information bit and the generator matrix, that is, c = u*G. On the other hand, LDPC code can be represented by the check matrix H instead of the generator matrix G. The relationship between the check matrix and the generator matrix is: G*H T =0. Assume that the check matrix can be written as: H = [H u ,H p ], where H u Corresponding to the information bit part in the check matrix, H p Corresponding to the check bit part in the check matrix. Then, the generator matrix can be written as

[0035] The number of 1s in a row of the check matrix is ​​called the row weight of the row. Correspondingly, the number of 1s in a column is called the column weight of the column. If all rows have the same row weight and all columns have the same column weight, the LDPC code is called a regular code. Otherwise, it is an irregular code. The distribution of row weight and column weight can also be used to analyze LDPC codes. v Indicates the number of column weights, d c represents the number of row weights, λ d Indicates that the column weight is d in d v The proportion of the columns in the weight, ρ d Indicates that the column weight is d in d c The distribution of column weight and row weight can be expressed by the following formula:

[0036]

[0037] In density evolution theory, column weight and row weight determine the performance of LDPC codes.

[0038] Another way to represent LDPC codes is the Tanner graph, which is a bipartite graph. Take the code represented by the following simple check matrix H as an example:

[0039]

[0040] The corresponding Tanner graph is as follows Figure 3 As shown in the Tanner graph, the nodes corresponding to the rows of the matrix H are called check nodes, and the nodes corresponding to the columns of H are called variable nodes. If the value corresponding to the intersection of the rows and columns in the matrix H is 1, there will be a connection in the graph, which is called an edge. Figure 3 In the Tanner graph shown, there are 10 variable nodes and 5 check nodes.

[0041] Tanner graphs are very helpful for studying LDPC codes, such as the loops and perimeters in Tanner graphs. A loop in a Tanner graph is a loop formed by the lines that pass through when starting from a node S and going along the connecting line and returning to the node S. The size of the loop is the number of lines or edges. Figure 3 The bold lines in the graph form a loop. The perimeter of the Tanner graph refers to the size of the smallest loop. In addition, there is also the concept of external information freedom in the Tanner graph. The number of check nodes that are connected to a loop by only one edge is called the external information freedom.

[0042] Structured LDPC codes are also called quasi-cyclic LDPC codes (QC-LDPC codes). Their structure is easy for hardware parallel processing and can achieve high throughput, so they are adopted by many systems. The following matrix P is a permutation matrix of a QC-LDPC code. Each value in the matrix represents a Z*Z submatrix, and Z is called the lifting factor.

[0043]

[0044] When the value in the matrix P is -1, it means a Z*Z all-zero matrix. Other values ​​x represent a matrix obtained by cyclically right-shifting a Z*Z identity matrix by x. See the example below. The actual check matrix is ​​the expansion of P. Taking Z=8 as an example, the following circulant matrix can be obtained:

[0045]

[0046] The basis matrix corresponding to the permutation matrix is ​​defined as follows: the elements greater than or equal to zero in the permutation matrix are 1, and the others are 0. That is, the following B matrix is ​​the basis matrix of the permutation matrix above:

[0047]

[0048] When designing a QC-LDPC code, you can first design a base matrix, and then perform lifting on the base matrix (i.e., determine the cyclic values ​​of the positions that are 1 in the base matrix) to obtain a permutation matrix. The Tanner graph obtained based on the base matrix is ​​called a protograph. For example, the protograph of the above B matrix is ​​as follows Figure 4 shown.

[0049] The lifting of the basis matrix is ​​to replace the original model graph. The process is to replace the original model graph with Z (lifting factor), where Z is a positive integer. For example, taking Z=8 as an example, first copy the above original model graph 8 times, and get the following Figure 5A The Tanner graph shown. Taking P(1,1)=1 as an example,

[0050]

[0051] This represents the matrix obtained by cyclically shifting right by 1 bit, so the original model is interleaved and permuted to obtain Figure 5B Similarly, by interleaving and permuting all elements of the base matrix that are greater than or equal to 0, the Tanner graph of the corresponding check matrix can be obtained.

[0052] The best decoders for Turbo code and LDPC code encoders all use iterative decoding methods. The iterative decoder transmits messages during the iteration process. At this time, the probability density of the transmitted messages is constantly changing during the iteration process. The probability density evolution (DE: density evolution) theory is based on this principle to predict the performance of an LDPC code. Specifically, the probability density evolution theory calculates the probability density of messages based on the distribution of row weight and column weight. The density evolution tool can be used to determine the optimal row and column weight distribution when constructing LDPC codes. Take the following column and row weight distribution as an example:

[0053]

[0054] Assume that the probability of the information transmitted by the check node to the variable node is p (c) , the probability that the variable node transmits information to the check node is p (v) , then the probability of information transmission between variable nodes and check nodes is as follows, where l is the number of iterations, and function Γ -1 (x) is the ф in the decoding calculation -1 The change in probability introduced by the operation of the (x) function.

[0055]

[0056]

[0057] For generating QC-LDPC codes based on a base matrix, the base matrix can be calculated using a density evolution method. For example, the density evolution method can use a protograph extrinsic-information-transfer (PEXIT) algorithm to calculate the base matrix and obtain the probability of the transferred information. For example, the steps of the algorithm are as follows:

[0058] (1) Initialization: Select an E b / N o , initialize σ ch =(σ ch,0 ,…,σ ch,N-1 ),

[0059] R is the bit rate

[0060] (2) From variable node to check node: b ij is the number of edges between variable node j and check node i, when c = i, δ ci =1, otherwise δ ci =0,

[0061]

[0062] (3) From the check node to the variable node: When v = j, δ vj =1, otherwise δ vj =0,

[0063]

[0064] (4) Cumulative mutual information calculation:

[0065]

[0066] (5) The criterion for stopping iteration is: If it is close to 1, stop; otherwise, go to step (2) and continue iterating.

[0067] In the above steps, the function J(x) is:

[0068]

[0069] J(x) and J -1 (x) can be calculated using the following simplified algorithm:

[0070]

[0071]

[0072] As a wireless LAN technology, WiFi is popular all over the world for its convenience, ease of use and low price. WiFi introduced structured QC-LDPC codes in the 802.11n standard to improve the throughput of WiFi networks. However, the QC-LDPC of the 802.11n standard only has several code rates such as 1 / 2, 2 / 3, 3 / 4, and 5 / 6, and lacks low-rate LDPC codes. WiFi's QC-LDPC uses an irregular code repeat-accumulate structure. This structure of LDPC code is easy to implement in hardware while ensuring that the performance meets the requirements.

[0073] Taking the 1 / 2 code rate as an example, as shown in the permutation matrix below, the size of the permutation matrix is ​​12*24, and the lifting factor Z=27 / 54 / 81. The part within the dotted line range corresponding to the check bit is 12*12 in size. This part has a fixed structure, which is easy to implement the encoder. The part outside the red dotted box in front is the part that needs to be designed. The row weight of each row of the base matrix under each code rate of the QC-LDPC of the above WiFi 802.11n standard is at most 1 different, and the total number of 1s in the base matrix is ​​between 79 and 88. For example, taking the 1 / 2 code rate as an example, the row weight of each row in the base matrix is ​​two values ​​of {7, 8}, and the total weight of the base matrix is ​​88.

[0074]

[0075] The QC-LDPC of the 802.11n standard only has the code rates of 1 / 2, 2 / 3, 3 / 4, and 5 / 6, and lacks low-rate LDPC codes. At least one embodiment of the present disclosure provides low-rate LDPC codes applicable to the 802.11n standard while being able to reuse the existing codec structure. These code rates include 1 / 6, 1 / 4, and 1 / 3 code rates, and can be used in low signal-to-noise ratio and long-distance transmission environments.

[0076] In at least one embodiment of the present disclosure, for the permutation matrices of the code rates of 1 / 6, 1 / 4 and 1 / 3, a structure similar to the code rates of 1 / 2, 2 / 3, 3 / 4 and 5 / 6 may be used, and the LDPC codecs of the code rates of 1 / 2, 2 / 3, 3 / 4 and 5 / 6 of the QC-LDPC of the aforementioned 802.11n standard may be reused. For example, Fig. 6A , Figure 6B and Figure 6C The permutation matrices are in the form of 1 / 6, 1 / 4 and 1 / 3 code rates, respectively. In each matrix, x is the cyclic value to be designed. The sizes of these permutation matrices are 20*24, 18*24 and 16*24 respectively.

[0077] The present invention discloses a method for designing a QC-LDPC code and the obtained QC-LDPC code, which includes methods for designing a base matrix, designing a permutation matrix through the base matrix, etc. These methods and the LDPC code and permutation matrix obtained thereby are described below.

[0078] At least one embodiment of the present disclosure provides a method for constructing a base matrix of a permutation matrix for a QC-LDPC code, see Figure 7 The method comprises:

[0079] Step 710, obtaining a code rate of the permutation matrix, and determining the number of columns Ns corresponding to the system bits in the base matrix and the number of rows Nrow of the base matrix according to the code rate;

[0080] Step 720, determining the maximum row weight dc of the basis matrix and the total weight range of the basis matrix, wherein the row weight of each row in the basis matrix is ​​dc or dc-1;

[0081] Step 730, determining a first range of rows with a row weight of dc-1 and a second range of rows with a row weight of dc in the basis matrix according to the total weight range of the basis matrix and the number of rows Nrow of the basis matrix;

[0082] Step 740, performing padding processing on the systematic bit part of each row in the initial basis matrix corresponding to the basis matrix according to the number of rows Nrow of the basis matrix, the total weight range, the first range and the second range to obtain an intermediate basis matrix;

[0083] Step 750: Perform convergence calculation on the intermediate basis matrix to determine whether the intermediate basis matrix converges. In response to the intermediate basis matrix converges, determine that the intermediate basis matrix is ​​a basis matrix.

[0084] For example, the systematic bit portion of the initial basis matrix is ​​completely blank or at least some elements are filled.

[0085] The above-mentioned method for constructing a base matrix for a permutation matrix of a QC-LDPC code in the embodiment of the present disclosure can conveniently construct a base matrix that meets the performance requirements for further constructing a corresponding permutation matrix, especially a permutation matrix for the above-mentioned 1 / 6, 1 / 4 and 1 / 3 code rates.

[0086] For example, in at least one embodiment of the present disclosure, the above-mentioned method for constructing a base matrix of a permutation matrix for a QC-LDPC code further includes: in response to the intermediate base matrix not converging, resetting at least part of the parameters of the intermediate base matrix, re-filling the system bits of each row of the reset intermediate base matrix to obtain a new intermediate base matrix, performing convergence calculation on the new intermediate base matrix again, and in response to the new intermediate base matrix converging, determining the new intermediate base matrix as the base matrix.

[0087] For example, in at least one embodiment of the present disclosure, in an example of step 750, performing convergence calculation includes: obtaining a signal-to-noise ratio (SNR) and a number of iterations, and performing a convergence calculation using a density evolution tool (e.g., Prototype Extra-Graph Information Transfer (PEXIT)) based on the signal-to-noise ratio and the number of iterations.

[0088] It should be noted that the above steps 710 to 750 are not limited to be executed in the above order, and the various steps can be executed interchangeably or in parallel as long as there is no conflict. For example, step 710 and step 720 can be executed interchangeably or in parallel.

[0089] In at least one embodiment, the code rate of the permutation matrix to be designed is 1 / 6, 1 / 4 or 1 / 3. For example, the total weight range of the corresponding base matrix is ​​79 to 88; for the code rate of 1 / 6, the maximum row weight dc = 5 or 4; for the code rate of 1 / 4, the maximum row weight dc = 5; for the code rate of 1 / 3, the maximum row weight dc = 6 or 5. In this way, it can be multiplexed with the codec of the LDPC code with a code rate of 1 / 2 to 5 / 6, and can be used in low signal-to-noise ratio and long-distance transmission environments, while also reducing development costs and manufacturing costs.

[0090] In at least one embodiment of the present disclosure, the codec performs encoding or decoding based on the permutation matrix, and processes according to the rows of the permutation matrix, for example, one clock cycle processes one element in the permutation matrix, and sets, for example, two processing units to process the elements in the permutation matrix in a pipeline manner (for example, row by row). At this time, the inventors note that if the row weights of the permutation matrix (for example, two adjacent rows) differ greatly, the speeds of the two processing units will not match, and more additional clock cycles are required to wait at this time, so the implementation of the decoder hardware will be more troublesome and affect the decoding speed. Therefore, when designing the base matrix, in at least one embodiment of the present disclosure, the row weights of two adjacent rows differ by at most 1 (with the same strategy as the WiFi high code rate QC-LDPC code). In addition, the total decoding speed depends on the number of 1s in the base matrix, so it is selected to limit the total weight of the base matrix to 79 to 88, and reuse the clock frequency of the codec for the LDPC code with a code rate of, for example, 1 / 2 to 5 / 6, or the clock frequency is proportionally scaled with the bandwidth. In addition, the memory cells of the codec are set according to the total weight of the base matrix, so that the total weight is 79 to 88, and no additional memory cells are added to the codec of the LDPC code with a code rate of, for example, 1 / 2 to 5 / 6. In addition, the above-mentioned row weight can make the LDPC code have better performance than the smaller row weight.

[0091] The following uses the code rate of 1 / 6, 1 / 4 or 1 / 3 as an example to illustrate the process of designing the base matrix. Figure 8In addition, for code rates of 1 / 6, 1 / 4, and 1 / 3, the sizes of the permutation matrices are 20*24, 18*24, and 16*24, respectively, and the corresponding permutation matrix forms are Fig. 6A , Figure 6B and Figure 6C As shown, in each permutation matrix to be designed, x is the cycle value to be designed.

[0092] like Figure 8 As shown, in step 810, the maximum row weight dc of the basis matrix to be designed is determined. For example, the row weight of each row of the basis matrix is ​​randomly selected from {dc, dc-1}, for example:

[0093] a) For 1 / 6 code rate, the maximum row weight dc = 5 or 4;

[0094] b) For 1 / 4 code rate, the maximum row weight dc = 5;

[0095] c) For 1 / 3 code rate, the maximum row weight dc=6 or 5.

[0096] The total weight of the basis matrix to be designed is set in the range of 79 to 88. In step 820, the range of the number of rows with a row weight of dc-1 in the basis matrix is ​​determined, for example, a maximum of M rows, and the range of the number of rows with a row weight of dc is determined, for example, a maximum of N rows. For example:

[0097] a) For 1 / 6 code rate, dc=5: M=20, N=8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0;

[0098] b) For 1 / 6 code rate, dc = 4: M = 1, N = 20;

[0099] c) For 1 / 4 code rate, dc=5: M=18, N=16 / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7;

[0100] d) For 1 / 3 code rate, dc=6: M=16, N=8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0;

[0101] e) For 1 / 3 code rate, dc=5: M=1, N=16.

[0102] The above value selection method is only an example. For example, the value of N may be fixed, and a value range of M may be given. For example, for a code rate of 1 / 6, dc=5:N=8, and M=12-20.

[0103] In step 830, the number of columns Ns corresponding to the systematic bits in the base matrix is ​​set for use in randomly generating the base matrix element positions, and the number of rows Nrow of the base matrix is ​​determined. For example, further reference may be made to Figure 6A to Figure 6C :

[0104] a) For a 1 / 6 code rate, Ns = 4 and Nrow = 20;

[0105] b) For a 1 / 4 code rate, Ns = 6 and Nrow = 18;

[0106] c) For a 1 / 3 code rate, Ns = 8 and Nrow = 16.

[0107] In step 840, the signal-to-noise ratio (SNR) and the number of iterations for the PEXIT tool are set.

[0108] After setting the above parameters, the processing is carried out from the first row to the last row of the base matrix to be designed, for example, processing each row sequentially one by one. In each processing, the number of rows with a current row weight of dc and the number of rows with a row weight of dc - 1 in the base matrix to be designed need to be recorded, denoted as Ndc and Ndc1 respectively, and the initial values of these two examples are both 0. In step 850, Ndc and Ndc1 are initialized to 0, and the index rowindex of the current row is initialized to 0 (corresponding to the 0th row).

[0109] For the current row, if Ndc < N and Ndc1 < M, then randomly select one from {dc, dc - 1} as the row weight of this row. Assume the row weight is d, and at the same time add 1 to Ndc or Ndc1 accordingly; if Ndc ≥ N, then select dc - 1 as the row weight d of this row; if Ndc1 ≥ M, then select dc as the row weight d of this row. It should be noted that there will be no situation where Ndc ≥ N and at the same time Ndc1 ≥ M. Further, determine the current row weight of the current row (for example, if there are already non-zero elements (such as 1) except for the loop value x to be designed, then the current row weight of the current row is greater than 1), denoted as dcurr, then the row weight to be supplemented is ds = d – dcurr, and then randomly select ds positions from the positions marked with x in the current row of the above base matrix to fill non-zero values, such as 1, and fill 0 in the remaining positions.

[0110] When all rows of the base matrix to be designed have been processed as above, a base matrix with randomly configured systematic bits is obtained. This base matrix can be called an intermediate base matrix. According to the code rate of this base matrix (such as 1 / 6, 1 / 4, or 1 / 3), the signal-to-noise ratio (SNR) and the number of iterations (such as pre-set) are selected, and then this intermediate base matrix is calculated using a density evolution tool (such as the PEXIT tool). If the calculation converges, it is considered that a suitable alternative base matrix is found; if the calculation does not converge, the currently obtained intermediate base matrix is abandoned, and all parameters of the base matrix to be designed are reset. For example, reset as Figure 6A to Figure 6CFor the systematic bits corresponding to the cyclic value x in the base matrix in , reset Ndc and Ndc1, and start processing from the first row of the base matrix to be designed. For example, process each row in sequence to obtain a new intermediate base matrix with systematically re-randomized bits. For this new base matrix, still use the density evolution tool to determine whether it converges during the calculation. Through the above process, multiple suitable alternative base matrices can be obtained for the same code rate.

[0111] Specifically referring to Figure 8 the example shown in , in step 860, determine the row weight dp of the parity bit part in the current row (i.e., the row pointed to by rowindex); in step 870, first determine whether Ndc < N holds. If it does not hold (N), then set the row weight d of the current row to dc - 1, i.e., d = dc - 1. Otherwise (Y), continue to determine whether Ndc1 < M holds. If it does not hold (N), then set the row weight d of the current row to dc, i.e., d = dc. Otherwise (Y), randomly select a value from dc and dc - 1 to assign to d. If the selected value is dc, then increment Ndc by 1. If the selected value is dc - 1, then increment Ndc1 by 1; in step 880, randomly select d - dp different values from the set {0, 1, …, Ns - 1} to assign to the d - dp positions of the systematic bits in the current row of the base matrix B; in step 890, increment the parameter rowindex by 1, and then determine whether rowindex is less than Nrow. If it is, it means that not all rows of the base matrix have been processed, so return to step 860 to process the row pointed to by the incremented rowindex. Otherwise, all rows of the base matrix have been processed. Use the PEXIT tool to calculate the base matrix. If it converges, the base matrix search is complete. If it does not converge, return to step 850 to start a new base matrix search.

[0112] At least one embodiment of the present disclosure further provides a method for constructing a permutation matrix for a QC - LDPC code, as Fig. 9 shown, the method includes:

[0113] Step 910, obtaining a base matrix for the permutation matrix;

[0114] Step 920, lifting the base matrix to obtain a permutation matrix.

[0115] In the above method, the base matrix in step 910 is not limited to obtaining the base matrix according to the above - mentioned embodiments such as Figure 7 shown, and can also be a base matrix obtained by other means. This base matrix is lifted in step 920 to obtain the required permutation matrix.

[0116] For example, step 920 includes: obtaining a prototype graph of the base matrix, obtaining each macro ring in the prototype graph, and for each macro ring in the prototype graph, determining the size of the short ring corresponding to the macro ring in the Tanner graph of the check matrix corresponding to the permutation matrix by the equivalent cycle value ECS of the macro ring, and determining whether it is necessary to set at least one cycle value in the macro ring according to the size of the short ring. The permutation matrix obtained in step 920 can be used to obtain the check matrix of the QC-LDPC code.

[0117] The method for constructing a permutation matrix for a QC-LDPC code according to an embodiment of the present disclosure can conveniently and quickly obtain an alternative permutation matrix, and is helpful for judging the performance of the permutation matrix.

[0118] In the embodiments of the present disclosure, a "macro ring" refers to a ring that appears in the original model graph, and a "short ring" refers to a ring that appears in the corresponding check matrix. As described above, for a macro ring in the original model graph, there is at least one short ring in the corresponding check matrix.

[0119] In at least one embodiment of the present disclosure, the above step 920 may further include: making the ECS of all macro rings in the original model graph meet the requirements of the Tanner graph of the check matrix for the minimum short ring and the requirements for the external information degree of freedom.

[0120] The lifting of the base matrix is ​​to determine the cyclic value of the position of 1 in the base matrix, and the position of 0 in the base matrix is ​​assigned to -1 (this represents a full 0 submatrix). The lifting process includes the process of interleaving and permuting the original model graph to generate the Tanner graph of the corresponding check matrix (i.e., the real Tanner graph). The ring of the Tanner graph has a relatively large impact on the performance of the LDPC code. The information transmission decoding algorithm of the LDPC code assumes that the variable nodes are independent of each other, but the existence of short rings in the Tanner graph of the corresponding check matrix will inevitably destroy the independence assumption, which reduces the decoding performance. Generally, the longer the length of the shortest ring in the Tanner graph of the corresponding check matrix, the closer the decoding performance is to the optimal algorithm. For example, in the embodiment of the present disclosure, the length of the shortest ring can be selected to be 6 or greater, that is, the minimum ring threshold is 6 or greater. For the Tanner graph of the check matrix, the greater the external information freedom, the better the performance of the corresponding LDPC code, especially the steeper the bit error rate curve, so after judging that a ring meets the length constraint, it is also necessary to judge whether the external information freedom is greater than a certain value.

[0121] The inventors discovered the quantitative relationship between the rings on the original model graph and the rings on the Tanner graph of the corresponding check matrix in their research. Based on this quantitative relationship, the information of the rings on the Tanner graph of the corresponding check matrix can be obtained by searching the basis matrix.

[0122] In at least one embodiment of the present disclosure, step 920 further includes: obtaining an equivalent cycle value (ECS) of the macro ring, wherein it is assumed that a macro ring of size 2*L on the original model graph is composed of cycle values ​​{P(i0,j0),P(i0,j1),P(i1,j1),P(i1,j2),…,P(i (L-1) ,j L )}, j L =j0, L is a positive integer, then the equivalent cycle value (ECS) is determined by the following formula:

[0123]

[0124] So, the following conclusions are drawn:

[0125] If the greatest common divisor of the ECS of a macroring in the original model graph and the lifting factor Z is q, then the size of the short ring of the Tanner graph of the check matrix corresponding to the macroring in the original model graph is 2*L*Z / q, and the number of short rings of size 2*L*Z / q generated in the Tanner graph of the corresponding check matrix corresponding to the macroring in the original model graph is q.

[0126] In an example, assuming Z = 8, the permutation matrix is ​​P, so the original model graph corresponding to P has a macro ring of size 4 (2*L, L = 2),

[0127]

[0128] ECS=-3+5-2+1=1, then the greatest common divisor of ECS and Z is q=1, then the size of the short ring of the Tanner graph of the check matrix corresponding to the original model image is 2*2*8 / 1=32, and the number of short rings of size 32 in the Tanner graph of the corresponding check matrix is ​​1. Fig.10 As shown, we can use the permutation matrix to draw a graph to illustrate that there is only one short cycle of 32 in the Tanner graph. The numbers in the figure are the cycle values, and the black dots in the figure represent the cyclic unit matrix corresponding to the cycle values. Starting from H(6,1), it connects adjacent nodes in sequence and finally returns to H(6,1), indicating that there is only one short cycle.

[0129] In another example, assuming Z = 8, the permutation matrix is ​​P, so there is a macro ring of size 4 (2*L, L = 2) on the original model graph corresponding to P.

[0130]

[0131] ECS=-3+6-2+1=2, then the greatest common divisor of ECS and Z is q=2, then the size of the short ring of the Tanner graph of the check matrix corresponding to the original model image is 2*2*8 / 2=16, and the number of short rings of size 16 in the Tanner graph is 2. Fig.11 As shown, it can be seen that there are two short rings of size 16.

[0132] In at least one embodiment of the present disclosure, the base matrix is ​​promoted by recursively calling a tree search method. In this embodiment, each variable node in the original model graph of the base matrix is ​​used as a root node to expand into a tree, and the tree is searched to check whether there is a macro ring corresponding to the tree.

[0133] Fig.12 A tree with the variable node of the base matrix as the root node is shown for tree search. Each variable node of the base matrix will be expanded into a tree, and there may be one or more macro rings on the tree, such as Fig.12 As shown, the dotted line portion indicates a macro ring formed. For each macro ring, according to the relationship between the equivalent cycle value ECS and the short ring described above, each cycle value in the macro ring is appropriately allocated to meet the minimum cycle threshold on the Tanner graph of the check matrix.

[0134] In at least one embodiment of the present disclosure, in the tree search, a recursive call method is adopted, and the entire search is divided into two types of node processing: variable node processing function and check node processing function. Initially, the variable node processing function is called from the root node to start processing, because the neighbor node of the variable node in the tree is a check node, and the check node processing function is continued to be called in the variable node processing function to process the neighbor node of this variable node, and the neighbor node of the check node is another variable node, so the variable node processing function is continued to be called in the check node processing function to process the neighbor node of this check node. This process is repeated until all macro rings originating from the root node are found, and a loop value is assigned to each macro ring to form a permutation matrix P, and the ECS of all macro rings meets the minimum ring requirement and the external information freedom requirement on the Tanner graph.

[0135] For example, in at least one example, Fig.13 The schematic diagram shown in FIG. 1 expands a tree with each variable node in the original model graph of the base matrix as the root node, and performs a tree search on the tree to check whether there is a macro ring corresponding to the tree, including:

[0136] Step 1310, establishing variable node information and check node information of the original model graph of the base matrix according to the base matrix;

[0137] Step 1320, based on the variable node information and the check node information, establish a transfer information combination for transfer between nodes during tree search;

[0138] Step 1330, set the initial value of the transfer information combination, and recursively call the tree to perform a tree search to check whether there is a macro ring corresponding to the tree.

[0139] For example, the variable node information and the check node information each include a node index, the number of neighbor nodes, and an index array of the neighbor nodes.

[0140] For example, the transfer information combination includes a root node index, a parent node index, a current search depth, and a ring node index, where the ring node index is used to record the node indexes of all nodes that form a ring. For another example, the transfer information combination may also include a minimum ring threshold of a Tanner graph of a check matrix and a minimum threshold of the external information degree of freedom of a Tanner graph of a check matrix.

[0141] For example, during the tree search, for each currently searched variable node in the tree: if the current search depth has satisfied the minimum ring threshold of the Tanner graph of the check matrix, the tree search is stopped and a success flag is returned; if the current search depth has not reached the minimum ring threshold, but the first macro ring has been found in the tree search, the equivalent cycle value ECS of the first macro ring is used to check or allocate the various cycle values ​​​​composing the first macro ring, so that the short rings on the Tanner graph of the check matrix satisfy greater than or equal to the minimum ring threshold; or, if the current search depth has not reached the minimum ring threshold and any macro ring is found in the tree search, the tree search is continued.

[0142] For example, during the tree search process, for each currently searched check node in the tree: if the current search depth has satisfied the minimum ring threshold of the Tanner graph of the check matrix, the tree search is stopped and a success flag is returned; if the current search depth has not reached the minimum ring threshold, but the second macro ring has been found in the tree search, the equivalent cycle value ECS of the second macro ring is used to check or allocate the various cycle values ​​​​composing the second macro ring, so that the short rings on the Tanner graph of the check matrix satisfy greater than or equal to the minimum ring threshold; or if the current search depth has not reached the minimum ring threshold, and any macro ring is found in the tree search, the tree search continues.

[0143] For example, during the tree search, each currently searched variable node in the tree is checked to see if a deadlock occurs. If a deadlock occurs, the tree search is stopped.

[0144] The equivalent cycle value ECS of the first macro ring or the second macro ring is used to check or allocate the various cycle values ​​constituting the first macro ring or the second macro ring accordingly, including: if a cycle value constituting the first macro ring or the second macro ring has not been allocated, then randomly select a value in [0, Z-1], if the ECS of the first macro ring or the second macro ring meets the minimum ring threshold, then stop the tree search and return a success mark; or, if all the cycle values ​​constituting the first macro ring or the second macro ring have been allocated, but the ECS of the first macro ring does not meet the minimum ring threshold, then select a modifiable cycle value in the first macro ring or the second macro ring, add 1 and modulo Z to obtain a new cycle value, and then start a new round of search from the root node, where Z is a boost factor.

[0145] The exemplary method of the embodiment of the present disclosure is described below with reference to specific examples of the above-mentioned code rates of 1 / 6, 1 / 4 and 1 / 3.

[0146] Get the base matrix and its original model graph. As mentioned above, when the code rate is 1 / 6, 1 / 4 and 1 / 3, the size of the base matrix is ​​20*24, 18*24 and 16*24 respectively. Traverse the base matrix and establish variable node information VNode

[24] and check node information CNode[Nrow] for the base matrix, where Nrow is 20, 18 and 16. Here, it is assumed that the base matrix B is m×n dimensional, and the node information NodeInf of each node (hereinafter referred to as "current node") may include the following content:

[0147]

[0148] Among them, nodeID represents the index of the current node. For example, for a variable node, the index value is [0,n-1], and for a check node, the index value is [0,m-1]. size represents the number of neighbor nodes of the current node, that is, the number of nodes connected to a node in the original model graph. index

[24] represents the index array of the neighbor nodes of the current node. As mentioned above, the maximum number of rows and columns of the base matrix is ​​24, so the maximum number of elements in the array is 24.

[0149] In order to facilitate the tree search, the transmission information transmitted between (adjacent) nodes during the tree search is established. The transmission information may include the following contents:

[0150]

[0151] In the original model graph, a macrocycle starts from a variable node, and after searching forward, it returns to this variable node, so the initial root nodes in the tree search process are all variable nodes. Conversely, a tree is expanded with each variable node in the original model graph of the base matrix as the root node, and a tree search is performed on the tree to check whether there is a macrocycle corresponding to the tree. When performing a tree search, each level of node above the root node needs to know the index of the root node so that it knows whether a macrocycle has been formed. Here, origVnID represents the index of the root node.

[0152] Parent represents the parent node of the current node. Since the parent node is in the neighbor node list of this node, the parent node is no longer searched during the search. This makes the search direction unidirectional and avoids deadlock.

[0153] Depth indicates the search depth of the current node in the tree to determine whether the search target has been reached. If the search depth exceeds the minimum ring threshold defined below, no further search is required, saving search resources and reducing search time.

[0154] cycleThresh represents the minimum cycle threshold of the Tanner graph of the target check matrix, that is, the length of the shortest cycle. As mentioned above, the longer the length of the shortest cycle, the closer the decoding performance is to the optimal algorithm. The minimum cycle threshold can be selected according to the required decoding performance to achieve a balance between the decoding performance and the above-mentioned search resources and time. For example, the minimum cycle threshold can be 6 or more.

[0155] emdThresh represents the minimum threshold of external information freedom.

[0156] IDsInCycle is, for example, an array whose length is greater than cycleThresh, and is used to record all node indexes constituting a cycle.

[0157] In another example, cycleThresh and emdThresh can be saved and called as system parameters without being part of the transmitted information. For example, cycleThresh can be selected to be greater than or equal to 6, and emdThresh can be selected to be greater than or equal to 3.

[0158] Before the recursive call of the tree search, first set the initial value of the passed information, for example:

[0159]

[0160] When a tree search is performed with the variable node of the base matrix as the root node, each variable node will be expanded into a tree. For example, see Fig.12In this tree, when searching upward from the root node, the node information at each node can be used to know whether the node is a variable node or a check node, the number of its neighbor nodes and the specific nodes. At the same time, the historical information of the current search can be obtained through the transmission of information. For example, Fig.12 In the search, the root node is adjacent to four check nodes. For example, in the search, the search is started from the neighboring node on the right. The first check node CNx on the right is searched first. The check node has two adjacent variable nodes VNa and VNb. The variable node VNa on the right is further searched first, but the branch ends here, so the search of the branch is ended, and then the search returns to the variable VNb on the left, but the branch ends here, so the search of the branch is ended. At this time, the search for the first check node CNx has been completed, and then further returns to the second check node CNy on the right side of the root node to check in the manner described above.

[0161] The processing of each variable node (hereinafter referred to as "current variable node") is as follows.

[0162] First, determine whether the search depth depth corresponding to the current variable node has met the minimum cycle threshold. If depth>cycleThresh, stop searching the branch leading to the current variable node and return a success flag.

[0163] If the search depth does not reach the minimum cycle threshold, that is, it does not satisfy depth > cycleThresh, but a macro cycle has been found through search (for example, referred to as the "first macro cycle" here), that is, the index of the current variable node is the same as the index origVnID of the root node, then the above-mentioned equivalent cycle value (ECS) is applied to check or assign the cycle values of the nodes constituting this macro cycle to ensure that the short cycles on the Tanner graph of the corresponding parity-check matrix satisfy greater than or equal to cycleThresh. As described above, the nodes of this macro cycle can be obtained through the IDsInCycle array. Next, the cycle values on this macro cycle are assigned (assigned values). If a certain cycle value has not been assigned, a value is randomly selected within [0, Z - 1]. If the ECS of the macro cycle obtained after assigning each cycle value satisfies the condition of the minimum cycle of the Tanner graph of the corresponding parity-check matrix, that is, depth * Z / q ≥ cycleThresh, then the search for this branch is stopped and a success flag is returned; if all cycle values have been assigned, but the ECS of the obtained macro cycle does not satisfy the condition of the minimum cycle on the Tanner graph, that is, depth * Z / q < cycleThresh, then the cycle value that can be changed in this macro cycle (the cycle value corresponding to the parity-check bit cannot be changed, while the cycle value corresponding to the systematic bit can be changed) is incremented by 1 and modulo Z to obtain a new cycle value. For example, the cycle value with the deepest search depth depth and that can be changed is incremented by 1 and modulo Z to obtain a new cycle value, and then a new round of search starts from the first variable node. For a macro cycle that satisfies the condition of the minimum cycle of the Tanner graph of the corresponding parity-check matrix, it is checked whether the Tanner graph of the parity-check matrix corresponding to this macro cycle satisfies the condition of the minimum threshold of the extrinsic information degree of freedom, that is, whether the extrinsic information degree of freedom of the Tanner graph of this parity-check matrix is > emdThresh. If it is satisfied, the subsequent operations are continued to retain the corresponding permutation matrix; otherwise, for example, the search is ended, and for example, the next alternative base matrix can be obtained and lifted to obtain a permutation matrix.

[0164] If the search depth does not reach the minimum cycle threshold, that is, depth ≤ cycleThresh, and no macro cycle is found, then the nodeID of the current variable node is added to the IDsInCycle array, that is, IDsInCycle[depth] = nodeID, depth is incremented by 1, and each parity-check node among the neighbor nodes of the current variable node except for the one with ID parent is called for processing. The processing of the parity-check node will be described as follows.

[0165] Since deadlock phenomena may occur during the tree search process, such as Fig.13As shown, when depth=2, variable node 5 (VN5) itself has a macro loop of size 4 (shown by the dotted line in the figure, from node VN5, node CN5, node VN3, node CN4, and then back to node VN5). If this macro loop is not eliminated when the search reaches variable node 5 again at depth=6, continued searching will result in a search deadlock. Therefore, it is necessary to check whether a deadlock has occurred at each variable node. If a deadlock occurs, it is necessary to stop searching for this branch in the tree. Because IDsInCycle has stored all ancestor nodes, it becomes easy to check for deadlocks. It is only necessary to compare the variable node IDs of the ancestor nodes except the first variable node with the current variable node ID to determine whether a deadlock exists.

[0166] The processing of each check node (hereinafter referred to as "current check node") is as follows.

[0167] First, determine whether the search depth depth corresponding to the current check node has satisfied the minimum cycle threshold. If depth>cycleThresh, stop searching the branch leading to the current check node and return a success flag.

[0168] If the search depth does not reach the minimum cycle threshold, i.e., it does not satisfy depth > cycleThresh, but a macro cycle has been found through the search (e.g., referred to as the "second macro cycle" here), that is, the index of the current check node is the same as the index origVnID of the root node, then the above equivalent cycle values (ECS) are applied to check or assign the cycle values of each node constituting this macro cycle to ensure that the short cycles on the Tanner graph of the corresponding parity-check matrix satisfy greater than or equal to cycleThresh. As described above, each node of this macro cycle can be obtained through the IDsInCycle array. Next, the cycle values on this macro cycle are assigned (assigned values). If a certain cycle value has not been assigned, a value is randomly selected within [0, Z - 1]. If the ECS of the macro cycle obtained after assigning each cycle value satisfies the condition of the minimum cycle of the Tanner graph of the corresponding parity-check matrix, that is, depth * Z / q ≥ cycleThresh, then the search for this branch is stopped and a success flag is returned; if all cycle values have been assigned, but the ECS of the obtained macro cycle does not satisfy the condition of the minimum cycle on the Tanner graph, that is, depth * Z / q < cycleThresh, then the cycle value that can be changed in this macro cycle (the cycle value corresponding to the check bit cannot be changed, while the cycle value corresponding to the systematic bit can be changed) is incremented by 1 and modulo Z to obtain a new cycle value. For example, the cycle value with the deepest search depth depth and that can be changed is incremented by 1 and modulo Z to obtain a new cycle value, and then a new round of search starts from the first variable node. Similarly, for a macro cycle that satisfies the condition of the minimum cycle of the Tanner graph of the corresponding parity-check matrix, it is checked whether the Tanner graph corresponding to this macro cycle satisfies the condition of the minimum threshold of the extrinsic information degrees of freedom, that is, whether the extrinsic information degrees of freedom of the Tanner graph of this parity-check matrix > emdThresh. If it is satisfied, the subsequent operations are continued to retain the corresponding permutation matrix; otherwise, for example, the search is ended, and for example, the next alternative base matrix can be obtained and lifted to obtain a permutation matrix.

[0169] If the search depth does not reach the minimum cycle threshold, i.e., depth ≤ cycleThresh, and no macro cycle is found, then the nodeID of the current check node is added to the IDsInCycle array, i.e., IDsInCycle[depth] = nodeID, depth is incremented by 1, and each variable node among the neighbor nodes of the current check node except the one with ID parent is called for processing, and the processing of the check node is as described above.

[0170] Similarly, at each check node, we need to check whether there is a deadlock. If a deadlock occurs, we need to stop searching for this branch in the tree. Because IDsInCycle has stored all ancestor nodes, it is easy to check for deadlocks. We only need to compare the check node IDs of the ancestor nodes except the first check node with the current check node ID to determine whether there is a deadlock.

[0171] After the base matrix is ​​lifted in the manner described above, one or more (alternative) permutation matrices that meet the requirements are obtained.

[0172] In at least one embodiment of the present disclosure, one or more permutation matrices are provided, wherein for a permutation matrix of a 1 / 6 code rate, a permutation matrix of a 1944 code length is as follows:

[0173]

[0174] The permutation matrix of 1296 code length is as follows:

[0175]

[0176] Alternatively, the permutation matrix for a 648-code length is as follows:

[0177]

[0178] Fig.14 The performance corresponding to the permutation matrices of the above three code lengths at a code rate of 1 / 6 is shown. As shown in the figure, the QC-LDPC codes of these three code lengths have excellent performance. For example, the encoder and decoder of the LDPC code at a code rate of 5 / 6 can be multiplexed, with lower development cost.

[0179] For the permutation matrix of 1 / 4 code rate, the permutation matrix of 1944 code length is as follows:

[0180]

[0181] The permutation matrix of 1296 code length is as follows:

[0182]

[0183] Alternatively, the permutation matrix for a 648-code length is as follows:

[0184] Fig.15 The performance of the permutation matrix corresponding to the above three code lengths of 1 / 4 code rate is shown. As shown in the figure, the QC-LDPC codes of these three code lengths have excellent performance, for example, the encoder and decoder of the LDPC code of 3 / 4 code rate can be reused, with low development cost

[0185] For the permutation matrix of 1 / 3 code rate, the permutation matrix of 1944 code length is as follows:

[0186]

[0187] The permutation matrix of 1296 code length is as follows:

[0188]

[0189] Alternatively, the permutation matrix for a 648-code length is as follows:

[0190]

[0191] Fig.16 The performance of the permutation matrix corresponding to the above three code lengths of 1 / 3 code rate is shown. As shown in the figure, the QC-LDPC codes of these three code lengths have excellent performance, for example, the encoder and decoder of the LDPC code of 2 / 3 code rate can be reused, with low development cost

[0192] At least one embodiment of the present disclosure provides a channel coding method, the method comprising: using a generator matrix or a check matrix of a QC-LDPC code to perform channel coding or channel decoding on a code stream, wherein the code rate of the generator matrix or the check matrix is ​​1 / 6, 1 / 4 or 1 / 3. Figure 1 As shown, the code stream obtained by source coding is channel coded to obtain a code stream to be further modulated, or the code stream obtained by demodulation is channel decoded to obtain a code stream to be further source decoded. For example, these code streams include object data and / or control signaling. That is, at least one embodiment of the present disclosure correspondingly provides a channel coding method; at least one embodiment of the present disclosure correspondingly also provides a channel decoding method. For example, the method can be used in a wireless communication system, which may include transceivers that communicate with each other, and these transceivers include, for example, base stations, UEs, etc. (for example, for mobile communication systems), or these transceivers include access devices (such as wireless routers) and clients (such as mobile phones, computers, etc.), and these transceivers can perform the above-mentioned channel coding method and / or channel decoding method. For example, the method uses the check matrix of the QC-LDPC code obtained by the method of constructing the check matrix as described in any of the above embodiments to channel code or channel decode the code stream.

[0193] At least one embodiment of the present disclosure further provides a communication method, which includes using the above-mentioned channel coding method to perform channel coding or channel decoding.

[0194] At least one embodiment of the present disclosure further provides a processing device for channel coding, the device comprising: a receiving unit and a processing unit. The receiving unit is configured to receive a code stream; the processing unit is configured to use a generator matrix or a check matrix of a QC-LDPC code to perform channel coding or channel decoding on the code stream, wherein the code rate of the generator matrix or the check matrix is ​​1 / 6, 1 / 4 or 1 / 3. The receiving unit and the processing unit can be implemented, for example, by software, hardware, firmware or any combination of these methods, for example, by analog / digital circuits. Reference Figure 1 As shown, the code stream obtained by source coding is channel-coded to obtain a code stream to be further modulated, or the code stream obtained by demodulation is channel-decoded to obtain a code stream to be further source-decoded; for example, these code streams include object data and / or control signaling. That is, at least one embodiment of the present disclosure correspondingly provides a channel coding device; at least one embodiment of the present disclosure correspondingly also provides a channel decoding device. For example, the processing device for channel coding and decoding can be used in a wireless communication system, and the wireless communication system can include transceiver devices that communicate with each other, and these transceiver devices include, for example, base stations, UEs, etc. (for example, for mobile communication systems), or these transceiver devices include access devices (such as wireless routers) and clients (such as mobile phones, computers, etc.), and these transceiver devices can execute the above-mentioned channel coding device and / or channel decoding device.

[0195] At least one embodiment of the present disclosure also provides a communication device, which includes the above-mentioned channel coding device to perform channel coding or channel decoding; as needed, the communication device may further include a source coding device or a source decoding device, such as a radio frequency device, etc.

[0196] For example, the channel coding method and device can be used in, for example, 5G NR, WiFi, DVB, and optical communication systems, and the embodiments of the present disclosure are not limited to this.

[0197] For example, the number of columns corresponding to the systematic bits in the permutation matrix corresponding to the generator matrix or the check matrix is ​​Ns, and the number of rows in the permutation matrix is ​​Nrow.

[0198] For 1 / 6 code rate, Ns=4, Nrow=20;

[0199] For 1 / 4 code rate, Ns=6, Nrow=18;

[0200] For 1 / 3 code rate, Ns=8, Nrow=16.

[0201] For example, the total weight of the permutation matrix ranges from 79 to 88;

[0202] For 1 / 6 code rate, the row weight of each row in the basis matrix = 5 or 4;

[0203] For 1 / 4 code rate, the row weight of each row in the basis matrix = 5;

[0204] For 1 / 3 code rate, the row weight of each row in the basis matrix is ​​6 or 5.

[0205] Furthermore, the exemplary permutation matrix described above may be used.

[0206] At least one embodiment of the present disclosure further provides a processing device for executing the above-mentioned base matrix construction method, permutation matrix construction method or encoding and decoding method, for example Fig.17 A schematic diagram of a processing device provided according to at least one embodiment of the present disclosure is shown.

[0207] like Fig.17 As shown, the processing device 600 of the instruction pipeline includes a processing unit 610 and a memory 620, and one or more computer program modules 621 are stored in the memory 620, each of which includes computer executable instructions; when the computer program module 621 is executed by the processing unit 610, it is used to execute the base matrix construction method, permutation matrix construction method or encoding and decoding method of any of the above-mentioned embodiments, and the base matrix construction method, permutation matrix construction method or encoding and decoding method of any of the above-mentioned embodiments is realized.

[0208] At least one embodiment of the present disclosure provides a non-transitory readable storage medium, on which computer instructions are stored. When the computer instructions are executed by a processor, they are used to execute the base matrix construction method, permutation matrix construction method or encoding and decoding method of any of the above-mentioned embodiments, and the base matrix construction method, permutation matrix construction method or encoding and decoding method of any of the above-mentioned embodiments is implemented.

[0209] For example, the non-transient readable storage medium is implemented as a memory, such as a volatile memory and / or a non-volatile memory. In the above embodiment, the memory may be a volatile memory, such as a random access memory (RAM) and / or a cache, etc. Non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the memory.

[0210] At least one embodiment of the present disclosure provides an electronic device, which includes a processing device for executing the above-mentioned base matrix construction method, permutation matrix construction method or encoding and decoding method as in any of the above embodiments, and the base matrix construction method, permutation matrix construction method or encoding and decoding method of any of the above embodiments is implemented.

[0211] For example, in at least one example, the electronic device is a processor. For example, the processor may be a single-core processor or a multi-core processor, and the processor core includes the processing device of the above-mentioned instruction pipeline; for example, the processor may be a scalar processor or a superscalar processor, etc., and the embodiments of the present disclosure are not limited to this.

[0212] Fig.18 A schematic block diagram of an electronic device 700 provided for at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as wireless communication base stations, wireless access devices (e.g., access point devices), wireless routers, mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (e.g., vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.18 The electronic device 700 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0213] For example, Fig.18 As shown, in some examples, the electronic device 700 includes a processor (e.g., a central processing unit) 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 708 into a random access memory (RAM) 703, for executing the base matrix construction method, permutation matrix construction method, or encoding and decoding method of any of the above-mentioned embodiments, etc., to implement the base matrix construction method, permutation matrix construction method, or encoding and decoding method of any of the above-mentioned embodiments. In RAM 703, various programs and data required for the operation of the computer system are also stored. The processor 701, ROM 702, and RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0214] For example, the following components may be connected to the I / O interface 705: an input device 706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 708 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 709 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 709 may allow the electronic device 700 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. Removable media 711, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 710 as needed, so that the computer programs read therefrom are installed into the storage device 708 as needed. Although Fig.18 The electronic device 700 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0215] For example, the electronic device 700 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 709 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0216] For example, the electronic device 700 can be any device such as a wireless communication base station, a wireless access device (such as an access point device), a wireless router, a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0217] There are a few points to note about this disclosure:

[0218] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0219] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0220] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A channel coding method, comprising: The code stream is channel encoded or channel decoded using the generator matrix or check matrix of the QC-LDPC code, where: The code rate of the generator matrix or the check matrix is ​​1 / 6, 1 / 4 or 1 / 3; Among them, the permutation matrix for the 1 / 6 code rate includes: Permutation matrix of 1944 code length: Permutation matrix of 1296 code length: Or, a permutation matrix with a length of 648 codes: The permutation matrix for the 1 / 4 code rate includes: the permutation matrix of the 1944 code length: Permutation matrix of 1296 code length: Or, a permutation matrix with a length of 648 codes: The permutation matrix for the 1 / 3 code rate includes: a permutation matrix of 1944 code length: Permutation matrix of 1296 code length: Or, a permutation matrix with a length of 648 codes:

2. The channel coding method according to claim 1, wherein: The number of columns corresponding to the systematic bits in the permutation matrix corresponding to the generator matrix or the check matrix is ​​Ns, and the number of rows of the permutation matrix is ​​Nrow. For 1 / 6 code rate, Ns=4, Nrow=20; For 1 / 4 code rate, Ns=6, Nrow=18; For 1 / 3 code rate, Ns=8, Nrow=16.

3. The channel coding method according to claim 2, wherein: The total weight of the substitution matrix ranges from 79 to 88; For 1 / 6 code rate, the row weight of each row in the basis matrix = 5 or 4; For 1 / 4 code rate, the row weight of each row in the basis matrix = 5; For 1 / 3 code rate, the row weight of each row in the basis matrix is ​​6 or 5.

4. A processing device for channel coding and decoding, comprising: A receiving unit, configured to receive a code stream, A processing unit is configured to perform channel encoding or channel decoding on a code stream using a generator matrix or a check matrix of a QC-LDPC code, wherein: The code rate of the generator matrix or the check matrix is ​​1 / 6, 1 / 4 or 1 / 3; Among them, the permutation matrix for the 1 / 6 code rate includes: Permutation matrix of 1944 code length: Permutation matrix of 1296 code length: Or, a permutation matrix with a length of 648 codes: The permutation matrix for the 1 / 4 code rate includes: the permutation matrix of the 1944 code length: Permutation matrix of 1296 code length: Or, a permutation matrix with a length of 648 codes: The permutation matrix for the 1 / 3 code rate includes: the permutation matrix of the 1944 code length: Permutation matrix of 1296 code length: Or, a permutation matrix with a length of 648 codes:

5. The channel coding device according to claim 4, wherein: The total weight of the substitution matrix ranges from 79 to 88; For 1 / 6 code rate, the row weight of each row in the basis matrix = 5 or 4; For 1 / 4 code rate, the row weight of each row in the basis matrix = 5; For 1 / 3 code rate, the row weight of each row in the basis matrix is ​​6 or 5.

6. A processing device for channel coding and decoding, comprising: Processing unit, a memory having one or more computer program modules stored thereon; Wherein, when the one or more computer program modules are configured to be executed by the processing unit, the channel coding method according to any one of claims 1 to 3 is implemented.

7. A non-transitory readable storage medium, wherein: The non-transitory readable storage medium stores computer instructions, wherein when the computer instructions are executed by a processor, the channel coding method according to any one of claims 1 to 3 is implemented.

8. A communication method, comprising processing using the channel coding method according to any one of claims 1 to 3.

9. A communication device, comprising the processing device for channel coding according to any one of claims 4-5.

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