Camera

Abstract

The present disclosure relates to an imaging device comprising: a plurality of pixel circuits each of which generates a pixel signal including a pixel voltage corresponding to the amount of light received, and performs AD conversion by comparing the pixel signal with a reference signal; and a reference signal generating unit comprising a signal generating circuit and a voltage follower circuit, the signal generating circuit generating a voltage signal having a ramp waveform, the voltage follower circuit performing a voltage follower operation based on the voltage signal to generate the reference signal, and providing the reference signal to the plurality of pixel circuits.

Description

Technical Field

[0001] The present disclosure relates to an imaging device for capturing an image of a subject. Background Art

[0002] Typically, in an imaging device, pixels, each including a photodiode, are arranged in a matrix, and each pixel generates a pixel voltage corresponding to the amount of light received. For example, an analog-to-digital converter (ADC) circuit then converts the pixel voltage (analog signal) into a digital signal. For example, Patent Document 1 discloses an imaging device that performs AD conversion by comparing a signal including a pixel voltage with a reference signal having a ramp waveform.

[0003] Citation list

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2005-278135 Summary of the Invention

[0006] Incidentally, an image pickup apparatus is expected to provide a captured image with high image quality, and is expected to have further improved image quality.

[0007] It is desirable to provide an image pickup device capable of improving the image quality of captured images.

[0008] According to an embodiment of the present disclosure, an imaging device includes a plurality of pixel circuits and a reference signal generating unit. The plurality of pixel circuits each generate a pixel signal including a pixel voltage corresponding to the amount of light received, and perform AD conversion by comparing the pixel signal with a reference signal. The reference signal generating unit includes a signal generating circuit and a voltage follower circuit. The signal generating circuit generates a voltage signal having a ramp waveform. The voltage follower circuit performs a voltage follower operation based on the voltage signal to generate the reference signal, and provides the reference signal to the plurality of pixel circuits.

[0009] In an imaging device according to an embodiment of the present disclosure, a voltage signal having a ramp waveform is generated in each of the plurality of pixel circuits, and a voltage follower operation is performed based on the voltage signal to generate the reference signal. Then, a pixel signal including a pixel voltage corresponding to the amount of received light is generated in each of the plurality of pixel circuits, and AD conversion is performed by comparing the pixel signal with the reference signal. The generated reference signal is provided to the plurality of pixel circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1is a block diagram illustrating a configuration example of an image pickup apparatus according to an embodiment of the present disclosure.

[0011] Figure 2 yes Figure 1 A schematic diagram of an embodiment of a camera device is shown.

[0012] Figure 3 It shows Figure 1 A circuit diagram showing an example of the configuration of a pixel circuit included in the pixel shown.

[0013] Figure 4 It shows Figure 1 A circuit diagram showing an example of the configuration of a reference signal generating section is shown.

[0014] Figure 5 It shows Figure 4 A block diagram of an example configuration of an amplifier is shown.

[0015] Figure 6 It shows Figure 4 A circuit diagram showing an example of the configuration of an amplifier is shown.

[0016] Figure 7 It shows Figure 1 The timing waveform diagram of the operation example of the imaging device shown is shown.

[0017] Figure 8 It shows Figure 6 An explanatory diagram of an example of the operation of the amplifier shown.

[0018] Figure 9 It shows Figure 4 An explanatory diagram of a characteristic example of a voltage follower circuit shown.

[0019] Figure 10 is a circuit diagram showing a configuration example of a reference signal generating section according to a comparative example.

[0020] Figure 11 is a circuit diagram showing a configuration example of an amplifier according to a modification.

[0021] Figure 12 is a circuit diagram showing a configuration example of an amplifier according to another modification.

[0022] Figure 13 is a circuit diagram showing a configuration example of an amplifier according to another modification.

[0023] Figure 14 It is an explanatory diagram showing an example of use of the imaging device.

[0024] Figure 15 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0025] Figure 16 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0026] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0027] 1. Example

[0028] 2. Example of using the camera device

[0029] 3. Application examples for mobile objects

[0030] <1. Example>

[0031] [Construction example]

[0032] Figure 1 The imaging device 1 includes a pixel array 11 , a reference signal generating section 12 , a pixel driving unit 13 , a vertical driving unit 14 , a signal processing section 15 , and a timing generating section 16 .

[0033] The pixel array 11 includes a plurality of pixels P arranged in a matrix. Each pixel P includes a photodiode PD and is configured to generate a pixel signal SIG including a pixel voltage Vpix corresponding to the amount of received light and perform AD conversion based on the pixel signal SIG. The pixels P are provided on two semiconductor substrates.

[0034] Figure 2 An embodiment of an imaging device 1 is shown. In this example, the imaging device 1 is formed on semiconductor substrates 101 and 102. The semiconductor substrate 101 is provided on the imaging surface side of the imaging device 1, and the semiconductor substrate 102 is provided on the side opposite to the imaging surface side of the imaging device 1. The semiconductor substrates 101 and 102 overlap each other. The wiring of the semiconductor substrate 101 and the wiring of the semiconductor substrate 102 are connected to each other by wiring 103. For example, a metal bond such as Cu-Cu can be used for the wiring 103. Pixels P are provided on these two semiconductor substrates 101 and 102.

[0035] Figure 3 1 shows a configuration example of a pixel P. The pixel P includes a pixel circuit 20. The pixel circuit 20 includes a light receiving circuit 21, a comparison circuit 22, and a latch 23.

[0036] The light receiving circuit 21 is configured to generate a pixel voltage Vpix corresponding to the amount of light received. The light receiving circuit 21 is provided on the semiconductor substrate 101. The light receiving circuit 21 includes a photodiode PD, a discharge transistor MN1, a transfer transistor MN2, a floating diffusion FD, and a reset transistor MN3. The discharge transistor MN1, the transfer transistor MN2, and the reset transistor MN3 are N-type MOS (Metal Oxide Semiconductor) transistors.

[0037] The photodiode PD is a photoelectric conversion element that generates and accumulates charges in an amount corresponding to the amount of received light. The photodiode PD has a grounded anode and a cathode connected to the source of the discharge transistor MN1 and the source of the transfer transistor MN2.

[0038] The gate of the discharge transistor MN1 is supplied with a charge from the pixel driving unit 13 ( Figure 1 ) is provided with a control signal OFG, the drain is provided with a voltage VOFG, and the source is connected to the cathode of the photodiode PD and the source of the transfer transistor MN2.

[0039] The gate of the transfer transistor MN2 is supplied with a signal from the pixel driving unit 13 ( Figure 1 ) provided by the control signal TX, the source is connected to the cathode of the photodiode PD and the source of the discharge transistor MN1, and the drain is connected to the floating diffusion portion FD, the source of the reset transistor MN3 and the gate of the transistor MN4 (described later) in the comparison circuit 22.

[0040] The floating diffusion FD is configured to accumulate charges transferred from the photodiode PD. The floating diffusion FD includes, for example, a diffusion layer formed on the surface of the semiconductor substrate 101 . Figure 3 The floating diffusion FD is shown by using the symbol of a capacitor.

[0041] The reset transistor MN3 has a gate supplied with a control signal RST, a drain connected to the drain of the transistor MN4 (described later) of the comparison circuit 22, and a source connected to the floating diffusion FD, the drain of the transfer transistor MN2, and the gate of the transistor MN4 (described later) of the comparison circuit 22.

[0042] With this configuration, the light receiving circuit 21 discharges the charge accumulated in the photodiode PD by turning on the discharge transistor MN1 based on the control signal OFG. The discharge transistor MN1 is then turned off to begin the exposure period, and an amount of charge corresponding to the amount of received light is accumulated in the photodiode PD. After the exposure period ends, the light receiving circuit 21 supplies a pixel signal SIG comprising a reset voltage Vreset and a pixel voltage Vpix to the comparison circuit 22. Specifically, as described below, during the P-phase (Pre-charge phase) after the voltage of the floating diffusion FD is reset, the light receiving circuit 21 supplies the voltage of the floating diffusion FD at that time to the comparison circuit 22 as the reset voltage Vreset. Furthermore, during the D-phase (Data phase) after the charge is transferred from the photodiode PD to the floating diffusion FD, the light receiving circuit 21 supplies the voltage of the floating diffusion FD at that time to the comparison circuit 22 as the pixel voltage Vpix.

[0043] Comparison circuit 22 is configured to generate signal CMP by comparing reference signal REF with pixel signal SIG. When the voltage of reference signal REF is higher than the voltage of pixel signal SIG, comparison circuit 22 changes signal CMP to a high level. When the voltage of reference signal REF is lower than the voltage of pixel signal SIG, comparison circuit 22 changes signal CMP to a low level. Comparison circuit 22 includes transistors MN4 to MN6 and transistors MP1 and MP2. Transistors MN4 to MN6 are N-type MOS transistors, while transistors MP1 and MP2 are P-type MOS transistors. Comparison circuit 22 is provided on two semiconductor substrates 101 and 102. Specifically, transistors MN4 to MN6 are provided on semiconductor substrate 101, while transistors MP1 and MP2 are provided on semiconductor substrate 102.

[0044] Transistor MN4 has a gate supplied with pixel signal SIG, a drain connected to the drain of reset transistor MN3 in light receiving circuit 21, and connected to the drain of transistor MP1 and the input terminal of amplifier AMP via wiring 103 between semiconductor substrates 101 and 102. Its source is connected to the source of transistor MN5 and the drain of transistor MN6. Reference signal REF is supplied to the gate of transistor MN5 from reference signal generator 12 via wiring 103 between semiconductor substrates 101 and 102. Its drain is connected to the drain of transistor MP2 and the gates of transistors MP1 and MP2 via wiring 103 between semiconductor substrates 101 and 102, and its source is connected to the source of transistor MN4 and the drain of transistor MN6. As described in detail below, reference signal REF is a signal having a so-called ramp waveform, where the voltage level gradually changes over time during the P-phase period TP and the D-phase period TD. Bias voltage Vb is supplied to the gate of transistor MN6, and its drain is connected to the sources of transistors MN4 and MN5, with its source being grounded. The transistors MN4 and MN5 constitute a differential pair, and the transistor MN6 constitutes a constant current source.

[0045] The gate of transistor MP1 is connected to the gate and drain of transistor MP2 and to the drain of transistor MN5 via wiring 103 between semiconductor substrates 101 and 102. The source is supplied with power supply voltage VDD, and the drain is connected to the input terminal of amplifier AMP. It is also connected to the drain of transistor MN4 and the drain of reset transistor MN3 in light receiving circuit 21 via wiring 103 between semiconductor substrates 101 and 102. The gate of transistor MP2 is connected to the gate of transistor MP1 and the drain of transistor MP2, and to the drain of transistor MN5 via wiring 103 between semiconductor substrates 101 and 102. The source is supplied with power supply voltage VDD, and the drain is connected to the gates of transistors MP1 and MP2, and to the drain of transistor MN5 via wiring 103 between semiconductor substrates 101 and 102. Transistors MP1 and MP2 constitute active loads for transistors MN4 and MN5.

[0046] The input terminal of the amplifier AMP is connected to the drain of the transistor MP1, and is connected to the drain of the transistor MN4 and the drain of the reset transistor MN3 in the light receiving circuit 21 via the wiring 103 between the semiconductor substrates 101 and 102. The output terminal of the amplifier AMP is connected to the latch 23. The comparison circuit 22 outputs the signal CMP from the output terminal of the amplifier AMP.

[0047] The latch 23 is configured to latch the signal CMP supplied from the pixel driving unit 13 ( Figure 1) is provided by the time code CODE. The time code CODE changes with time. For example, the time code CODE can use a Gray code. As described below, the latch 23 latches the time code CODE at the transition moment of the signal CMP in the P-phase period TP, and obtains the time from the start of the P-phase period TP to the occurrence of the signal CMP transition (code value CODE1). In addition, the latch 23 obtains the time from the start of the D-phase period TD to the occurrence of the signal CMP transition (code value CODE2) by latching the time code CODE at the transition moment of the signal CMP in the D-phase period TD. The difference between the two code values ​​(CODE2-CODE1) corresponds to the pixel value corresponding to the amount of light received. Then, the latch 23 provides the two code values ​​CODE1 and CODE2 to the signal processing unit 15 based on the control signal provided from the vertical drive unit 14.

[0048] Therefore, the pixel circuit 20 generates a pixel signal SIG including a pixel voltage Vpix corresponding to the amount of received light, and performs AD conversion based on the pixel signal SIG to generate code values ​​CODE1 and CODE2.

[0049] The reference signal generating section 12 is configured to generate a reference signal REF. The reference signal REF is a signal having a so-called ramp waveform whose voltage level gradually changes over time in the P-phase period TP and the D-phase period TD. The reference signal generating section 12 then supplies the generated reference signal REF to the pixel array 11 ( Figure 1 ) in a plurality of pixel circuits 20. Figure 3 As shown, the reference signal generating section 12 is provided on the semiconductor substrate 102 .

[0050] Pixel driving unit 13 ( Figure 1 ) is configured to control the operation of the plurality of pixel circuits 20 in the pixel array 11. Specifically, the pixel driving unit 13 generates control signals OFG, TX, and RST and supplies these control signals OFG, TX, and RST to the light receiving circuit 21, and also generates a time code CODE and supplies the time code CODE to the latch 23, thereby controlling the operation of the pixel circuit 20. For example, the pixel driving unit 13 is provided on the semiconductor substrate 102.

[0051] The vertical driving unit 14 is configured to supply code values ​​CODE1 and CODE2 generated by each of the plurality of pixel circuits 20 in the pixel array 11 to the signal processing section 15 in a predetermined order. The vertical driving unit 14 is provided on the semiconductor substrate 102, for example.

[0052] The signal processing unit 15 is configured to perform predetermined image processing based on the code values ​​CODE1 and CODE2 generated by each of the plurality of pixel circuits 20, thereby generating an image signal Spic. Examples of the predetermined image processing include processing for generating pixel values ​​based on the two code values ​​CODE1 and CODE2 generated by the pixel circuits 20 using the principle of correlated double sampling (DCS), and black level correction processing for correcting the black level. For example, the signal processing unit 15 is provided on the semiconductor substrate 102.

[0053] The timing generation section 16 is configured to control the operation of the image pickup apparatus 1 by generating various timing signals and supplying the generated various timing signals to the reference signal generation section 12, the pixel drive unit 13, the vertical drive unit 14, and the signal processing section 15. For example, the timing generation section 16 is provided on the semiconductor substrate 102.

[0054] (Reference Signal Generator 12)

[0055] Figure 4 FIG. 1 shows an example of a configuration of the reference signal generating unit 12. Note that, Figure 4 Also shown are a plurality of pixel circuits 20 supplied with a reference signal REF generated by the reference signal generating section 12. The reference signal generating section 12 includes a signal generating circuit 31 and a voltage follower circuit 34.

[0056] Signal generating circuit 31 is configured to generate signal REF0 having a ramp waveform similar to that of reference signal REF. Signal generating circuit 31 includes current source 32 and resistor 33. Current source 32 is a variable current source in which the current to be transmitted is variable. One end of current source 32 is supplied with power supply voltage VDD, and the other end is connected to one end of resistor 33 and the input terminal of voltage follower circuit 34. One end of resistor 33 is connected to the other end of current source 32 and the input terminal of voltage follower circuit 34, and the other end is grounded. With this configuration, signal REF having a ramp waveform is generated by switching the current value of the current transmitted by current source 32.

[0057] The voltage follower circuit 34 is configured to generate a reference signal REF by performing a voltage follower operation based on the signal REF0. The voltage follower circuit 34 includes an amplifier 35. The amplifier 35 has a positive input terminal InP, a negative input terminal InN, and an output terminal OUT. The positive input terminal InP of the amplifier 35 is provided with the signal REF0, and the negative input terminal InN is connected to the output terminal OUT of the amplifier 35. The amplifier 35 outputs the reference signal REF from the output terminal OUT. The voltage follower circuit 34 provides the reference signal REF output from the output terminal OUT of the amplifier 35 to the negative input terminal InN of the amplifier 35. The voltage follower circuit 34 performs a voltage follower operation by performing a negative feedback operation in this manner.

[0058] Therefore, in the reference signal generating section 12, the signal generating circuit 31 generates a signal REF having a ramp waveform, and the voltage follower circuit 34 generates a reference signal REF by performing a voltage follower operation based on the signal REF0. Then, the reference signal generating section 12 supplies the generated reference signal REF to the pixel array 11 ( Figure 1 ) in a plurality of pixel circuits 20.

[0059] Figure 5 : An example of the configuration of the amplifier 35 is shown. The amplifier 35 includes a differential input circuit 91, a bias circuit 92, and an output circuit 93. The differential input circuit 91 is used to output a differential signal corresponding to the voltage difference between the voltage at the positive input terminal InP and the voltage at the negative input terminal InN. The bias circuit 92 is used to set the operating point of the output circuit 93 based on the differential signal provided from the differential input circuit 91. The bias circuit 92 is a circuit using the translinear principle. The output circuit 93 is an output circuit capable of rail-to-rail operation. For example, this amplifier 35 is also called a cross-coupled feedforward class AB amplifier.

[0060] Figure 6 1 shows an example of a specific circuit configuration of the amplifier 35. The amplifier 35 includes a constant current source IS, transistors MP11 to MP22 and MN31 to MN40, resistors R1 and R2, and capacitors C1 and C2. The transistors MP11 to MP22 are P-type MOS transistors, and the transistors MN31 to MN40 are N-type MOS transistors.

[0061] One end of the constant current source IS is connected to the gate and drain of transistor MP11, and to the gates of transistors MP12, MP13, and MP19, and the other end is connected to ground node NVSS. The gate of transistor MP11 is connected to the drain of transistor MP11 and one end of the constant current source IS, and to the gates of transistors MP12, MP13, and MP19. The source of transistor MP11 is connected to power supply node NVDD, and the drain of transistor MP11 is connected to the gate of transistor MP11 and one end of the constant current source IS, and to the gates of transistors MP12, MP13, and MP19. Transistors MP11, MP12, MP13, and MP19 form a current mirror circuit.

[0062] The gate of transistor MP12 is connected to the gate and drain of transistor MP11, one end of constant current source IS, and the gates of transistors MP13 and MP19. Its source is connected to power supply node NVDD, and its drain is connected to the gate and drain of transistor MN31, as well as to the gate of transistor MN39. Transistor MN31 has a gate connected to the drains of transistors MN31 and MP12, and to the gate of transistor MN39. Its drain is connected to the gate of transistor MN31 and the drain of transistor MP12, and to the gate of transistor MN39. Its source is connected to ground node NVSS. Transistors MN31 and MN39 form a current mirror circuit.

[0063] The gate of transistor MP13 is connected to the gate and drain of transistor MP11, one end of constant current source IS, and the gates of transistors MP12 and MP19. Its source is connected to power supply node NVDD, and its drain is connected to the sources of transistors MP14 and MP15. Transistor MP14 has a gate connected to the negative input terminal InN of amplifier 35, a source connected to the source of transistor MP15 and the drain of transistor MP13, and a drain connected to the gate and drain of transistor MN32 and the gate of transistor MN35. Transistor MP15 has a gate connected to the positive input terminal InP of amplifier 35, a source connected to the source of transistor MP14 and the drain of transistor MP13, and a drain connected to the gate and drain of transistor MN33 and the gate of transistor MN34. Transistor MN32 has a gate connected to the drains of transistors MN32 and MP14, and to the gate of transistor MN35. Its drain is connected to the gate of transistor MN32, the drain of transistor MP14, and the gate of transistor MN35. Its source is connected to ground node NVSS. Transistor MN33 has a gate connected to the drains of transistors MN33 and MP15, and to the gate of transistor MN34. Its drain is connected to the gate of transistor MN33, the drain of transistor MP15, and to the gate of transistor MN34. Its source is connected to ground node NVSS. Transistors MP14 and MP15 form a differential pair. Transistors MN32 and MN35 form a current mirror circuit, and transistors MN33 and MN34 form a current mirror circuit.

[0064] Transistors MP13 to MP15, MN32, and MN33 correspond to Figure 5 The differential input circuit 91 is shown.

[0065] Transistor MN34 has a gate connected to the gate and drain of transistor MN33 and to the drain of transistor MP15. Its drain is connected to the gate and drain of transistor MP16 and to the gate of transistor MP17. Its source is connected to ground node NVSS. Transistor MP16 has a gate connected to the drains of transistors MP16 and MN34 and to the gate of transistor MP17. Its source is connected to power supply node NVDD. Its drain is connected to the gate of transistor MP16 and the drain of transistor MN34 and to the gate of transistor MP17. Transistors MP16 and MP17 form a current mirror circuit.

[0066] Transistor MP17 has a gate connected to the gate and drain of transistor MP16 and to the drain of transistor MN34, a source connected to power supply node NVDD, and a drain connected to node N1. Transistor MP18 has a gate connected to the gate and drain of transistor MP21 and to the drain of transistor MN39, a source connected to node N1, and a drain connected to node N2. Transistor MN36 has a gate connected to the gate and drain of transistor MN38 and to the drain of transistor MP19, a drain connected to node N1, and a source connected to node N2. Transistor MN35 has a gate connected to the gate and drain of transistor MN32 and to the drain of transistor MP14, a drain connected to node N2, and a source connected to ground node NVSS.

[0067] Transistor MP19 has a gate connected to the gate and drain of transistor MP11, one end of constant current source IS, and the gates of transistors MP12 and MP13. Its source is connected to power supply node NVDD, and its drain is connected to the gate and drain of transistor MN38, as well as to the gate of transistor MN36. Transistor MN38 has a gate connected to the drain of transistor MN38 and the drain of transistor MP19, as well as to the gate of transistor MN36. Its drain is connected to the gate of transistor MN38 and the drain of transistor MP19, as well as to the gate of transistor MN36. Its source is connected to the gate and drain of transistor MN37. Transistor MN37 has a gate connected to the drain of transistor MN37 and the source of transistor MN38, a drain connected to the gate of transistor MN37 and the source of transistor MN38, and a source connected to ground node NVSS. Transistors MP19, MN38, and MN37 form a bias circuit that generates a bias voltage to be supplied to the gate of transistor MN36.

[0068] The gate of transistor MP20 is connected to the drain of transistor MP20 and the source of transistor MP21. Its source is connected to power supply node NVDD, and its drain is connected to the gate of transistor MP20 and the source of transistor MP21. Transistor MP21 has a gate connected to the drains of transistors MP21 and MN39, and to the gate of transistor MP18. Its source is connected to the gate and drain of transistor MP20, and its drain is connected to the gate of transistor MP21 and the drain of transistor MN39, and to the gate of transistor MP18. Transistor MN39 has a gate connected to the gate and drain of transistor MN31 and to the drain of transistor MP12. Its drain is connected to the gate and drain of transistor MP21 and to the gate of transistor MP18, and its source is connected to ground node NVSS. Transistors MP20, MP21, and MN39 constitute a bias circuit that generates a bias voltage to be supplied to the gate of transistor MP18.

[0069] Transistors MP16 to MP21 and MN34 to MN39 correspond to Figure 5 The bias circuit 92 is shown.

[0070] Transistor MP22 has a gate connected to node N1, a source connected to power supply node NVDD, and a drain connected to output terminal OUT of amplifier 35. Transistor MN40 has a gate connected to node N2, a drain connected to output terminal OUT of amplifier 35, and a source connected to ground node NVSS. Capacitor C1 has one end connected to node N1 and the other end connected to one end of resistor R1. Resistor R1 has one end connected to the other end of capacitor C1 and the other end connected to output terminal OUT. Capacitor C2 has one end connected to node N2 and the other end connected to one end of resistor R2. Resistor R2 has one end connected to the other end of capacitor C2 and the other end connected to output terminal OUT. Capacitors C1 and C2, and resistors R1 and R2, constitute a phase compensation circuit.

[0071] Transistors MP22 and MN40, capacitors C1 and C2, and resistors R1 and R2 correspond to Figure 5 The output circuit 93 is shown.

[0072] With this configuration, in the image pickup device 1 , as described below, the reference signal REF can be stably supplied to the pixel circuits 20 of the plurality of pixels P in the pixel array 11 .

[0073] Here, the pixel circuit 20 corresponds to a specific example of the “pixel circuit” in the present disclosure. The reference signal generating section 12 corresponds to a specific example of the “reference signal generating section” in the present disclosure. The signal generating circuit 31 corresponds to a specific example of the “signal generating circuit” in the present disclosure. The voltage follower circuit 34 corresponds to a specific example of the “voltage follower circuit” in the present disclosure. The pixel signal SIG corresponds to a specific example of the “pixel signal” in the present disclosure. The reference signal REF corresponds to a specific example of the “reference signal” in the present disclosure. The amplifier 35 corresponds to a specific example of the “amplifier” in the present disclosure. The output circuit 93 corresponds to a specific example of the “output circuit” in the present disclosure.

[0074] The power supply node NVDD corresponds to a specific example of a "first power supply node" in the present disclosure. The ground node NVSS corresponds to a specific example of a "second power supply node" in the present disclosure. The transistor MP22 corresponds to a specific example of a "first transistor" in the present disclosure. The transistor MN40 corresponds to a specific example of a "second transistor" in the present disclosure. The pair of transistors MP14 and MP15 corresponds to a specific example of a "first differential transistor pair" in the present disclosure. The transistor MP17 corresponds to a specific example of a "third transistor" in the present disclosure. The transistor MN35 corresponds to a specific example of a "fourth transistor" in the present disclosure. The transistor MP18 corresponds to a specific example of a "fifth transistor" in the present disclosure. The transistor MN36 corresponds to a specific example of a "sixth transistor" in the present disclosure. The node N1 corresponds to a specific example of a "first node" in the present disclosure. The node N2 corresponds to a specific example of a "second node" in the present disclosure. The transistor MN33 corresponds to a specific example of a "seventh transistor" in the present disclosure. The transistor MN32 corresponds to a specific example of an "eighth transistor" in the present disclosure. The transistor MN34 corresponds to a specific example of a "ninth transistor" in the present disclosure. The transistor MP16 corresponds to a specific example of a “tenth transistor” in the present disclosure.

[0075] [Operation and function]

[0076] Next, the operation and effects of the image pickup apparatus 1 according to the present embodiment will be described.

[0077] (Overview of overall operation)

[0078] First, refer to Figure 1 and Figure 3 An overview of the overall operation of the image pickup device 1 is described. The reference signal generating section 12 generates a reference signal REF. The plurality of pixel circuits 20 in the pixel array 11 each generate a pixel signal SIG including a pixel voltage Vpix corresponding to the amount of received light, and performs AD conversion based on the pixel signal SIG to generate code values ​​CODE1 and CODE2. The pixel driving unit 13 controls the operation of the plurality of pixel circuits 20 in the pixel array 11. The vertical driving unit 14 supplies the code values ​​CODE1 and CODE2 respectively generated by the plurality of pixel circuits 20 in the pixel array 11 to the signal processing section 15 in a predetermined order. The signal processing section 15 performs predetermined image processing based on the code values ​​CODE1 and CODE2 respectively generated by the plurality of pixel circuits 20 to generate an image signal Spic. The timing generating section 16 generates various timing signals and supplies the generated various timing signals to the reference signal generating section 12, the pixel driving unit 13, the vertical driving unit 14, and the signal processing section 15 to control the operation of the image pickup device 1.

[0079] (Detailed operation)

[0080] In the plurality of pixel circuits 20 ( Figure 3 ), the discharge transistor MN1 is turned on based on the control signal OFG to discharge the charge accumulated in the photodiode PD. The discharge transistor MN1 is then turned off to begin the exposure period, and an amount of charge corresponding to the amount of received light is accumulated in the photodiode PD. After the exposure period ends, the pixel circuit 20 performs A / D conversion based on the pixel signal SIG, which includes the reset voltage Vreset and the pixel voltage Vpix. This A / D conversion is described in detail below.

[0081] Figure 7 1 shows an example of AD conversion operation in the pixel circuit 20 of interest. (A) shows the waveform of the control signal RST, (B) shows the waveform of the control signal TX, (C) shows the waveform of the reference signal REF, (D) shows the waveform of the pixel signal SIG, and (E) shows the waveform of the signal CMP.

[0082] First, at time t11, the reference signal generating unit 12 changes the voltage of the reference signal REF to the reset voltage Vreset ( Figure 7 (C)). In addition, at time t11, the pixel driving unit 13 changes the control signal RST from the low level to the high level ( Figure 7 (A)). Therefore, in the pixel circuit 20, the reset transistor MN3 is turned on, the floating diffusion FD is reset, and the voltage of the pixel signal SIG becomes the reset voltage Vreset ( Figure 7 Then, after a predetermined time has passed from time t11, the pixel driving unit 13 changes the control signal RST from the high level to the low level ( Figure 7 (A)). Therefore, the reset transistor MN3 is turned off.

[0083] Next, at time t12, the reference signal generating section 12 changes the voltage of the reference signal REF from the reset voltage Vreset to the voltage V1 ( Figure 7 (C)). This makes the voltage of the reference signal REF higher than the voltage of the pixel signal SIG; therefore, the comparison circuit 22 changes the signal CMP to a high level ( Figure 7 (E)).

[0084] Next, in the period from time t13 to time t15 (P-phase period TP), the pixel circuit 20 performs AD conversion based on the voltage of the pixel signal SIG (reset voltage Vreset). Specifically, at time t13, the reference signal generating section 12 starts to reduce the voltage of the reference signal REF from the voltage V1 by a predetermined degree of change ( Figure 7(C)). In addition, at time t13, the pixel driving unit 13 starts the increment operation of the time code CODE.

[0085] At time t14, the voltage of the reference signal REF is lower than the voltage of the pixel signal SIG (reset voltage Vreset) ( Figure 7 (C) and (D)). Therefore, the comparison circuit 22 changes the signal CMP from high level to low level ( Figure 7 (E)). Latch 23 latches time code CODE based on the transition of signal CMP. The code value of time code CODE latched by latch 23 at time t14 is CODE1. Code value CODE1 is a code value corresponding to the length of time from time t13 to time t14 and a code value corresponding to reset voltage Vreset.

[0086] At time t15, the reference signal generating section 12 changes the voltage of the reference signal REF to the voltage V2 ( Figure 7 Then, in the period from time t15 to time t16, the vertical drive unit 14 supplies the code value CODE1 generated by the pixel circuit 20 to the signal processing section 15.

[0087] Next, at time t16, the reference signal generating section 12 changes the voltage of the reference signal REF from the voltage V2 to the voltage V1 ( Figure 7 (C)). This makes the voltage of the reference signal REF higher than the voltage of the pixel signal SIG; therefore, the comparison circuit 22 changes the signal CMP from a low level to a high level ( Figure 7 (E)).

[0088] Next, at time t17, the pixel driving unit 13 changes the control signal TX from the low level to the high level ( Figure 7 (B)). Therefore, in the pixel circuit 20, the transfer transistor MN2 is turned on, the charge generated in the photodiode PD is transferred to the floating diffusion FD, and the voltage of the pixel signal SIG becomes the pixel voltage Vpix ( Figure 7 Then, after a predetermined time has passed from time t17, the pixel driving unit 13 changes the control signal TX from the high level to the low level ( Figure 7 (B)). Therefore, the transfer transistor MN2 is turned off.

[0089] Next, in the period from time t18 to time t20 (D phase period), the pixel circuit 20 performs AD conversion based on the voltage of the pixel signal SIG (pixel voltage Vpix). Specifically, at time t18, the reference signal generating section 12 starts to reduce the voltage of the reference signal REF from the voltage V1 by a predetermined degree of change ( Figure 7(C)). In addition, at time t18, the pixel driving unit 13 starts the increment operation of the time code CODE.

[0090] Then, at time t19, the voltage of the reference signal REF is lower than the voltage of the pixel signal SIG (pixel voltage Vpix) ( Figure 7 (C) and (D)). Therefore, the comparison circuit 22 changes the signal CMP from high level to low level ( Figure 7 (E)). Latch 23 latches time code CODE based on the transition of signal CMP. The code value of time code CODE latched by latch 23 at time t19 is CODE2. Code value CODE2 is a code value corresponding to the length of time from time t18 to time t19 and a code value corresponding to pixel voltage Vpix.

[0091] At time t20, the reference signal generating section 12 changes the voltage of the reference signal REF to the voltage V2 ( Figure 7 Then, in the period from time t20 to time t21, the vertical driving unit 14 supplies the code value CODE2 generated by the pixel circuit 20 to the signal processing section 15.

[0092] The signal processing unit 15 performs predetermined image processing based on the code values ​​CODE1 and CODE2 generated by each of the plurality of pixel circuits 20. For example, the signal processing unit 15 generates pixel values ​​based on the two code values ​​CODE1 and CODE2 using the principle of correlated double sampling. Furthermore, the signal processing unit 15 performs black level correction processing, etc., to correct the black level. Thus, the signal processing unit 15 generates an image signal Spic.

[0093] (Regarding the voltage follower circuit 34)

[0094] Next, description will be given of the operation of the voltage follower circuit 34. The voltage follower circuit 34 performs a negative feedback operation to generate a reference signal REF corresponding to the signal REF0 supplied from the signal generating circuit 31, and supplies the generated reference signal REF to the plurality of pixel circuits 20 in the pixel array 11.

[0095] First, the operation of the bias circuit 92 in the amplifier 35 will be described.

[0096] Figure 8 The operation example of the amplifier 35 is shown. In the amplifier 35, for example, transistors MN36, MN38, MN37, and MN40 form a loop. In this loop, the following expression is established according to the translinear law.

[0097] Vgs(MN36)+Vgs(MN40)=Vgs(MN38)+Vgs(MN37)...(EQ1)

[0098] Here, Vgs(MN36) is the gate-source voltage of transistor MN36, Vgs(MN40) is the gate-source voltage of transistor MN40, Vgs(MN38) is the gate-source voltage of transistor MN38, and Vgs(MN37) is the gate-source voltage of transistor MN37. If the dimensions (gate width W and gate length L) of the four transistors MN36, MN38, MN37, and MN40 are equal to each other, the following expressions EQ2 and EQ3 are obtained from expression EQ1.

[0099] I36=I38...(EQ2)

[0100] I37=I40...(EQ3)

[0101] Here, I36 is the current flowing through transistor MN36, I38 ​​is the current flowing through transistor MN38, I37 is the current flowing through transistor MN37, and I40 is the current flowing through transistor MN40. Currents I37 and I38 are set by the current value of constant current source IS and the current mirror ratio of transistors MP11 and MP19. These currents I37 and I38 are equal to each other. By setting currents I37 and I38 in expressions EQ2 and EQ3 in this manner, currents I36 and I40 in expressions EQ2 and EQ3 are also set.

[0102] Likewise, in the amplifier 35, for example, transistors MP18, MP21, MP20, and MP22 form a loop. In this loop, the following expression is established based on the translinear law.

[0103] Vgs(MP18)+Vgs(MP22)=Vgs(MP21)+Vgs(MP20)...(EQ4)

[0104] Here, Vgs(MP18) is the gate-source voltage of transistor MP18, Vgs(MP22) is the gate-source voltage of transistor MP22, Vgs(MP21) is the gate-source voltage of transistor MP21, and Vgs(MP20) is the gate-source voltage of transistor MP20. If the dimensions (gate width W and gate length L) of the four transistors MP18, MP21, MP20, and MP22 are equal to each other, the following expressions EQ5 and EQ6 are obtained from expression EQ4.

[0105] I18=I21...(EQ5)

[0106] I20=I22...(EQ6)

[0107] Here, I18 is the current flowing through transistor MP18, I21 is the current flowing through transistor MP21, I20 is the current flowing through transistor MP20, and I22 is the current flowing through transistor MP22. Currents I20 and I21 are set by the current value of constant current source IS, the current mirror ratio of transistors MP11 and MP12, and the current mirror ratio of transistors MN31 and MN39. These currents I20 and I21 are equal to each other. By setting currents I20 and I21 in expressions EQ5 and EQ6 in this manner, currents I18 and I20 in expressions EQ5 and EQ6 are also set.

[0108] As described above, the case where the sizes of the four transistors MN36, MN38, MN37, and MN40 are equal to each other and the sizes of the four transistors MP18, MP21, MP20, and MP22 are equal to each other is described as an example. In practice, currents I36 and I40 can be set by adjusting the sizes of MN36 and MN40. Similarly, currents I18 and I20 can be set by adjusting the sizes of MP18 and MP22.

[0109] The following focuses on the current paths of transistors MP17, MP18, MN36, and MN35. In a stable state where the voltage at the positive input terminal InP and the voltage at the negative input terminal InN are equal to each other, the amplifier 35 is set to establish the following expression, for example.

[0110] I17=I35=I18+I36...(EQ7)

[0111] Here, I17 is the current flowing through the transistor MP17, and I35 is the current flowing through the transistor MN35. In a steady state, as shown in Expression EQ7, the current I17 flowing through the transistor MP17 and the current I35 flowing through the transistor MN35 are equal to each other.

[0112] For example, when the voltage at the positive input terminal InP of amplifier 35 increases, the current flowing through transistor MP14 increases and the current flowing through transistor MP15 decreases instantaneously, resulting in an increase in current I25 flowing through transistor MN35 and a decrease in current I17 flowing through transistor MP17. In this case, the voltages at nodes N1 and N2 decrease. The absolute value of the gate-source voltage Vgs (MP18) of transistor MP18 decreases due to the voltage drop at node N1, thereby decreasing current I18 flowing through transistor MP18. By reducing the absolute value of the gate-source voltage Vgs (MP18) of transistor MP18 in this manner, as can be seen from expression EQ4, the absolute value of the gate-source voltage Vgs (MP22) of transistor MP22 increases. Consequently, current I22 flowing through transistor MP22 increases. Furthermore, the gate-source voltage Vgs (MN36) of transistor MN36 increases due to the voltage drop at node N2, thereby increasing current I36 flowing through transistor MN36. By increasing the absolute value of the gate-source voltage Vgs (MN36) of the transistor MN36 in this manner, as can be seen from Expression EQ1, the gate-source voltage Vgs (MN40) of the transistor MN40 decreases. Therefore, the current I40 flowing through the transistor MN40 decreases. Therefore, in the output circuit 93, the current I22 flowing through the transistor MP22 increases, and the current I40 flowing through the transistor MN40 decreases; therefore, the voltage at the output terminal OUT of the amplifier 35 increases. In the voltage follower circuit 34, the output terminal OUT of the amplifier 35 is connected to the negative input terminal InN; therefore, the voltage at the negative input terminal InN of the amplifier 35 increases. Then, when the voltage at the positive input terminal InP and the voltage at the negative input terminal InN become approximately equal, the state returns to the stable state (Expression EQ7).

[0113] Similarly, for example, when the voltage at the positive input terminal InP of amplifier 35 decreases, the current flowing through transistor MP15 increases and the current flowing through transistor MP14 decreases instantaneously, resulting in an increase in current I17 flowing through transistor MN17 and a decrease in current I35 flowing through transistor MP35. In this case, the voltages at nodes N1 and N2 increase. The absolute value of the gate-source voltage Vgs (MP18) of transistor MP18 increases due to the voltage increase at node N1, thereby increasing current I18 flowing through transistor MP18. By increasing the absolute value of the gate-source voltage Vgs (MP18) of transistor MP18 in this manner, as can be seen from expression EQ4, the absolute value of the gate-source voltage Vgs (MP22) of transistor MP22 decreases. Therefore, current I22 flowing through transistor MP22 decreases. In addition, the gate-source voltage Vgs (MN36) of transistor MN36 decreases due to the voltage increase at node N2, thereby decreasing current I36 flowing through transistor MN36. By reducing the absolute value of the gate-source voltage Vgs (MN36) of the transistor MN36 in this manner, as can be seen from Expression EQ1, the gate-source voltage Vgs (MN40) of the transistor MN40 increases. The current I40 flowing through the transistor MN40 increases. Therefore, in the output circuit 93, the current I40 flowing through the transistor MP40 increases, and the current I22 flowing through the transistor MN22 decreases; therefore, the voltage at the output terminal OUT of the amplifier 35 decreases. In the voltage follower circuit 34, the output terminal OUT of the amplifier 35 is connected to the negative input terminal InN; therefore, the voltage at the negative input terminal InN of the amplifier 35 decreases. Then, when the voltage at the positive input terminal InP and the voltage at the negative input terminal InN become approximately equal, the state returns to the stable state (Expression EQ7).

[0114] In the voltage follower circuit 34, when the signal REF0 input to the positive input terminal InP of the amplifier 35 changes, the currents I22 and I40 in the output circuit 93 may vary significantly. However, within the voltage follower circuit 34, the voltage changes at the various nodes are small. In addition, even when the voltage at the output terminal OUT varies within a wide voltage range from ground level to the power supply voltage level, for example, the voltage changes at the various nodes are small. As a result, the voltage follower circuit 34 can operate stably as described below.

[0115] Figure 9The following table shows the simulation results of the oscillation analysis in the voltage follower circuit 34. The characteristic WG_0 shows the gain characteristic when the load current is 0 mA, and the characteristic WP_0 shows the phase characteristic when the load current is 0 mA. The characteristic WG_500 shows the gain characteristic when the load current is 500 mA, and the characteristic WP_500 shows the phase characteristic when the load current is 500 mA.

[0116] In the voltage follower circuit 34, even when the load current varies greatly in this manner, variations in characteristics can be suppressed and a sufficient phase margin can be ensured. Therefore, the voltage follower circuit 34 can operate stably under various load conditions.

[0117] As described above, in the imaging device 1, the voltage follower circuit 34 can operate stably, thereby improving the image quality of captured images. Specifically, in the imaging device 1, the multiple pixel circuits 20 in the pixel array 11 each perform AD conversion; therefore, the reference signal generator 12 needs to provide the reference signal REF to the multiple pixel circuits 20. When providing the reference signal REF to the multiple pixel circuits 20 in this manner, it is desirable that the reference signal generator 12 be able to carry a large output current to drive the input capacitance of the multiple pixel circuits 20 and the wiring capacitance to the multiple pixel circuits 20.

[0118] For example, Figure 10 As shown, in the case where the reference signal generating section 12R is configured to provide the reference signal REF to a plurality of pixel circuits 20 using a source follower 34R, it is necessary to increase the gate width W of the transistor 18 of the source follower 34R. However, in this case, the gate-source parasitic capacitance of the transistor 18 increases; therefore, the cutoff frequency of the source follower 34R decreases, and the output impedance of the source follower 34R increases due to the influence of the cutoff frequency in the high-frequency region. Therefore, in the case where the reference signal generating section 12R intends to provide the reference signal REF to a plurality of pixel circuits 20, oscillation and ringing occur due to such frequency characteristics; therefore, it is difficult to provide the reference signal REF to the plurality of pixel circuits 20 in the pixel array 11. As a result, in an imaging device including such a reference signal generating section 12R, it is difficult to improve image quality.

[0119] Furthermore, for example, if a typical operational amplifier is used to construct a voltage follower circuit, and the reference signal generation unit is configured to use this voltage follower circuit to provide the reference signal REF to the plurality of pixel circuits 20, then, for example, when a significant change in load current occurs, the operating point of the operational amplifier will significantly change, resulting in, for example, a significant decrease in the phase margin. Therefore, it is difficult for this reference signal generation unit to provide the reference signal REF to the plurality of pixel circuits 20 in the pixel array 11. As a result, it is difficult to improve image quality in an imaging device including this reference signal generation unit.

[0120] On the contrary, in the camera device 1, if Figure 5 and Figure 6 As shown, the bias circuit 92, which utilizes the translinearity principle, sets the operating point of the output circuit 93. Therefore, as described above, when the voltage at the output terminal OUT varies within a wide voltage range from the ground level to the power supply voltage level, or when the load current varies significantly, the voltage variation at each node in the amplifier 35 can be reduced. Therefore, the reference signal generation unit 12 can provide the reference signal REF to the plurality of pixel circuits 20 in the pixel array 11. As a result, in the imaging device 1, image quality can be improved.

[0121] Therefore, the imaging device 1 includes a signal generating circuit 31 that generates a signal REF0 having a ramp waveform and a voltage follower circuit 34 that performs a voltage follower operation based on the signal REF0 to generate a reference signal REF and provides the reference signal REF to multiple pixel circuits 20, thereby improving the image quality of the captured image compared to the case of using a source follower.

[0122] Furthermore, in the imaging device 1, the output circuit 93 of the amplifier 35 includes a P-type transistor MP22 having a source connected to the power supply node NVDD and a drain connected to the output terminal OUT, and an N-type transistor MP40 having a source connected to the ground node NVSS and a drain connected to the output terminal OUT. Consequently, the output circuit 93 is capable of rail-to-rail operation, enabling the reference signal generation unit 12 to generate a reference signal REF having a large amplitude. Consequently, for example, in the imaging device 1, the dynamic range of captured images can be improved, thereby enhancing the image quality of the captured images.

[0123] In the imaging device 1, the amplifier 35 includes transistors MP17, MP18, and MN36, as well as transistor MN35, in a current path connecting power supply node NVDD and ground node NVSS. Transistor MP17 has a source connected to power supply node NVDD, and transistor MN35 has a source connected to ground node NVSS. Transistor MP18 is provided between transistors MP17 and MN35 in this current path and has a source connected to node N1 in this current path, a gate supplied with a bias voltage, and a drain connected to node N2 in this current path. Transistor MN36 is provided between transistors MP17 and MN35 in this current path and has a source connected to node N2, a gate supplied with a bias voltage, and a drain connected to node N1. Amplifier 35 then controls the current flowing between nodes N1 and N2 based on the current flowing through transistors MP14 and MP15 of the differential input circuit 19. Specifically, a current corresponding to the current flowing through transistor MP15 of differential input circuit 19 flows through transistor MP17, and a current corresponding to the current flowing through transistor MP14 of differential input circuit 19 flows through transistor MN35. Consequently, voltage variations at various nodes in voltage follower circuit 34 can be reduced, and reference signal generation section 12 can provide reference signal REF to multiple pixel circuits 20. As a result, image quality can be improved in imaging device 1. Furthermore, frame rate can be increased in imaging device 1. Consequently, image quality can be further improved in imaging device 1.

[0124] [Effect]

[0125] As described above, in this embodiment, a signal generating circuit that generates a signal REF0 having a ramp waveform and a voltage follower circuit that performs a voltage follower operation based on the signal REF0 to generate a reference signal and provides the reference signal to multiple pixel circuits are provided, thereby improving the image quality of the captured image.

[0126] [Variation 1]

[0127] In the above embodiment, transistors MP14 and MP15, which are P-type MOS transistors, are used to form the differential pair of differential input circuit 91. However, the present invention is not limited to this. Alternatively, N-type MOS transistors may be used to form the differential pair of differential input circuit 91. Amplifier 35A according to this variation will be described in detail below.

[0128] Figure 11 1 shows an example of a configuration of the amplifier 35A. The amplifier 35A includes transistors MN51 to MN54 and MP41 to MP43. The transistors MN51 to MN54 are N-type MOS transistors, and the transistors MP41 to MP43 are P-type MOS transistors.

[0129] Transistor MN51 has a gate connected to the negative input terminal InN of amplifier 35A, a drain connected to the gate and drain of transistor MP41 and to the gate of transistor MP17, and a source connected to the source of transistor MN52 and to the drain of transistor MN53. Transistor MN52 has a gate connected to the positive input terminal InP of amplifier 35A, a drain connected to the gate and drain of transistor MP42 and to the gate of transistor MP43, and a source connected to the source of transistor MN51 and to the drain of transistor MN53. Transistor MN53 has a gate connected to the gate and drain of transistor MN31, to the drain of transistor MP12, and to the gate of transistor MN39, a drain connected to the sources of transistors MN51 and MN52, and a source connected to ground node NVSS. Transistor MP41 has a gate connected to the drains of transistors MP41 and MN51, as well as the gate of transistor MP17, a source connected to power supply node NVDD, and a drain connected to the gate of transistor MP41, the drain of transistor MN51, and the gate of transistor MP17. Transistor MP42 has a gate connected to the drains of transistors MP42 and MN52 and to the gate of transistor MP43. Its source is connected to power supply node NVDD, and its drain is connected to the gate of transistor MP42 and the drain of transistor MN52, and to the gate of transistor MP43. Transistors MN51 and MN52 form a differential pair. Transistors MP41 and MP17 form a current mirror circuit, and transistors MP42 and MP43 form a current mirror circuit.

[0130] Transistors MN51 to MN53, MP41, and MP42 correspond to Figure 5 The differential input circuit 91 is shown.

[0131] Transistor MP43 has a gate connected to the gate and drain of transistor MP42 and to the drain of transistor MN52, a source connected to power supply node NVDD, and a drain connected to the gate and drain of transistor MN54 and the gate of transistor MN35. Transistor MN54 has a gate connected to the drains of transistors MN54 and MP43 and to the gate of transistor MN35, a drain connected to the gate of transistor MN54 and the drain of transistor MP43 and to the gate of transistor MN35, and a source connected to ground node NVSS. Transistors MN54 and MN35 form a current mirror circuit.

[0132] Transistors MP43, MP17 to MP21, MN54, and MN35 to MN39 correspond to Figure 5 The bias circuit 92 is shown.

[0133] The ground node NVSS corresponds to a specific example of a "first power supply node" in the present disclosure. The power supply node NVDD corresponds to a specific example of a "second power supply node" in the present disclosure. The transistor MN40 corresponds to a specific example of a "first transistor" in the present disclosure. The transistor MP22 corresponds to a specific example of a "second transistor" in the present disclosure. The pair of transistors MN51 and MN52 corresponds to a specific example of a "first differential transistor pair" in the present disclosure. The transistor MN35 corresponds to a specific example of a "third transistor" in the present disclosure. The transistor MP17 corresponds to a specific example of a "fourth transistor" in the present disclosure. The transistor MN36 corresponds to a specific example of a "fifth transistor" in the present disclosure. The transistor MP18 corresponds to a specific example of a "sixth transistor" in the present disclosure. The node N2 corresponds to a specific example of a "first node" in the present disclosure. The node N1 corresponds to a specific example of a "second node" in the present disclosure. The transistor MP42 corresponds to a specific example of a "seventh transistor" in the present disclosure. The transistor MP41 corresponds to a specific example of an "eighth transistor" in the present disclosure. The transistor MP43 corresponds to a specific example of a "ninth transistor" in the present disclosure. The transistor MN54 corresponds to a specific example of a “tenth transistor” in the present disclosure.

[0134] For example, when the voltage at the positive input terminal InP of the amplifier 35A increases, the current flowing through the transistor MN52 increases and the current flowing through the transistor MN51 decreases instantaneously, causing the current flowing through the transistor MN35 to increase and the current flowing through the transistor MP17 to decrease. In this case, the voltages at the nodes N1 and N2 decrease. Therefore, as in the above-described embodiment, in the output circuit 93, the current flowing through the transistor MP22 increases and the current flowing through the transistor MN40 decreases; thus, the voltage at the output terminal OUT of the amplifier 35A increases. Then, when the voltage at the positive input terminal InP and the voltage at the negative input terminal InN become approximately equal, the state returns to a stable state.

[0135] Similarly, for example, when the voltage at the positive input terminal InP of amplifier 35A decreases, the current flowing through transistor MP51 increases and the current flowing through transistor MP52 decreases instantaneously, causing the current flowing through transistor MN17 to increase and the current flowing through transistor MP35 to decrease. In this case, the voltages at nodes N1 and N2 increase. Consequently, as in the above-described embodiment, in output circuit 93, the current flowing through transistor MN40 increases and the current flowing through transistor MP22 decreases; thus, the voltage at output terminal OUT of amplifier 35A decreases. Then, when the voltage at positive input terminal InP and the voltage at negative input terminal InN become approximately equal, the state returns to a stable state.

[0136] [Variation 2]

[0137] In the above embodiment, the current mirror circuit (transistors MN32 to MN35) is used to connect the differential input circuit 91 and the bias circuit 92, but the present invention is not limited thereto. The amplifier 35B according to this modification will be described in detail below.

[0138] Figure 12 1 is a block diagram of an amplifier 35B. The amplifier 35B includes transistors MN61 and MN62. The transistors MN61 and MN62 are N-type MOS transistors.

[0139] Transistor MN61 has a gate connected to the gate and drain of transistor MN31, the drain of transistor MP12, and the gates of transistors MN62 and MN39. Its drain is connected to the drains of transistors MP14 and MP16, and the gates of transistors MP16 and MP17. Its source is connected to ground node NVSS. Transistor MN62 has a gate connected to the gate and drain of transistor MN31, the drain of transistor MP12, and the gates of transistors MN61 and MN39. Its drain is connected to node N2, and its source is connected to ground node NVSS. Transistors MN31, MN61, and MN62 form a current mirror circuit.

[0140] Transistors MP13 to MP15 correspond to Figure 5 The differential input circuit 91 shown. Transistors MP16 to MP21, MN61, MN62, and MN36 to MN39 correspond to Figure 5 The bias circuit 92 is shown. Therefore, in the amplifier 35B, the differential input circuit 91 and the bias circuit 92 are connected using a folded cascade circuit.

[0141] The power supply node NVDD corresponds to a specific example of a "first power supply node" in the present disclosure. The ground node NVSS corresponds to a specific example of a "second power supply node" in the present disclosure. The transistor MP22 corresponds to a specific example of a "first transistor" in the present disclosure. The transistor MN40 corresponds to a specific example of a "second transistor" in the present disclosure. The pair of transistors MP14 and MP15 corresponds to a specific example of a "first differential transistor pair" in the present disclosure. The transistor MP17 corresponds to a specific example of a "third transistor" in the present disclosure. The transistor MN35 corresponds to a specific example of a "fourth transistor" in the present disclosure. The transistor MP18 corresponds to a specific example of a "fifth transistor" in the present disclosure. The transistor MN36 corresponds to a specific example of a "sixth transistor" in the present disclosure. The node N1 corresponds to a specific example of a "first node" in the present disclosure. The node N2 corresponds to a specific example of a "second node" in the present disclosure. The transistor MN61 corresponds to a specific example of an "eleventh transistor" in the present disclosure. The transistor MP16 corresponds to a specific example of a "seventh transistor" in the present disclosure. The transistor MP14 corresponds to a specific example of a "first input transistor" in the present disclosure. The transistor MP15 corresponds to a specific example of a “second input transistor” in the present disclosure.

[0142] The total current of the current flowing through transistor MP14 of differential input circuit 91 and the current flowing through transistor MP16 flows through transistor MN61 as a current having a predetermined current value. That is, transistor MN61 operates as a constant current source; therefore, the current value of the total current is constant. Similarly, the total current of the current flowing through transistor MP15 of differential input circuit 91 and the currents flowing through transistors MP18 and MN36 flows through transistor MN62 as a current having a predetermined current value. That is, transistor MN62 operates as a constant current source; therefore, the current value of the total current is constant.

[0143] For example, when the voltage at the positive input terminal InP of amplifier 35B increases, the current flowing through transistor MP14 increases and the current flowing through transistor MP15 decreases instantaneously. This decreases the current flowing through transistor MP15, thereby increasing the current flowing from transistors MP18 and MN36 to transistor MN62. Furthermore, the current flowing through transistor MP14 increases, thereby decreasing the current flowing from transistor MP16 to transistor MN61. Consequently, the current flowing through transistor MP17 decreases. In this case, the voltages at nodes N1 and N2 decrease. Thus, as in the above-described embodiment, in output circuit 93, the current flowing through transistor MP22 increases, while the current flowing through transistor MN40 decreases; thus, the voltage at output terminal OUT of amplifier 35B increases. Then, when the voltages at the positive input terminal InP and the negative input terminal InN become approximately equal, the state returns to a stable state.

[0144] Similarly, for example, when the voltage at the positive input terminal InP of amplifier 35B decreases, the current flowing through transistor MP15 increases and the current flowing through transistor MP14 decreases instantaneously. This decreases the current flowing through transistor MP14, thereby increasing the current flowing from transistor MP16 to transistor MN61. Consequently, the current flowing through transistor MP17 increases. Furthermore, this increases the current flowing through transistor MP15, thereby decreasing the current flowing from transistors MP18 and MN36 to transistor MN62. In this case, the voltages at nodes N1 and N2 rise. Consequently, as in the above-described embodiment, in output circuit 93, the current flowing through transistor MN40 increases, while the current flowing through transistor MP22 decreases; thus, the voltage at output terminal OUT of amplifier 35B decreases. Subsequently, when the voltages at the positive input terminal InP and the negative input terminal InN become approximately equal, the state returns to a stable state.

[0145] [Variation 3]

[0146] In the above embodiment, one differential pair is used to constitute the differential input circuit 91, but the present invention is not limited thereto. Alternatively, two differential pairs may be used to constitute the differential input circuit 91. The amplifier 35C according to this modification will be described in detail below.

[0147] Figure 13 1 shows an example of a configuration of an amplifier 35C. The amplifier 35C includes transistors MN51 to MN53, MP71 to MP75, and MN81 to MN85, and bias circuits 38 and 39. The transistors MN51 to MN53 and MN81 to MN85 are N-type MOS transistors, and the transistors MP71 to MP75 are P-type MOS transistors.

[0148] Transistor MN51 has a gate connected to the negative input terminal InN of amplifier 35C, a drain connected to the drain of transistor MP71 and the source of transistor MP72, and a source connected to the source of transistor MN52 and the drain of transistor MN53. Transistor MN52 has a gate connected to the positive input terminal InP of amplifier 35C, a drain connected to the drain of transistor MP74 and the source of transistor MP75, and a source connected to the source of transistor MN51 and the drain of transistor MN53. Transistor MN53 has a gate connected to the gate and drain of transistor MN31, the drain of transistor MP12, and the gate of transistor MN39, a drain connected to the sources of transistors MN51 and MN52, and a source connected to ground node NVSS. Transistors MN51 and MN52 form a differential pair.

[0149] Transistors MP13 to MP15 and MN51 to MN53 correspond to Figure 5 The differential input circuit 91 is shown.

[0150] Transistor MP71 has a gate connected to node N3, a source connected to power supply node NVDD, and a drain connected to the drain of transistor MN51 and the source of transistor MP72. Transistor MP72 has a gate supplied with a bias voltage from bias circuit 38, a source connected to the drains of transistors MP71 and MN51, and a drain connected to node N3. Transistor MP73 has a gate connected to the gate and drain of transistor MP21, the drain of transistor MN39, and the gate of transistor MP18, a source connected to node N3, and a drain connected to node N4. Transistor MN83 has a gate connected to the gate and drain of transistor MN38, the drain of transistor MP19, and the gate of transistor MN36, a drain connected to node N3, and a source connected to node N4. Transistor MN82 has a gate supplied with a bias voltage from bias circuit 39, a drain connected to node N4, and a source connected to the drains of transistors MN81 and MP14. Transistor MN81 has a gate connected to node N4, a drain connected to the drain of transistor MP14 and the source of transistor MN82, and a source connected to ground node NVSS. Transistors MP71 and MP74 form a current mirror circuit, and transistors MN81 and MN84 form a current mirror circuit.

[0151] Transistor MP74 has a gate connected to node N3, a source connected to power supply node NVDD, and a drain connected to the drain of transistor MN52 and the source of transistor MP75. Transistor MP75 has a gate supplied with a bias voltage from bias circuit 38, a source connected to the drains of transistors MP74 and MN52, and a drain connected to node N1. Transistor MN85 has a gate supplied with a bias voltage from bias circuit 39, a drain connected to node N2, and a source connected to the drains of transistors MN84 and MP15. Transistor MN84 has a gate connected to node N4, a drain connected to the drain of transistor MP15 and the source of transistor MN85, and a source connected to ground node NVSS.

[0152] The bias circuits 38 and 39 are each configured to generate a bias voltage.

[0153] Transistors MP71 to MP75, MN81 to MN85, MP18 to MP21, MN36 to MN39, and bias circuits 38 and 39 correspond to Figure 5 The bias circuit 92 is shown.

[0154] The power supply node NVDD corresponds to a specific example of a "first power supply node" in the present disclosure. The ground node NVSS corresponds to a specific example of a "second power supply node" in the present disclosure. The transistor MP22 corresponds to a specific example of a "first transistor" in the present disclosure. The transistor MN40 corresponds to a specific example of a "second transistor" in the present disclosure. The pair of transistors MP14 and MP15 corresponds to a specific example of a "first differential transistor pair" in the present disclosure. The transistor MP14 corresponds to a specific example of a "first input transistor" in the present disclosure. The transistor MP15 corresponds to a specific example of a "second input transistor" in the present disclosure. The transistor MP17 corresponds to a specific example of a "third transistor" in the present disclosure. The transistor MN35 corresponds to a specific example of a "fourth transistor" in the present disclosure. The transistor MP18 corresponds to a specific example of a "fifth transistor" in the present disclosure. The transistor MN36 corresponds to a specific example of a "sixth transistor" in the present disclosure. The node N1 corresponds to a specific example of a "first node" in the present disclosure. The node N2 corresponds to a specific example of a "second node" in the present disclosure.

[0155] The pair of transistors MN52 and MN51 corresponds to a specific example of a “second differential transistor pair” in the present disclosure. Transistor MN52 corresponds to a specific example of a “third input transistor” in the present disclosure. Transistor MN51 corresponds to a specific example of a “fourth input transistor” in the present disclosure. Transistor MP71 corresponds to a specific example of a “thirteenth transistor” in the present disclosure. Transistor MN81 corresponds to a specific example of a “fourteenth transistor” in the present disclosure. Transistor MP73 corresponds to a specific example of a “fifteenth transistor” in the present disclosure. Transistor MN83 corresponds to a specific example of a “sixteenth transistor” in the present disclosure. Node N3 corresponds to a specific example of a “third node” in the present disclosure. Node N4 corresponds to a specific example of a “fourth node” in the present disclosure.

[0156] [Other modifications]

[0157] In addition, two or more of these modifications may be combined.

[0158] <2. Example of use of the imaging device>

[0159] Figure 14 The above-described imaging device 1 is used as an example of a method of sensing light such as visible light, infrared light, ultraviolet light, and X-rays.

[0160] - Devices that capture images for viewing, such as digital cameras and mobile devices with camera capabilities.

[0161] - Equipment used in transportation, such as on-board sensors that capture images of the front, rear, surroundings, and interior of a car for safe driving, such as automatic parking, and for identifying the driver's status; surveillance cameras that monitor moving vehicles and roads; and ranging sensors that measure the distance between vehicles.

[0162] -Devices used in home appliances such as TVs, refrigerators, and air conditioners to capture images of user gestures and operate the device based on those gestures.

[0163] -Equipment for healthcare use, such as endoscopes and devices that take images of blood vessels by receiving infrared light.

[0164] -Equipment used for security purposes, such as surveillance cameras for crime prevention and cameras for personnel authentication.

[0165] - Devices for cosmetic purposes, such as skin measurement devices for taking images of the skin and microscopes for taking images of the scalp.

[0166] - Equipment for sports use, such as action cameras and wearable cameras for sports use, etc.

[0167] -Equipment for agricultural use, such as cameras used to monitor field and crop conditions.

[0168] <3. Application Examples of Mobile Objects>

[0169] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object, such as an automobile, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, or a robot.

[0170] Figure 15 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0171] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 15 In the illustrated example, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, the functional configuration of the integrated control unit 12050 includes a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0172] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for the following devices: a drive force generating device, such as an internal combustion engine or a drive motor, for generating drive force for the vehicle; a drive force transmission mechanism for transmitting drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating braking force for the vehicle.

[0173] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system; a smart key system; power windows; or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves transmitted from a mobile device that replaces a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, and so on.

[0174] The vehicle exterior information detection unit 12030 detects information outside the vehicle that includes the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can detect objects such as pedestrians, vehicles, obstacles, signs, or letters on the road surface, or perform distance detection processing.

[0175] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output this electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0176] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 for detecting the driver's condition. For example, the driver status detection unit 12041 includes a camera for capturing the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration, or determine whether the driver is dozing off.

[0177] Based on the information outside or inside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for implementing advanced driver assistance system (ADAS) functions, such as collision avoidance or impact mitigation, following driving based on a following distance, speed maintenance driving, vehicle collision warning, or lane departure warning.

[0178] In addition, the microcomputer 12051 is capable of controlling the driving force generating device, steering mechanism or braking device, etc. based on the information outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby performing collaborative control for realizing automatic driving, etc., which enables the vehicle to drive autonomously without relying on the driver's operation.

[0179] In addition, based on information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights to switch from high beam to low beam based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030, thereby performing cooperative control for glare prevention.

[0180] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can visually or auditorily notify information to passengers on the vehicle or outside the vehicle. Figure 15 In the example of FIG, as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0181] Figure 16 12031 is a diagram showing an example of the installation position of the camera unit 12031.

[0182] exist Figure 16 , the camera unit 12031 includes camera units 12101 , 12102 , 12103 , 12104 and 12105 .

[0183] For example, camera units 12101, 12102, 12103, 12104, and 12105 are located at the front nose, rearview mirror, rear bumper, and rear door of vehicle 12100, as well as at the upper portion of the windshield inside the vehicle. Camera unit 12101 located at the front nose and camera unit 12105 located at the upper portion of the windshield inside the vehicle primarily capture images in front of vehicle 12100. Camera units 12102 and 12103 located at the rearview mirror primarily capture images from the side of vehicle 12100. Camera unit 12104 located at the rear bumper or rear door primarily captures images from the rear of vehicle 12100. Camera unit 12105 located at the upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0184] By the way, Figure 16 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located on the rearview mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, located on the rear bumper or rear door. For example, by superimposing the image data acquired by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 as viewed from above is obtained.

[0185] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or an imaging element having pixels for phase difference detection.

[0186] For example, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111-12114 and the change in this distance over time (relative speed to vehicle 12100) based on the distance information obtained from imaging units 12101-12104. This allows the microcomputer 12051 to identify the three-dimensional object closest to vehicle 12100 on its travel path and traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., greater than or equal to 0 km / h) as the leading vehicle. Furthermore, microcomputer 12051 can pre-set a following distance to be maintained ahead of the leading vehicle and execute automatic braking control (including follow-up stop control) or automatic acceleration control (including follow-up start control). This allows for cooperative control, such as autonomous driving, that allows the vehicle to travel autonomously without relying on driver input.

[0187] For example, based on the distance information obtained from the cameras 12101-12104, the microcomputer 12051 can classify 3D object data related to three-dimensional objects into 3D object data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data to automatically avoid obstacles. For example, the microcomputer 12051 classifies obstacles around the vehicle 12100 into those that the driver of the vehicle 12100 can visually identify and those that are difficult for the driver of the vehicle 12100 to visually identify. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is greater than or equal to a set value, indicating a potential collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or display unit 12062 and executes forced deceleration or evasive steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist in driving to avoid collisions.

[0188] At least one of the imaging units 12101-12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether the pedestrian exists in the images captured by the imaging units 12101-12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras; and performing pattern matching on a series of feature points representing the object's outline to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to superimpose and display a rectangular outline on the identified pedestrian for emphasis. The audio / video output unit 12052 may also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0189] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the camera unit 12031 in the above-described configuration. Consequently, the vehicle control system 12000 can improve the image quality of images captured by the camera unit 12031. This enables the vehicle control system 12000 to implement high-precision functions such as collision avoidance and impact mitigation, vehicle-to-vehicle distance-based follow-up driving, speed maintenance driving, collision warning, and lane departure warning.

[0190] Although the present technology has been described above with reference to some embodiments, modifications, and specific application examples, the present technology is not limited to these embodiments and the like, and can be modified in various ways.

[0191] For example, in the above embodiment, the pixels P are provided on two semiconductor substrates 101 and 102, but the present invention is not limited thereto. The pixels may be provided on one semiconductor substrate, or may be provided on three or more semiconductor substrates.

[0192] It should be noted that the effects described here are merely illustrative and not restrictive, and other effects may be included.

[0193] Note that the present technology may have the following configurations. According to the present technology having the following configurations, the image quality of captured images can be improved. (1)

[0195] A camera device, comprising:

[0196] a plurality of pixel circuits each generating a pixel signal including a pixel voltage corresponding to an amount of received light and performing AD conversion by comparing the pixel signal with a reference signal; and

[0197] A reference signal generating section includes a signal generating circuit and a voltage follower circuit. The signal generating circuit generates a voltage signal having a ramp waveform. The voltage follower circuit performs a voltage follower operation based on the voltage signal to generate the reference signal and provides the reference signal to the plurality of pixel circuits. (2)

[0199] The imaging device according to (1), wherein

[0200] The voltage follower circuit includes an amplifier having a positive input terminal to which the voltage signal is supplied, a negative input terminal, an output terminal that outputs the reference signal, and an output circuit connected to the output terminal, and

[0201] The output circuit includes:

[0202] a first transistor of a first conductivity type having a source connected to a first power supply node, a drain connected to the output terminal, and a gate; and

[0203] A second transistor of a second conductivity type has a source connected to the second power supply node, a drain connected to the output terminal, and a gate. (3)

[0205] The imaging device according to (2), wherein

[0206] The amplifier comprises:

[0207] a first differential transistor pair connected to the positive input terminal and the negative input terminal and generating a differential current including a first current and a second current;

[0208] a third transistor of the first conductivity type, disposed in a first current path connecting the first power supply node and the second power supply node, and having a source, a gate, and a drain connected to the first power supply node;

[0209] a fourth transistor of the second conductivity type, disposed in the first current path and having a source, a gate, and a drain connected to the second power supply node;

[0210] a fifth transistor of the first conductivity type, which is provided between the third transistor and the fourth transistor in the first current path and has a source connected to a first node in the first current path, a drain connected to a second node in the first current path, and a gate supplied with a first bias voltage; and

[0211] a sixth transistor of the second conductivity type, which is provided between the third transistor and the fourth transistor in the first current path and has a drain connected to the first node, a source connected to the second node, and a gate supplied with a second bias voltage,

[0212] the amplifier controlling a current flowing between the first node and the second node in the first current path based on the first current and the second current,

[0213] The gate of the first transistor is connected to the first node, and

[0214] The gate of the second transistor is connected to the second node. (4)

[0216] The imaging device according to (3), wherein

[0217] A current corresponding to the first current flows through the third transistor, and

[0218] A current corresponding to the second current flows through the fourth transistor. (5)

[0220] The imaging device according to (3) or (4), wherein

[0221] The amplifier comprises:

[0222] a seventh transistor of the second conductivity type having a drain, a gate connected to the drain, and a source connected to the second power supply node, and wherein the first current flows through the seventh transistor;

[0223] an eighth transistor of the second conductivity type having a drain, a gate connected to the drain and the gate of the fourth transistor, and a source connected to the second power supply node, and wherein the second current flows through the eighth transistor;

[0224] a ninth transistor of the second conductivity type, provided in a second current path connecting the first power supply node and the second power supply node, and having a drain, a gate connected to the gate and the drain of the seventh transistor, and a source connected to the second power supply node; and

[0225] The tenth transistor of the first conductivity type is provided in the second current path and has a drain, a gate connected to the drain and the gate of the third transistor, and a source connected to the first power supply node. (6)

[0227] The imaging device according to (3), wherein

[0228] A current corresponding to the first current flows through the third transistor, and

[0229] A current having a predetermined current value including the second current flows through the fourth transistor. (7)

[0231] The imaging device according to (3) or (6), wherein

[0232] The amplifier further comprises:

[0233] an eleventh transistor of the second conductivity type, which is provided in a second current path connecting the first power supply node and the second power supply node, and has a drain, a gate, and a source connected to the second power supply node, and through which a current having a predetermined current value including the first current flows; and

[0234] a twelfth transistor of the first conductivity type, which is provided in the second current path and has a drain, a gate connected to the drain and the gate of the third transistor, and a source connected to the first power supply node,

[0235] The first differential transistor pair includes:

[0236] a first input transistor of the first conductivity type having a drain and generating the first current; and

[0237] the second input transistor of the first conductivity type having a drain and generating the second current,

[0238] The drain of the eleventh transistor is connected to the drain of the first input transistor, and

[0239] The drain of the fourth transistor is connected to the drain of the second input transistor. (8)

[0241] The imaging device according to (3), wherein

[0242] The amplifier further includes a second differential transistor pair connected to the positive input terminal and the negative input terminal and generating a differential current including a third current and a fourth current, and

[0243] The amplifier controls a current flowing between the first node and the second node based on the first current, the second current, the third current, and the fourth current. (9)

[0245] The imaging device according to (3) or (8), wherein

[0246] The amplifier further comprises:

[0247] a thirteenth transistor of the first conductivity type, provided in a second current path connecting the first power supply node and the second power supply node, and having a source connected to the first power supply node, a gate connected to a third node in the second current path, and a drain;

[0248] a fourteenth transistor of the second conductivity type, provided in the second current path and having a source connected to the second power supply node, a gate connected to a fourth node in the second current path, and a drain;

[0249] a fifteenth transistor of the first conductivity type, which is provided between the thirteenth transistor and the fourteenth transistor in the second current path and has a source connected to the third node, a drain connected to the fourth node, and a gate supplied with the first bias voltage; and

[0250] a sixteenth transistor of the second conductivity type, which is provided between the thirteenth transistor and the fourteenth transistor in the second current path and has a drain connected to the third node, a source connected to the fourth node, and a gate supplied with the second bias voltage,

[0251] The first differential transistor pair includes:

[0252] a first input transistor of the first conductivity type having a drain and generating the first current; and

[0253] the second input transistor of the first conductivity type having a drain and generating the second current,

[0254] The second differential transistor pair includes:

[0255] a third input transistor of the second conductivity type having a drain and generating the third current; and

[0256] the fourth input transistor of the second conductivity type having a drain and generating the fourth current,

[0257] The drain of the third transistor is connected to the drain of the third input transistor,

[0258] The drain of the fourth transistor is connected to the drain of the second input transistor,

[0259] The drain of the thirteenth transistor is connected to the drain of the fourth input transistor, and

[0260] The drain of the fourteenth transistor is connected to the drain of the first input transistor.

[0261] This application claims the benefit of Japanese Priority Patent Application JP 2020-052229 filed in the Japan Patent Office on March 24, 2020, the entire contents of which are incorporated herein by reference.

[0262] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A camera device comprising: a plurality of pixel circuits each generating a pixel signal including a pixel voltage corresponding to an amount of received light and performing AD conversion by comparing the pixel signal with a reference signal; and a reference signal generating section including a signal generating circuit and a voltage follower circuit, wherein the signal generating circuit generates a voltage signal having a ramp waveform, the voltage follower circuit performs a voltage follower operation based on the voltage signal to generate the reference signal, and provides the reference signal to the plurality of pixel circuits, wherein The voltage follower circuit includes an amplifier having a positive input terminal supplied with the voltage signal, a negative input terminal, an output terminal connected to the negative input terminal and outputting the reference signal, and an output circuit connected to the output terminal, and The output circuit includes: a first transistor of a first conductivity type having a source connected to a first power supply node, a drain connected to the output terminal, and a gate; and a second transistor of a second conductivity type having a source connected to the second power supply node, a drain connected to the output terminal, and a gate, The amplifier includes a first differential transistor pair connected to the positive input terminal and the negative input terminal and generating a differential current including a first current and a second current.

2. The imaging device according to claim 1, wherein The amplifier comprises: a third transistor of the first conductivity type, disposed in a first current path connecting the first power supply node and the second power supply node, and having a source, a gate, and a drain connected to the first power supply node; a fourth transistor of the second conductivity type, disposed in the first current path and having a source, a gate, and a drain connected to the second power supply node; a fifth transistor of the first conductivity type, which is provided between the third transistor and the fourth transistor in the first current path and has a source connected to a first node in the first current path, a drain connected to a second node in the first current path, and a gate supplied with a first bias voltage; and a sixth transistor of the second conductivity type, which is provided between the third transistor and the fourth transistor in the first current path and has a drain connected to the first node, a source connected to the second node, and a gate supplied with a second bias voltage, the amplifier controlling a current flowing between the first node and the second node in the first current path based on the first current and the second current, The gate of the first transistor is connected to the first node, and The gate of the second transistor is connected to the second node.

3. The imaging device according to claim 2, wherein: A current corresponding to the first current flows through the third transistor, and A current corresponding to the second current flows through the fourth transistor.

4. The imaging device according to claim 2, wherein: The amplifier comprises: a seventh transistor of the second conductivity type having a drain, a gate connected to the drain, and a source connected to the second power supply node, and wherein the first current flows through the seventh transistor; an eighth transistor of the second conductivity type having a drain, a gate connected to the drain and the gate of the fourth transistor, and a source connected to the second power supply node, and wherein the second current flows through the eighth transistor; a ninth transistor of the second conductivity type, provided in a second current path connecting the first power supply node and the second power supply node, and having a drain, a gate connected to the gate and the drain of the seventh transistor, and a source connected to the second power supply node; and The tenth transistor of the first conductivity type is provided in the second current path and has a drain, a gate connected to the drain and the gate of the third transistor, and a source connected to the first power supply node.

5. The imaging device according to claim 2, wherein: A current corresponding to the first current flows through the third transistor, and A current having a predetermined current value including the second current flows through the fourth transistor. The imaging device according to claim 2 , wherein: The amplifier further comprises: an eleventh transistor of the second conductivity type, which is provided in a second current path connecting the first power supply node and the second power supply node, and has a drain, a gate, and a source connected to the second power supply node, and through which a current having a predetermined current value including the first current flows; and a twelfth transistor of the first conductivity type, which is provided in the second current path and has a drain, a gate connected to the drain and the gate of the third transistor, and a source connected to the first power supply node, The first differential transistor pair includes: a first input transistor of the first conductivity type having a drain and generating the first current; and the second input transistor of the first conductivity type having a drain and generating the second current, The drain of the eleventh transistor is connected to the drain of the first input transistor, and The drain of the fourth transistor is connected to the drain of the second input transistor.

7. The imaging device according to claim 2, wherein: The amplifier further includes a second differential transistor pair connected to the positive input terminal and the negative input terminal and generating a differential current including a third current and a fourth current, and The amplifier controls a current flowing between the first node and the second node based on the first current, the second current, the third current, and the fourth current.

8. The imaging device according to claim 7, wherein: The amplifier further comprises: a thirteenth transistor of the first conductivity type, provided in a second current path connecting the first power supply node and the second power supply node, and having a source connected to the first power supply node, a gate connected to a third node in the second current path, and a drain; a fourteenth transistor of the second conductivity type, provided in the second current path and having a source connected to the second power supply node, a gate connected to a fourth node in the second current path, and a drain; a fifteenth transistor of the first conductivity type, which is provided between the thirteenth transistor and the fourteenth transistor in the second current path and has a source connected to the third node, a drain connected to the fourth node, and a gate supplied with the first bias voltage; and a sixteenth transistor of the second conductivity type, which is provided between the thirteenth transistor and the fourteenth transistor in the second current path and has a drain connected to the third node, a source connected to the fourth node, and a gate supplied with the second bias voltage, The first differential transistor pair includes: a first input transistor of the first conductivity type having a drain and generating the first current; and the second input transistor of the first conductivity type having a drain and generating the second current, The second differential transistor pair includes: a third input transistor of the second conductivity type having a drain and generating the third current; and the fourth input transistor of the second conductivity type having a drain and generating the fourth current, The drain of the third transistor is connected to the drain of the third input transistor, The drain of the fourth transistor is connected to the drain of the second input transistor, The drain of the thirteenth transistor is connected to the drain of the fourth input transistor, and The drain of the fourteenth transistor is connected to the drain of the first input transistor.

Images