A method and a detection system for detecting appearance defects of wafer-level packaged chips

Abstract

The present invention discloses a method and a detection system for detecting appearance defects of wafer-level packaged chips. Under the illumination of a high-angle annular light source and a low-angle annular light source, a camera is used to separately image the chips on the tray. According to a plurality of regional image templates, corresponding regional images are respectively extracted from each of the chip images, and different second-level algorithms are used to process different regional images; the detection results of each second-level algorithm are summarized to obtain the detection result output of a single chip. By circularly detecting, the detection results of each chip are obtained and summarized to obtain the result output of the entire tray of chips; through the combination of imaging and algorithms, the present invention can more effectively detect target defects and avoid missed detections.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer-level chip packaging detection, and particularly to a method and a detection system for detecting appearance defects of wafer-level packaged chips. Background Art

[0002] The WLCSP packaging technology is different from traditional packaging methods. All operations are directly completed on the wafer after the front-end wafer manufacturing process. Packaging and testing are carried out on the whole wafer, and then it is cut into single-chip IC small particles, so that WLCSP can achieve the smallest package body with the same size as the chip. After cutting, the chip particle size is small, ranging from a few millimeters to more than a dozen millimeters. During the chip manufacturing process, various appearance defects will occur due to the reasons of the material itself and the process problems, mainly including poor solder balls, poor circuits, and poor resin protection layers, etc. The solder ball size on the chip is getting smaller and smaller, the circuits are getting more and more complex, and the line width is getting narrower and narrower; at the same time, the solder balls, circuit layers, and resin protection layers are located at different height levels. When focusing on multiple height targets at the same time, it is easy to miss detections. All in all, the complex structure and small size of the chip make it difficult for the naked eye to find the defects on it.

[0003] At present, WLCSP chip packaging factories basically use the method of manual visual inspection under a microscope for appearance defect detection. Due to the large number of products, the manual detection efficiency is very low, and the human eye is prone to fatigue and is easily affected by external interference factors, so the detection effect is unstable, and it is very difficult to control the missed detection rate. Therefore, it is becoming more and more important to use machine vision technology to replace the human eye and brain to achieve automatic appearance defect detection. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems existing in the prior art, and provide a method and a detection system for detecting appearance defects of wafer-level packaged chips, which can more effectively detect target defects through the combination of imaging technology and algorithms, and avoid missed detections.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is:

[0006] The present invention provides a method for detecting appearance defects of wafer-level packaged chips, including the following steps:

[0007] Step S1: Load the chip product design drawing in CAD software, and at the same time select a representative chip good image. After fusing the two images and locally correcting them, a standard template is obtained; and using the drawing layer function of CAD software, the standard template is segmented into several regional image templates according to different functions.

[0008] Separate images of the chip on the tray are taken by a camera under the illumination of a high-angle annular light source and a low-angle annular light source respectively; the two separately taken images are synthesized into a new image of the chip on the tray by setting a weight ratio.

[0009] Specifically, the high-angle annular light source illuminates the top of the upper half of the solder ball, and the low-angle annular light source illuminates the bottom of the upper half of the solder ball. The images of the two separate imagings are synthesized together through an algorithm to obtain the complete three-dimensional information of the upper half of the solder ball, and the defects of the solder ball are effectively detected by comparing with good products.

[0010] The high-angle annular light source cooperates with the camera to clearly image the two-dimensional defects of the chip, and the low-angle annular light source cooperates with the camera to clearly image the three-dimensional defects of the chip. The two-dimensional defects are short circuits, open circuits, etc., and the three-dimensional defects are scratches, resin protective layer breakage, etc. The combined use of the two groups of light sources realizes clear imaging of various defects on the chip. The detection of a specific defect must be comprehensively processed by combining the characteristic information of the two images.

[0011] The optical imaging system consists of a high-angle infrared annular light source, a low-angle infrared annular light source, and an industrial line array camera. The industrial line array camera separately images the chip under test under the two light sources, and then processes the two images to achieve detection.

[0012] [[ID=ll]]Step S2: The imaging system inputs the image of the whole tray of the tray chips, and divides the individual areas of each chip in the whole tray through a template matching algorithm to obtain the chip images in each individual area. Perform a first-level detection on each chip image. The first-level detection detects the abnormal placement of the chip through a set algorithm, such as the chip being upside down, the chip being missing, and the chip being skewed. If the placement is abnormal, prompt the operator to intervene for correction, otherwise enter the next detection process;

[0013] Step S3: According to several regional image templates, extract the corresponding regional images from each chip image respectively, and process different regional images with different second-level algorithms;

[0014] Specifically, the regional image templates include a circuit area image template, a solder ball area image template, and a protection area image template; use a second-level traditional vision algorithm to process the circuit area image template and the solder ball area image template, match them with the corresponding areas of the actual chip image, and detect structural defects through comparison; use a second-level AI algorithm to process the protection area image template. By collecting a large number of images of various types of defects and making corresponding defect annotations, customize and design an AI algorithm model, input the annotated image data into the AI algorithm model, and gradually optimize the model through training and parameter adjustment to achieve the detection result of non-structural defects.

[0015] It should be pointed out that the imaging scheme in step S1 of the present invention and the algorithm in step S3 do not exist independently, but support and cooperate with each other to jointly achieve more effective detection of target defects. Specifically, by independently imaging the chip through high- and low-angle light sources, the different heights of the chip show different brightness, which facilitates the extraction of solder ball area, circuit area and protection area images at different heights from each chip image, so that corresponding algorithms can be used for processing different areas.

[0016] Step S4: Summarize the detection results of each second-level algorithm to obtain the detection result output of a single chip, obtain the detection result of each chip through cyclic detection and summarize it to obtain the result output of the entire tray chip.

[0017] The improvements and corresponding advantages of the above scheme are:

[0018] First, the unique high- and low-angle infrared ring light source time-sharing imaging lighting solution solves the problem of clearly imaging different types of defects in areas with different height differences on the chip, and solves the problem of clear imaging of the metal circuit layer under the resin layer.

[0019] Secondly, the imaging solution and algorithm do not exist independently, but support and cooperate with each other to achieve more effective detection of target defects. Specifically, by illuminating the chip with high and low angle light sources respectively, the chip presents different brightness levels at different heights, making it convenient to extract the solder ball area, circuit area and protection area images at different heights from each chip image, so that the corresponding algorithms can be used for processing in different areas, achieving more accurate chip detection result output.

[0020] Third, a two-level detection algorithm framework is adopted to divert abnormal and normal detection; a parallel two-layer algorithm is adopted, using traditional visual inspection algorithms and AI algorithms to detect chip structural defects and non-structural defects respectively, and then the information is merged to complete the detection of the entire chip.

[0021] Furthermore, the image of the standard template is combined with the image of a single good chip from the same batch with the same feature anchor point. The feature anchor point is used as the positioning point. After aligning the two images, the detailed pixel-level differences are ignored, and the large structural differences between the two are compared. The two are subjected to set logical operations based on the structural features to obtain a composite template, and the composite template is used as the standard template for the next step.

[0022] The advantage lies in that the algorithm adopts two special algorithms: composite template creation and composite image processing. The correction template is formed through CAD drawings and actual good product images. Through the synthetic analysis of high and low angle images, more effective detection of targets is achieved and the over-inspection rate is reduced.

[0023] The present invention provides a system for detecting appearance defects of wafer-level packaged chips, comprising: a conveying mechanism, an optical detection device, a main controller, a picking position, a picking and replenishing mechanism, a defective material tray position, and a replenishing position;

[0024] Multiple whole trays of tray chips are successively unloaded and conveyed to the optical detection device. The optical detection device separately images the tray chips under the irradiation of a high-angle annular light source and a low-angle annular light source. The main controller detects and outputs the detection results of the tray chips according to the detection method of claim 1;

[0025] Then the whole tray of the tray chips is conveyed to the picking position. The picking and replenishing mechanism removes defective materials and places the defective materials at the defective material tray position. The tray chips with defective materials removed are conveyed to the replenishing position;

[0026] The picking and replenishing mechanism replenishes the good products of the tray chips into the empty positions of the next tray from which defective materials are picked at the picking position, obtaining a full tray of good product chips, thereby realizing the sorting of good products and defective materials.

[0027] The above solution effectively realizes the effective detection of various defects on such chips and automatic sorting by integrating a specially designed optical detection device, an automatic sorting system, customized detection software, and detection algorithms.

[0028] Compared with the prior art, the beneficial effects of the present invention are:

[0029] 1. Adopting a unique lighting scheme of time-sharing imaging with high and low-angle infrared annular light sources, it solves the problem that different types of defects in areas with different height differences on the chip can be clearly imaged, and solves the problem of clear imaging of the metal wiring layer covered by the resin layer;

[0030] 2. The imaging scheme and algorithm do not exist independently, but support and cooperate with each other to jointly achieve more effective detection of target defects. Specifically, by separately irradiating the chip with high and low-angle light sources for independent imaging, different heights of the chip present different brightness levels, which is convenient for separately extracting the solder ball area, wiring area, and protection area images of different heights from each chip image, so as to use corresponding algorithms for processing in different regions, avoiding missed detection and realizing more accurate detection result output of the chip;

[0031] 3. Adopting a two-stage detection algorithm framework to divert abnormal and normal detections; adopting a parallel double-layer algorithm, respectively using traditional vision detection algorithms and AI algorithms to separately detect the structural defects and non-structural defects of the chip, and then merging the information to complete the detection of the entire chip;

[0032] 4. Two special algorithms, namely composite template creation and composite image processing, are adopted in the algorithm. A correction template is formed through CAD drawings and actual good product images. Through the synthetic analysis of two images at high and low angles, more effective detection of the target and reduction of the over-detection rate are achieved.

[0033] 5. By integrating a specially designed optical detection device, an automated sorting system, customized detection software, and detection algorithms, effective detection of various defects on such chips and automated sorting are effectively achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic flowchart of a method for detecting appearance defects of a wafer-level packaged chip according to the present invention;

[0035] Figure 2 It is a schematic structural diagram of the optical imaging system according to the present invention;

[0036] Figure 3 It is a top view of a system for detecting appearance defects of a wafer-level packaged chip according to the present invention;

[0037] In the figure: 1. High-angle infrared ring light source; 2. Low-angle infrared ring light source; 3. Industrial line array camera; 4. Chip to be measured; 5. Loading mechanism; 6. Optical detection device; 7. Picking position; 8. Picking and replenishing mechanism; 9. Bad material tray position; 10. Replenishing position; 11. Good product tray bin; 12. Empty tray bin. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] Hereinafter, the technical solutions of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

[0039] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "top", "bottom", "inner", "outer", "horizontal", "vertical", etc. are all based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0040] Embodiment 1

[0041] As Figure 1 shown, the present invention provides a method for detecting appearance defects of a wafer-level packaged chip, including the following steps:

[0042] Step S1: Load the chip product design drawing in CAD software, and at the same time select representative images of good chip products. After fusing the two images and making local corrections, a standard template is obtained. And using the drawing layering function of CAD software, the standard template is divided into several regional image templates according to different functions.

[0043] Under the illumination of a high-angle ring light source and a low-angle ring light source, use a camera to image the tray chips separately; synthesize the images of the two separate imagings into a new tray chip image by setting a weight ratio.

[0044] Specifically, the high-angle ring light source lights up the top of the upper half of the solder ball, and the low-angle ring light source lights up the bottom of the upper half of the solder ball. The images of the two separate imagings are synthesized together through an algorithm to obtain the three-dimensional complete information of the upper half of the solder ball, and the solder ball defects are effectively detected by comparing with good products.

[0045] The high-angle ring light source cooperates with the camera to clearly image the two-dimensional defects of the chip, and the low-angle ring light source cooperates with the camera to clearly image the three-dimensional defects of the chip. Among them, the two-dimensional defects are short circuits, open circuits, etc., and the three-dimensional defects are scratches, resin protection layer breakage, etc. The combined use of the two groups of light sources realizes the clear imaging of various defects on the chip. The detection of a specific defect must be comprehensively processed by combining the characteristic information of the two images.

[0046] As Figure 2 shown, the optical imaging system consists of a high-angle infrared ring light source 1, a low-angle infrared ring light source 2, and an industrial line array camera 3. The industrial line array camera 3 images the chip 4 to be measured separately under the two light sources, and then processes the two images to realize detection.

[0047] Step S2: The imaging system inputs the image of the entire tray of the tray chips, and uses a template matching algorithm to divide the individual areas of each chip in the entire tray, obtains the chip images in each individual area, and performs a first-level detection on each chip image. The first-level detection uses a set algorithm to detect the abnormal placement of the chip, such as the chip being upside down, the chip being missing, and the chip being skewed. If the placement is abnormal, prompt the operator to intervene for correction, otherwise enter the next detection process.

[0048] Step S3: According to several regional image templates, extract the corresponding regional images from each chip image respectively, and process different regional images using different second-level algorithms.

[0049] Specifically, the regional image templates include circuit area image templates, solder ball area image templates and protection area image templates; the second-level traditional visual algorithm is used to process the circuit area image templates and the solder ball area image templates, and match them with the corresponding areas of the actual chip image. By comparison, structural defects are detected; the second-level AI algorithm is used to process the protection area image templates, and a large number of images of various types of defects are collected and corresponding defect annotations are made. A customized AI algorithm model is designed, and the annotated image data is input into the AI algorithm model. Through training and parameter adjustment, the model is gradually optimized to achieve the detection results of non-structural defects.

[0050] It should be pointed out that the imaging scheme in step S1 of the present invention and the algorithm in step S3 do not exist independently, but support and cooperate with each other to jointly achieve more effective detection of target defects. Specifically, by independently imaging the chip with high and low angle light sources, the different heights of the chip show different brightness, which facilitates the extraction of solder ball area, circuit area and protection area images at different heights from each chip image, so that corresponding algorithms can be used for processing different areas to avoid missed detection.

[0051] Step S4: Summarize the detection results of each second-level algorithm to obtain the detection result output of a single chip, obtain the detection result of each chip through cyclic detection and summarize it to obtain the result output of the entire tray chip.

[0052] The improvement and corresponding advantages of the above scheme are

[0053] First, the unique high- and low-angle infrared ring light source time-sharing imaging lighting solution solves the problem of clearly imaging different types of defects in areas with different height differences on the chip, and solves the problem of clear imaging of the metal circuit layer under the resin layer.

[0054] Secondly, the imaging solution and algorithm do not exist independently, but support and cooperate with each other to achieve more effective detection of target defects. Specifically, by illuminating the chip with high and low angle light sources respectively, the chip presents different brightness levels at different heights, making it convenient to extract the solder ball area, circuit area and protection area images at different heights from each chip image, so that the corresponding algorithms can be used for processing different areas to avoid missed detections and achieve more accurate chip detection result output.

[0055] Third, a two-level detection algorithm framework is adopted to divert abnormal and normal detection; a parallel two-layer algorithm is adopted, using traditional visual inspection algorithms and AI algorithms to detect chip structural defects and non-structural defects respectively, and then the information is merged to complete the detection of the entire chip.

[0056] Example 2

[0057] The difference between this embodiment and Embodiment 1 is that, by combining the image of the standard template and the image of a single good chip with the same characteristic anchor points in the same batch, using the characteristic anchor points as positioning points, after aligning the two images, ignoring the pixel-level differences in details, comparing the large structural differences between the two, performing a set logical operation on the two according to the structural characteristics to obtain a composite template, and using the composite template as the next standard template.

[0058] The advantages are that two special algorithms, namely composite template creation and composite image processing, are adopted in the algorithm. A corrected template is formed through CAD drawings and actual good product images, and through the synthetic analysis of two images at high and low angles, more effective detection of the target and reduction of the over-detection rate are achieved.

[0059] Embodiment 3

[0060] As Figure 3 shown, the present invention provides a wafer-level packaged chip appearance defect detection system, including: a loading mechanism 5, a conveying mechanism, an optical detection device 6, a main controller, a picking position 7, a picking and replenishing mechanism 8, a defective product tray position 9, a replenishing position 10, a good product tray bin 11, and an empty tray bin 12;

[0061] Multiple whole trays of tray chips are sequentially unloaded and transported to the optical detection device 6. The optical detection device 6 separately images the tray chips under the irradiation of a high-angle annular light source and a low-angle annular light source, and the main controller outputs the detection results of the tray chips according to the detection method of Claim 1;

[0062] Then the whole tray of the tray chips is transported to the picking position 7. The picking and replenishing mechanism 8 removes the defective products and places the defective products at the defective product tray position 9. The tray chips with defective products removed are transported to the replenishing position 10;

[0063] The picking and replenishing mechanism 8 replenishes the good products of the tray chips into the empty positions of the next tray from which defective products are picked at the picking position, obtaining a full tray of good chips, and realizing the sorting of good products and defective products.

[0064] The above solution effectively realizes the effective detection of various defects on such chips and automatic sorting by integrating a specially designed optical detection device, an automatic sorting system, a customized detection software, and a detection algorithm.

[0065] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for detecting appearance defects of wafer-level packaged chips, characterized in that, The following steps are involved: S1. Create a standard template for a single chip product, and divide the standard template into several regional image templates according to different functional areas; Using a camera to separately image the tray chip under the illumination of a high-angle ring light source and a low-angle ring light source; synthesizing the two separately imaged images into a new tray chip image by setting a weight ratio; S2. The imaging system inputs the image of the entire tray of chips, segments each chip in the tray into a separate area using a template matching algorithm, obtains the chip image in each separate area, and performs a first-level inspection on each chip image. The first-level inspection uses a set algorithm to detect abnormal chip placement. If the placement is abnormal, the operator is prompted to intervene and make corrections. Otherwise, the inspection process proceeds to the next step. S3. Extract corresponding regional images from each chip image based on several regional image templates, and use different second-level algorithms for processing different regional images; the regional image templates include circuit area image templates, solder ball area image templates, and protection area image templates; use the second-level traditional visual algorithm to process the circuit area image templates and solder ball area image templates, match them with the corresponding areas of the actual chip image, and detect structural defects through comparison; use the second-level AI algorithm to process the protection area image templates, collect a large number of images of various types of defects and make corresponding defect annotations, customize and design an AI algorithm model, input the annotated image data into the AI algorithm model, and gradually optimize the model through training and parameter adjustment to obtain detection results for non-structural defects; S4. Summarize the detection results of each second-level algorithm to obtain the detection result output of a single chip. Obtain the detection result of each chip through cyclic detection and summarize it to obtain the result output of the entire tray chip.

2. The method for detecting appearance defects of a wafer-level packaged chip according to claim 1, wherein The step S1 specifically includes loading the chip product design drawing through the software, selecting a representative chip good product image, fusing the two images and performing local correction to obtain a standard template; and using the drawing layering function of the software to divide the standard template into several regional image templates according to different functional areas.

3. The method for detecting appearance defects of a wafer-level packaged chip according to claim 2, characterized in that, Combine the image of the standard template with the image of a single good chip from the same batch with the same feature anchor point. Use the feature anchor point as the positioning point. After aligning the two images, ignore the detailed pixel-level differences, compare the structural differences between the two, and perform set logic operations on the two according to the structural features to obtain a composite template. Use the composite template as the standard template for the next step.

4. A method for detecting appearance defects of a wafer-level packaged chip according to claim 1, characterized in that, The abnormal arrangement includes the chip being inverted, the chip being missing, and the chip being skewed.

5. A method for detecting appearance defects of a wafer-level packaged chip according to claim 1, characterized in that, The high-angle ring light source illuminates the top of the upper half of the solder ball, and the low-angle ring light source illuminates the bottom of the upper half of the solder ball. The two independently imaged images are synthesized together through an algorithm to obtain complete three-dimensional information of the upper half of the solder ball, and effective detection of solder ball defects is achieved by comparing with good products.

6. A method for detecting appearance defects of a wafer-level packaged chip according to claim 1, characterized in that, The high-angle annular light source cooperates with the camera to clearly image the two-dimensional defects of the chip, and the low-angle annular light source cooperates with the camera to clearly image the three-dimensional defects of the chip.

7. A wafer-level packaged chip appearance defect detection system, characterized in that, include: Transport mechanism, optical detection device (6), main controller, picking position (7), picking and replenishing mechanism (8), defective material tray position (9) and replenishing position (10); Multiple full trays of tray chips are successively unloaded and transported to the optical detection device (6). The optical detection device (6) separately images the tray chips individually under the illumination of a high-angle annular light source and a low-angle annular light source. The main controller detects and outputs the detection results of the full trays of tray chips according to the detection method described in claim 1; Then the full trays of the tray chips are transported to the picking position (7). The picking and replenishing mechanism (8) removes defective materials and places the defective materials at the defective material tray position (9). The full trays of the tray chips with defective materials removed are transported to the replenishing position (10); The picking and replenishing mechanism (8) replenishes the good products of the tray chips into the empty spaces of the next tray from which defective materials are picked at the picking position, obtaining full trays of good product chips and realizing the sorting of good products and defective materials.

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