Low Dropout Regulators

Abstract

The present disclosure relates to a low-dropout voltage regulator. The low-dropout voltage regulator includes: a comparator for comparing a feedback voltage with a reference voltage to output a comparison signal corresponding to the comparison result to a control node; an internal voltage generator coupled to the control node and generating a feedback voltage and an internal voltage based on the comparison signal; and a controller coupled to the control node and monitoring the internal voltage based on the comparison signal, and controlling the voltage level of the comparison signal according to the monitoring result.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0036141 filed on Mar. 19, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly to low dropout regulators. Background Art

[0004] Semiconductor devices are capable of generating and using an internal voltage having a relatively lower level than a power supply voltage. For example, such semiconductor devices may include a low dropout regulator as a circuit for generating the internal voltage. In order for the semiconductor device to operate normally, it is important to accurately monitor the internal voltage. Summary of the invention

[0005] Various embodiments of the present disclosure relate to a low dropout regulator capable of generating a stable internal voltage through a monitoring operation.

[0006] According to one embodiment, a low dropout regulator may include: a comparator, adapted to compare a feedback voltage with a reference voltage to output a comparison signal corresponding to a comparison result to a control node; an internal voltage generator, coupled to the control node and adapted to generate a feedback voltage and an internal voltage based on the comparison signal; and a controller, coupled to the control node and adapted to monitor the internal voltage based on the comparison signal, and to control a voltage level of the comparison signal according to the monitoring result.

[0007] The controller may be adapted to monitor a load current flowing through an output node of the internal voltage based on the comparison signal, and suppress undershoot and overshoot of the internal voltage according to the monitoring result.

[0008] The controller may be adapted to suppress an undershoot of the internal voltage when the monitoring result satisfies a first condition, and suppress an overshoot of the internal voltage when the monitoring result satisfies a second condition.

[0009] The first condition may be a case where the load current is higher than a first threshold level when the load current changes from a target level to a peak level, and the second condition may be a case where the load current is lower than a second threshold level when the load current changes from a peak level to a target level.

[0010] The second threshold level may be higher than the first threshold level.

[0011] According to one embodiment, a low dropout regulator may include: a comparator, adapted to compare a feedback voltage with a reference voltage to generate a comparison signal corresponding to a comparison result; an internal voltage generator, adapted to generate a feedback voltage and an internal voltage based on the comparison signal; a monitoring circuit, adapted to monitor a load current flowing through an output node of the internal voltage generator based on the comparison signal, a first inhibition signal, and a second inhibition signal to generate a monitoring signal corresponding to the monitoring result; an inhibition signal generating circuit, adapted to generate a first inhibition signal for inhibiting an undershoot of the internal voltage based on the monitoring signal when the monitoring result satisfies a first condition, and to generate a second inhibition signal for inhibiting an overshoot of the internal voltage when the monitoring result satisfies a second condition; and a control circuit, adapted to control a voltage level of the comparison signal based on the first inhibition signal and the second inhibition signal.

[0012] The first condition may be a case where the load current is higher than a first threshold level when the load current changes from a target level to a peak level, and the second condition may be a case where the load current is lower than a second threshold level when the load current changes from a peak level to a target level.

[0013] The second threshold level may be higher than the first threshold level.

[0014] According to one embodiment, a low dropout regulator may include: a voltage generator adapted to generate an output voltage corresponding to an input voltage and to generate a control signal corresponding to a voltage level of the output voltage; and a controller adapted to suppress undershoot and overshoot of the output voltage based on the control signal.

[0015] The controller may be adapted to monitor a load current flowing through an output node of the output voltage based on the control signal, and suppress undershoot and overshoot of the output voltage according to the monitoring result.

[0016] The controller may be adapted to suppress an undershoot of the output voltage when the monitoring result satisfies a first condition, and suppress an overshoot of the output voltage when the monitoring result satisfies a second condition.

[0017] The first condition may be a case where the load current is higher than a first threshold level when the load current changes from a target level to a peak level, and the second condition may be a case where the load current is lower than a second threshold level when the load current changes from a peak level to a target level.

[0018] The second threshold level may be higher than the first threshold level.

[0019] In one embodiment, the voltage generator may include: a comparator adapted to compare a reference voltage with a feedback voltage to generate a control signal corresponding to the comparison result; and a generator adapted to generate the feedback voltage and the output voltage based on the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a block diagram illustrating a low dropout regulator according to one embodiment.

[0021] Figure 2 It is shown Figure 1 The circuit diagram of the internal voltage generator is shown.

[0022] Figure 3 It is shown Figure 1 The circuit diagram of the controller is shown.

[0023] Figure 4 It is shown Figure 3 The circuit diagram of the second sensing circuit is shown.

[0024] Figure 5 It is shown Figure 3 The circuit diagram of the suppression signal generating circuit is shown.

[0025] Figure 6 and Figure 7 It is shown Figure 1 A timing diagram of the operation of the low dropout regulator is shown. DETAILED DESCRIPTION

[0026] Various embodiments are described below with reference to the accompanying drawings in order to describe the present disclosure in detail so that those skilled in the art to which the present disclosure belongs can easily realize the technical spirit of the present disclosure.

[0027] It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, the component may be directly connected to or coupled to the other component, or may be electrically connected to or electrically coupled to the other component through one or more components interposed therebetween. In addition, it should be understood that, unless otherwise stated, the terms "include", "comprise", "include", "include" when used in this specification do not exclude the presence of one or more other components, but may also include or have one or more other components. In the description throughout the specification, some components are described in the singular, but the present disclosure is not limited thereto, and it should be understood that these components may be formed in plurality.

[0028] Figure 1 is a block diagram showing a low dropout regulator 10 according to an embodiment.

[0029] Reference Figure 1 , the low dropout regulator 10 may include an internal voltage generator 100 and a controller 200 .

[0030] The internal voltage generator 100 may receive a reference voltage VREF as an input voltage and generate an internal voltage VOUT as an output voltage. The internal voltage generator 100 may generate an internal voltage VOUT corresponding to the reference voltage VREF. The internal voltage generator 100 may generate a control signal corresponding to the voltage level of the internal voltage VOUT. The control signal may refer to a comparison signal VPGATE to be described below.

[0031] The controller 200 may be coupled to a control node CN and an output node ON (these nodes are Figure 2 ). The control node CN may be a node to which the comparison signal VPGATE generated by the internal voltage generator 100 is output, and the output node ON may be a node to generate the internal voltage VOUT. The controller 200 may control the voltage level of the internal voltage VOUT based on the comparison signal VPGATE. In one embodiment, the controller 200 may monitor the load current IL flowing through the output node ON of the internal voltage VOUT based on the comparison signal VPGATE, and suppress the undershoot and overshoot of the internal voltage VOUT according to the monitoring result.

[0032] Figure 2 It is shown Figure 1 A circuit diagram of the internal voltage generator 100 is shown.

[0033] Reference Figure 2 , the internal voltage generator 100 may include a comparator 110 and a generator 120 .

[0034] The comparator 110 may compare the reference voltage VREF with the feedback voltage VFB and output a comparison signal VPGATE corresponding to the comparison result to the control node CN. For example, the comparator 110 may include an error amplifier.

[0035] The generator 120 may be coupled to the control node CN. The generator 120 may generate a feedback voltage VFB and an internal voltage VOUT based on the comparison signal VPGATE. In one embodiment, the generator 120 may include a driver 121 and a voltage divider 123.

[0036] The driver 121 may drive the output node ON of the internal voltage VOUT with the high voltage VDD based on the comparison signal VPGATE. In one embodiment, the driver 121 may include a first PMOS transistor PM0. The first PMOS transistor PM0 may have a gate terminal receiving the comparison signal VPGATE, and a source terminal and a drain terminal coupled between a power supply terminal of the high voltage VDD and the output node ON of the internal voltage VOUT.

[0037] In one implementation, the voltage divider 123 may divide the internal voltage VOUT at a predetermined ratio and generate a feedback voltage VFB. The voltage divider 123 may include a first resistor R0 and a second resistor R1.

[0038] The first resistor R0 may be coupled between an output node ON of the internal voltage VOUT and an output node of the feedback voltage VFB.

[0039] The second resistor R1 may be coupled between an output node of the feedback voltage VFB and a power supply terminal of the low voltage VSS.

[0040] Figure 3 It is shown Figure 1 A circuit diagram of the controller 200 is shown.

[0041] Reference Figure 3 , the controller 200 may include a monitoring circuit 210 , a suppression signal generating circuit 220 , and a control circuit 230 .

[0042] The monitoring circuit 210 can monitor the load current IL flowing through the output node ON of the internal voltage VOUT based on the comparison signal VPGATE, the first inhibition signal VONESHOT_N and the second inhibition signal VONESHOT_P, and generate a monitoring signal VCTRL corresponding to the monitoring result. In one embodiment, the monitoring circuit 210 may include a first sensing circuit 211, a second sensing circuit 213 and a third sensing circuit 215.

[0043] The first sensing circuit 211 may generate a sensing current IS corresponding to the load current IL based on the comparison signal VPGATE. The first sensing circuit 211 may generate the sensing current IS by mirroring the load current IL. The first sensing circuit 211 may include a second PMOS transistor PM1. The second PMOS transistor PM1 may have a gate terminal receiving the comparison signal VPGATE and a source terminal and a drain terminal coupled between the first sensing node SN1 and the output node ON of the internal voltage VOUT. When the size of the first PMOS transistor PM0 is "M", the size of the second PMOS transistor PM1 may be "1". In one embodiment, the size of the second PMOS transistor PM1 may correspond to "1 / M" of the size of the first PMOS transistor PM0.

[0044] The second sensing circuit 213 may sense the level of the load current IL based on the sensing voltage V_SENSE corresponding to the sensing current IS, the first suppression signal VONESHOT_N, and the second suppression signal VONESHOT_P, and generate a sensing signal VI_LEV_H corresponding to the sensing result. In one embodiment, the second sensing circuit 213 may activate the sensing signal VI_LEV_H when the level of the load current IL satisfies a first condition, and deactivate the sensing signal VI_LEV_H when the level of the load current satisfies a second condition.

[0045] The third sensing circuit 215 may generate a monitoring signal VCTRL based on the sensing current IS and the sensing signal VI_LEV_H. In one embodiment, the third sensing circuit 215 may include a third resistor R2, a fourth resistor R3, mirror circuits PM2 and PM3, a first current source CS1, a first switch NM0, a second current source CS2, a third current source CS3, a second switch NM1, a fourth current source CS4, a third switch NM2, and a fifth current source CS5.

[0046] The third resistor R2 may be coupled between a power supply terminal of the high voltage VDD and the first sensing node SN1 .

[0047] The fourth resistor R3 may be coupled between a power supply terminal of the high voltage VDD and the first node N1. In one implementation, a resistance value of the fourth resistor R3 may correspond to "M" times a resistance value of the third resistor R2.

[0048] The mirror circuits PM2 and PM3 may be coupled between the first sensing node SN1, the first node N1, the second node N2, and the third node N3. In one embodiment, the mirror circuits PM2 and PM3 may include a third PMOS transistor PM2 and a fourth PMOS transistor PM3. The third PMOS transistor PM2 may have a gate terminal and a drain terminal coupled to the gate terminal, and a source terminal and a drain terminal coupled between the first sensing node SN1 and the second node N2. The fourth PMOS transistor PM3 may have a gate terminal coupled to the gate terminal of the third PMOS transistor PM2, and a source terminal and a drain terminal coupled between the first node N1 and the third node N3.

[0049] The first current source CS1 may be coupled between the second node N2 and a power terminal of the low voltage VSS. The first current source CS1 may generate a first reference current IR1.

[0050] The first switch NM0 may be coupled between the second node N2 and the fourth node N4. The first switch NM0 may be controlled by the sensing signal VI_LEV_H. The first switch NM0 may include a first NMOS transistor. The first NMOS transistor may have a gate terminal receiving the sensing signal VI_LEV_H, and a source terminal and a drain terminal coupled between the second node N2 and the fourth node N4.

[0051] The second current source CS2 may be coupled between the fourth node N4 and a power terminal of the low voltage VSS. The second current source CS2 may generate a second reference current IR2.

[0052] The third current source CS3 may be coupled between the third node N3 and a power terminal of the low voltage VSS. The third current source CS3 may generate a first reference current IR1.

[0053] The second switch NM1 may be coupled between the third node N3 and the fifth node N5. The second switch NM1 may be controlled by the sensing signal VI_LEV_H. The second switch NM1 may include a second NMOS transistor. The second NMOS transistor may have a gate terminal receiving the sensing signal VI_LEV_H, and a source terminal and a drain terminal coupled between the third node N3 and the fifth node N5.

[0054] The fourth current source CS4 may be coupled between the fifth node N5 and a power terminal of the low voltage VSS. The fourth current source CS4 may generate a second reference current IR2.

[0055] The third switch NM2 may be coupled between the second sensing node SN2 to which the monitoring signal VCTRL is output and the power supply terminal of the low voltage VSS. The third switch NM2 may be controlled by a voltage applied to the third node N3. The third switch NM2 may include a third NMOS transistor. The third NMOS transistor may have a gate terminal coupled to the third node N3, and a source terminal and a drain terminal coupled between the second sensing node SN2 and the power supply terminal of the low voltage VSS.

[0056] The fifth current source CS5 may be coupled between a power terminal of the high voltage VDD and the second sensing node SN2 The fifth current source CS5 may generate a third reference current IR3.

[0057] The suppression signal generating circuit 220 may generate a first suppression signal VONESHOT_N for suppressing the undershoot of the internal voltage VOUT when the monitoring result satisfies a first condition based on the monitoring signal VCTRL, and generate a second suppression signal VONESHOT_P for suppressing the overshoot of the internal voltage VOUT when the monitoring result satisfies a second condition. The first condition may be a case where the load current is higher than a first threshold level when the load current changes from a target level to a peak level. The second condition may be a case where the load current is lower than a second threshold level when the load current changes from a peak level to a target level.

[0058] The control circuit 230 may control the voltage level of the comparison signal VPGATE based on the first suppression signal VONESHOT_N and the second suppression signal VONESHOT_P. The control circuit 230 may reduce the voltage level of the comparison signal VPGATE based on the first suppression signal VONESHOT_N, and increase the voltage level of the comparison signal VPGATE based on the second suppression signal VONESHOT_P. The control circuit 230 may include a first driver NM3 and a second driver PM4.

[0059] The first driver NM3 may drive the control node CN to which the comparison signal VPGATE is outputted with the pull-down voltage VREFN based on the first suppression signal VONESHOT_N. The first driver NM3 may include a fourth NMOS transistor. The fourth NMOS transistor may have a gate terminal receiving the first suppression signal VONESHOT_N, and a source terminal and a drain terminal coupled between the control node CN and a power supply terminal of the pull-down voltage VREFN.

[0060] The second driver PM4 may drive the control node CN with the pull-up voltage VREFP based on the second inhibition signal VONESHOT_P. The second driver PM4 may include a fifth PMOS transistor. The fifth PMOS transistor may have a gate terminal receiving the second inhibition signal VONESHOT_P, and a source terminal and a drain terminal coupled between the control node CN and a power supply terminal of the pull-up voltage VREFP.

[0061] Figure 4 It is shown Figure 3 FIG. 2 is a circuit diagram of the second sensing circuit 213 shown in FIG.

[0062] Reference Figure 4 , the second sensing circuit 213 may include a first circuit DFF1 , a second circuit AMP1 , and a third circuit AND1 .

[0063] The first circuit DFF1 may generate a first condition check signal EN based on the first suppression signal VONESHOT_N and the second suppression signal VONESHOT_P. The first circuit DFF1 may include a D flip-flop. The D flip-flop may receive a high voltage VDD through its input terminal D, receive the first suppression signal VONESHOT_N through its clock terminal CLK, receive the second suppression signal VONESHOT_P through its reset terminal RESET, and output the first condition check signal EN through its output terminal Q.

[0064] The second circuit AMP1 may compare the sensing voltage V_SENSE with a predetermined voltage VR and generate a second condition check signal EN_I_HIGH corresponding to the comparison result. The predetermined voltage VR may be a reference voltage having a constant voltage level. For example, the second circuit AMP1 may include a differential amplifier.

[0065] The third circuit AND1 may generate a sensing signal VI_LEV_H based on the first condition check signal EN and the second condition check signal EN_I_HIGH. The third circuit AND1 may continuously deactivate the sensing signal VI_LEV_H according to the second condition check signal EN_I_HIGH regardless of the first condition check signal EN. The third circuit AND1 may include an AND gate.

[0066] The second sensing circuit 213 may further include at least one of a first buffer BF1 and a second buffer BF2 according to design. Each of the first buffer BF1 and the second buffer BF2 may be associated with a delay time.

[0067] Figure 5 It is shown Figure 3 A circuit diagram of the suppression signal generating circuit 220 is shown.

[0068] Reference Figure 5 , the suppression signal generating circuit 220 may include a delay circuit 221 , a first logic circuit 223 , and a second logic circuit 225 .

[0069] The delay circuit 221 may delay the monitoring signal VCTRL by a predetermined delay time and generate a delayed monitoring signal VCTRL_DLY The delay circuit 221 may include a first inverter INV1, a fifth resistor R5, and a first capacitor C1.

[0070] The first logic circuit 223 may generate a first suppression signal VONESHOT_N based on the monitoring signal VCTRL and the delay monitoring signal VCTRL_DLY. The first logic circuit 223 may include a first NOR circuit NOR1.

[0071] The second logic circuit 225 may generate a second inhibiting signal VONESHOT_P based on the monitoring signal VCTRL, the delay monitoring signal VCTRL_DLY, and the second condition check signal EN_I_HIGH. The second logic circuit 225 may continuously deactivate the second inhibiting signal VONESHOT_P regardless of the monitoring signal VCTRL and the delay monitoring signal VCTRL_DLY according to the second condition check signal EN_I_HIGH. The second logic circuit 225 may include a second AND gate AND2 and a second inverter INV2.

[0072] In the following, reference Figure 6 and Figure 7 The operation of the low dropout regulator 10 having the above-described configuration according to one embodiment will be described.

[0073] Figure 6 is a timing diagram showing the operation of the low dropout regulator 10 .

[0074] Reference Figure 6 , internal voltage generator 100( Figure 1 ) can be turned on by the output node (also Figure 1 ) generates an internal voltage VOUT corresponding to the reference voltage VREF. The controller 200 (also shown in Figure 1 ) can monitor the load current IL flowing through the output node ON in real time and suppress undershoot and overshoot occurring in the internal voltage VOUT. The operation of the controller 200 is described in more detail below.

[0075] First, the operation of the controller 200 according to undershoot is described.

[0076] When the first sensing circuit 211 generates a sensing current IS corresponding to the load current IL based on the comparison signal VPGATE, the third sensing circuit 215 can monitor the sensing current IS based on the sensing current IS and the sensing signal VI_LEV_H, and generate a monitoring signal VCTRL corresponding to the monitoring result. The third sensing circuit 215 can generate a monitoring signal VCTRL having a logic low level when the monitoring result satisfies a first condition. The first condition may be a case where the load current IL is higher than the first threshold level IT1 when the load current IL changes from a target level to a peak level. The first threshold level IT1, the load current IL, and the sensing current IS are shown in the following equations 1 to 5.

[0077] [Equation 1]

[0078] IT1=IS=IL / M

[0079] [Equation 2]

[0080] IS*R2V=IR1*(M*R3V)

[0081] [Equation 3]

[0082] IS=M*IR1

[0083] [Equation 4]

[0084] IT1=M*IR1

[0085] [Equation 5]

[0086] IL=M 2 *IR1

[0087] Here, “R2V” represents a resistance value of the third resistor R2 , “R3V” represents a resistance value of the fourth resistor R3 , and “M” represents a ratio between the sizes of the first PMOS transistor PM0 and the second PMOS transistor PM1 described above.

[0088] The suppression signal generating circuit 220 may activate the first suppression signal VONESHOT_N for suppressing an undershoot occurring in the internal voltage VOUT based on the monitoring signal VCTRL having a logic low level.

[0089] The control circuit 230 may lower the voltage level of the comparison signal VPGATE based on the activated first suppression signal VONESHOT_N.

[0090] Therefore, the undershoot of the internal voltage VOUT can be suppressed as Figure 6 0048 ] The minimum undershoot value is shown at the leftmost offset of the internal voltage VOUT at the top of , where the solid line representing the internal voltage VOUT is suppressed relative to the dashed line when no suppression occurs.

[0091] Next, the operation of the controller 200 according to the overshoot is described.

[0092] When the first sensing circuit 211 generates a sensing current IS corresponding to the load current IL based on the comparison signal VPGATE, the third sensing circuit 215 can monitor the sensing current IS based on the sensing current IS and the sensing signal VI_LEV_H, and generate a monitoring signal VCTRL corresponding to the monitoring result. The third sensing circuit 215 can generate a monitoring signal VCTRL having a logic high level when the monitoring result satisfies a second condition. The second condition may be a case where the load current IL is lower than the second threshold level IT2 when the load current IL changes from a peak level to a target level. The second threshold level IT2, the load current IL, and the sensing current IS are shown in the following equations 6 to 10.

[0093] [Equation 6]

[0094] IT2=IS=IL / M

[0095] [Equation 7]

[0096] IS*R2V=(IR1+IR2)*(M*R3V)

[0097] [Equation 8]

[0098] IS=M*(IR1+IR2)

[0099] [Equation 9]

[0100] IT1=M*(IR1+IR2)

[0101] [Equation 10]

[0102] IL=M 2 *(IR1+IR2)

[0103] The suppression signal generating circuit 220 may activate the second suppression signal VONESHOT_P for suppressing an overshoot occurring in the internal voltage VOUT based on the monitoring signal VCTRL having a logic high level.

[0104] The control circuit 230 may increase the voltage level of the comparison signal VPGATE based on the activated second suppression signal VONESHOT_P.

[0105] Therefore, the overshoot of the internal voltage VOUT can be suppressed as follows, for example Figure 6 The minimum overshoot value is shown at the rightmost offset of the internal voltage VOUT at the top of FIG. 5 , where the solid line representing the internal voltage VOUT is suppressed relative to the dotted line when no suppression occurs.

[0106] Figure 7 It is shown Figure 6 FIG. 1 is a timing diagram of the first suppression signal VONESHOT_N and the second suppression signal VONESHOT_P.

[0107] Reference Figure 7 , the first suppression signal VONESHOT_N may be generated based on the monitoring signal VCTRL and the delay monitoring signal VCTRL_DLY. When the monitoring signal VCTRL has a logic low level and the delay monitoring signal VCTRL_DLY has a logic low level, the first suppression signal VONESHOT_N may be activated to a logic high level.

[0108] The second inhibition signal VONESHOT_P can be generated based on the monitoring signal VCTRL, the delayed monitoring signal VCTRL_DLY and the second condition check signal EN_I_HIGH (not shown). When the monitoring signal VCTRL has a logic high level, the delayed monitoring signal VCTRL_DLY has a logic high level and the second condition check signal EN_I_HIGH has a logic high level, the second inhibition signal VONESHOT_P can be activated to a logic low level. For reference, when the load current IL does not exceed the second threshold level IT2 (i.e., the second condition is not met), the second condition check signal EN_I_HIGH can maintain a logic low level. Therefore, the second inhibition signal VONESHOT_P can maintain a logic high level (i.e., a deactivated state) regardless of the logic levels of the monitoring signal VCTRL and the delayed monitoring signal VCTRL_DLY.

[0109] According to one embodiment, since undershoot is suppressed according to the first condition and overshoot is suppressed according to the second condition, a stable internal voltage may be generated.

[0110] According to one embodiment, since a stably generated internal voltage is used, the operational reliability of a low dropout regulator may be improved.

[0111] Although the present disclosure is shown and described with respect to specific embodiments, the disclosed embodiments are provided for illustrative purposes and are not intended to be limiting. In addition, it should be noted that, as will be appreciated by those skilled in the art from the present disclosure, the present disclosure can be implemented in various ways by substitutions, changes and modifications falling within the scope of the appended claims.

Claims

1. A low dropout voltage regulator, comprising: a comparator adapted to compare the feedback voltage with the reference voltage to output a comparison signal corresponding to the comparison result to the control node; a generator coupled to the control node and adapted to generate the feedback voltage and an internal voltage based on the comparison signal; as well as a controller coupled to the control node and adapted to generate a sense current corresponding to a load current based on the comparison signal, the load current flowing through the output node of the internal voltage, monitor the load current based on the comparison signal, and control a voltage level of the comparison signal according to a monitoring result, Wherein, the controller comprises: a first sensing circuit adapted to generate the sensing current based on the comparison signal; a second sensing circuit adapted to sense the level of the load current based on the first suppression signal, the second suppression signal, and a sensing voltage corresponding to the sensing current to generate a sensing signal corresponding to the sensing result; and The third sensing circuit is adapted to generate a monitoring signal corresponding to the monitoring result based on the sensing signal and the sensing current.

2. The low dropout voltage regulator according to claim 1, wherein: The controller is adapted to suppress an undershoot of the internal voltage when the monitoring result satisfies a first condition, and suppress an overshoot of the internal voltage when the monitoring result satisfies a second condition.

3. The low dropout voltage regulator according to claim 2, wherein: The first condition is a case where the load current is higher than a first threshold level when the load current changes from a target level to a peak level, and The second condition is a case where the load current is lower than a second threshold level when the load current changes from the peak level to the target level.

4. The low dropout voltage regulator according to claim 3, wherein: The second threshold level is higher than the first threshold level.

5. A low dropout voltage regulator, comprising: a comparator adapted to compare the feedback voltage with a reference voltage to generate a comparison signal corresponding to a comparison result; an internal voltage generator adapted to generate the feedback voltage and an internal voltage based on the comparison signal; a monitoring circuit adapted to monitor a load current flowing through an output node of the internal voltage generator based on the comparison signal, the first inhibition signal and the second inhibition signal to generate a monitoring signal corresponding to a monitoring result; an inhibition signal generating circuit adapted to generate, based on the monitoring signal, the first inhibition signal for inhibiting an undershoot of the internal voltage when the monitoring result satisfies a first condition and to generate the second inhibition signal for inhibiting an overshoot of the internal voltage when the monitoring result satisfies a second condition; as well as A control circuit is adapted to control a voltage level of the comparison signal based on the first inhibition signal and the second inhibition signal.

6. The low dropout voltage regulator according to claim 5, wherein: The first condition is a case where the load current is higher than a first threshold level when the load current changes from a target level to a peak level, and The second condition is a case where the load current is lower than a second threshold level when the load current changes from the peak level to the target level.

7. The low dropout voltage regulator according to claim 6, wherein: The second threshold level is higher than the first threshold level.

8. The low dropout voltage regulator according to claim 5, wherein: The monitoring circuit comprises: a first sensing circuit adapted to generate a sensing current corresponding to the load current based on the comparison signal; a second sensing circuit adapted to sense the level of the load current based on the first inhibition signal, the second inhibition signal, and a sensing voltage corresponding to the sensing current to generate a sensing signal corresponding to a sensing result; and The third sensing circuit is adapted to generate the monitoring signal based on the sensing signal and the sensing current.

9. The low dropout voltage regulator according to claim 8, wherein: The first sensing circuit is adapted to mirror the load current to generate the sensing current.

10. The low dropout voltage regulator according to claim 8, wherein: The second sensing circuit comprises: a first circuit adapted to generate a first condition check signal based on the first inhibit signal and the second inhibit signal; a second circuit adapted to compare the sensed voltage with a predetermined voltage having a fixed voltage level to generate a second condition check signal corresponding to the comparison result; and A third circuit is adapted to generate the sensing signal based on the first condition check signal and the second condition check signal.

11. The low dropout voltage regulator according to claim 8, wherein: The third sensing circuit comprises: a first resistor coupled between a power supply terminal of a high voltage and a first sensing node to which the sensing voltage is applied; a second resistor coupled between the high voltage power supply terminal and the first node; a mirror circuit coupled between the first sensing node, the first node, the second node and the third node; a first current source coupled between the second node and a power supply terminal of a low voltage and adapted to generate a first reference current; a first switch coupled between the second node and a fourth node and controlled by the sensing signal; a second current source coupled between the fourth node and the power supply terminal of the low voltage and adapted to generate a second reference current; a third current source coupled between the third node and the power supply terminal of the low voltage and adapted to generate the first reference current; a second switch coupled between the third node and the fifth node and controlled by the sensing signal; a fourth current source coupled between the fifth node and the power supply terminal of the low voltage and adapted to generate the second reference current; a third switch coupled between the second sensing node to which the monitoring signal is output and the power supply terminal of the low voltage and controlled by a voltage applied to the third node; and A fifth current source is coupled between the power supply terminal of the high voltage and the second sensing node and is adapted to generate a third reference current.

12. The low dropout voltage regulator according to claim 10, wherein: The suppression signal generating circuit comprises: a delay circuit adapted to delay the monitoring signal by a predetermined delay time to generate a delayed monitoring signal; a first logic circuit adapted to generate the first inhibit signal based on the monitoring signal and the delayed monitoring signal; and A second logic circuit is adapted to generate the second inhibit signal based on the monitoring signal, the delayed monitoring signal and the second condition check signal.

13. The low dropout voltage regulator according to claim 5, wherein: The control circuit comprises: a first driver adapted to drive a control node with a pull-down voltage based on the first inhibit signal, wherein the comparison signal is output through the control node; and A second driver is adapted to drive the control node with a pull-up voltage based on the second inhibit signal.

14. A low dropout voltage regulator, comprising: an internal voltage generator adapted to generate an output voltage corresponding to an input voltage, and to generate a control signal corresponding to a voltage level of the output voltage; as well as a controller adapted to generate a sensing current corresponding to a load current based on the control signal, the load current flowing through an output node of the output voltage, and to suppress undershoot and overshoot of the output voltage according to a monitoring result, Wherein, the controller comprises: a first sensing circuit adapted to generate the sensing current based on the control signal; a second sensing circuit adapted to sense the level of the load current based on the first suppression signal, the second suppression signal, and a sensing voltage corresponding to the sensing current to generate a sensing signal corresponding to the sensing result; and The third sensing circuit is adapted to generate a monitoring signal based on the sensing signal and the sensing current.

15. The low dropout voltage regulator according to claim 14, wherein: The controller is adapted to suppress an undershoot of the output voltage when the monitoring result satisfies a first condition, and suppress an overshoot of the output voltage when the monitoring result satisfies a second condition.

16. The low dropout voltage regulator according to claim 15, wherein: The first condition is a case where the load current is higher than a first threshold level when the load current changes from a target level to a peak level, and The second condition is a case where the load current is lower than a second threshold level when the load current changes from the peak level to the target level.

17. The low dropout voltage regulator according to claim 16, wherein: The second threshold level is higher than the first threshold level.

18. The low dropout voltage regulator according to claim 14, wherein: The internal voltage generator comprises: a comparator adapted to compare a reference voltage with a feedback voltage to generate the control signal corresponding to the comparison result; and A generator is adapted to generate the feedback voltage and the output voltage based on the control signal.

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