Timing adjustment method and apparatus, storage medium, and electronic device

Abstract

The application discloses a timing adjustment method and device, a storage medium and an electronic device. The method comprises the following steps: in response to a first read instruction, a sampling signal is generated, a data signal transmitted by N transmission circuits is sampled at a sampling edge of the sampling signal to obtain first sampling data, a transmission circuit with a timing offset is determined from the training data and the values of the same bits in the first sampling data, the transmission delay of the transmission circuit with the timing offset is adjusted until the center of the data signal transmitted by the transmission circuit with the timing offset is aligned with the sampling edge of the sampling signal. The application can be applied to the field of artificial intelligence, but is not limited thereto. The application solves the technical problem that the data signal and the sampling signal cannot be aligned in the related art, resulting in sampling error of read data.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a timing adjustment method and apparatus, a storage medium, and an electronic device. Background Technology

[0002] According to the HBM (High-Bandwidth Memory) protocol, HBM devices can achieve data read / write speeds of up to 3.6 GHz bit rates. At such high operating frequencies, data transmission is easily susceptible to errors due to noise interference on the data communication link or crosstalk between data lines. High-frequency data reading and transmission are also vulnerable to environmental changes during PVT (Process Verification Test) and crosstalk between signals, leading to offsets between read data and the sampled RDQS signal, resulting in read data sampling errors.

[0003] For example, when the HBM Host initiates a read operation to the HBM DRAM (Dynamic Random Access Memory), the HBM DRAM will return the read data to the HBM Host. Simultaneously, the HBM DRAM will also return an RDQS (Read DQ Strobe) signal to the HBM Host that matches the read data. The HBM Host will use this signal as the sampling signal for the read data; therefore, if the read data and the sampling RDQS signal are misaligned, it will lead to sampling errors in the read data.

[0004] When an error occurs while reading data from HBM DRAM, it will affect the correct execution of the entire HBM subsystem, and in severe cases, it may even affect the normal operation of the entire chip.

[0005] There is currently no effective solution to the above problems. Summary of the Invention

[0006] This application provides a timing adjustment method and apparatus, a storage medium and an electronic device to at least solve the technical problem in the related art where the data signal and the sampling signal cannot be aligned, resulting in incorrect data sampling.

[0007] According to one aspect of the embodiments of this application, a timing adjustment method is provided, comprising: generating a sampling signal in response to a first read instruction, wherein the first read instruction is used to read training data, wherein the training data is known data represented by N bits, where N is a positive integer greater than or equal to 2; sampling data signals transmitted on N transmission circuits at the sampling edge of the sampling signal to obtain first sampled data, wherein the N bits in the training data are transmitted as data signals on the N transmission circuits, and the first sampled data is data represented by N bits; determining the transmission circuits among the N transmission circuits that have timing offsets based on the values ​​of the same bits in the training data and the first sampled data; adjusting the transmission delay on the transmission circuits with timing offsets until the center of the data signal transmitted on the transmission circuits with timing offsets is aligned with the sampling edge of the sampling signal.

[0008] According to another aspect of the embodiments of this application, a timing adjustment apparatus is also provided, comprising: a generation module, configured to generate a sampling signal in response to a first read instruction, wherein the first read instruction is used to read training data, wherein the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2; a sampling module, configured to sample data signals transmitted on N transmission circuits at the sampling edge of the sampling signal to obtain first sampled data, wherein the N bits in the training data are transmitted as data signals on the N transmission circuits, and the first sampled data is data represented by N bits; a determination module, configured to determine the transmission circuits with timing offsets among the N transmission circuits based on the values ​​of the same bits in the training data and the first sampled data; and an adjustment module, configured to adjust the transmission delay on the transmission circuits with timing offsets until the center of the data signal transmitted on the transmission circuits with timing offsets is aligned with the sampling edge of the sampling signal.

[0009] Optionally, the device is configured to determine the transmission circuits with timing offsets among the N transmission circuits based on the values ​​of the same bits in the training data and the first sampled data in the following manner: determining whether the values ​​of the same bits in the training data and the first sampled data are the same; if there are M bits with different values ​​among the N bits, determining the M transmission circuits among the N transmission circuits as the transmission circuits with timing offsets, wherein the M transmission circuits are used to transmit the data signals corresponding to the M bits, where M is greater than or equal to 1 and less than or equal to N.

[0010] Optionally, the device is used to adjust the transmission delay on the timing-skewed transmission circuit in such a way that the center of the data signal transmitted on the timing-skewed transmission circuit is aligned with the sampling edge of the sampled signal:

[0011] The transmission delay of the transmission circuit with timing offset in the N transmission circuits is adjusted in the first round until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampling signal.

[0012] If, after the first round of adjustment, there is a transmission circuit in the N transmission circuits whose transmitted data signal is not aligned with the target sampling edge, a second round of adjustment is performed on the transmission delay of the transmission circuit whose transmitted data signal is not aligned with the target sampling edge, until the center of the transmitted data signal in each of the N transmission circuits is aligned with the target sampling edge, wherein the target sampling edge is the sampling edge that is aligned with the center of the transmitted data signal in the N transmission circuits the most times.

[0013] Optionally, the device is used to perform a first round of adjustment on the transmission delay of the transmission circuits with timing offsets among the N transmission circuits in the following manner, until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampled signal:

[0014] Perform the following operations on each of the N transmission circuits that has a timing offset, wherein each of the transmission circuits that has a timing offset is the current transmission circuit when performing the following operations:

[0015] When the data signal transmitted on the current transmission circuit corresponds to the high level of the sampling signal, the first edge of the time window where the data signal transmitted on the current transmission circuit is located is determined as the first position, and the second edge of the time window where the data signal is located is determined as the second position.

[0016] Increase the transmission delay on the current transmission circuit until the first edge moves from the first position to the target position, and determine a first delay amount of the increased transmission delay on the current transmission circuit, wherein the target position corresponds to the sampling edge of the sampled signal;

[0017] Reduce the transmission delay of the current transmission circuit until the second edge moves from the second position to the target position, and determine a second delay amount that reduces the transmission delay on the current transmission circuit;

[0018] The time window of the data signal transmitted on the current transmission circuit is adjusted according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampled signal.

[0019] Optionally, the device is configured to perform a second round of adjustment on the transmission delay of the transmission circuits in which the transmitted data signal is not aligned with the target sampling edge, in the case where, after the first round of adjustment, there is a transmission circuit in which the transmitted data signal is not aligned with the target sampling edge, until the center of the transmitted data signal in each of the N transmission circuits is aligned with the target sampling edge:

[0020] Repeat the following operation until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, wherein the current sampling edge is initialized as the sampling edge adjacent to the target sampling edge:

[0021] The first group of sampling edges in the sampling signal, excluding the target sampling edge, is turned off by clock gating, while the target sampling edge is retained.

[0022] Based on whether the center of the data signal transmitted on the N transmission circuits is aligned with the target sampling edge, determine whether there is a first group of data signals that is not aligned with the target sampling edge among the data signals transmitted on the N transmission circuits;

[0023] In the presence of the first set of data signals, the second set of sampling edges in the sampling signal, excluding the current sampling edge, is closed by the clock gating, while the current sampling edge is retained. The second set of sampling edges includes the target sampling edge, and the current sampling edge is different from the target sampling edge.

[0024] Based on whether the center of the first group of data signals is aligned with the current sampling edge, it is determined whether there is a second group of data signals in the first group of data signals that is not aligned with the second group of sampling edges;

[0025] If a target data signal is present in the first group of data signals, the transmission delay on the transmission circuit that transmits the target data signal is adjusted, wherein the center of the target data signal is aligned with the current sampling edge before the adjustment and with the target sampling edge after the adjustment.

[0026] In the presence of the second set of data signals, the current sampling edge is updated to the sampling edge in the sampling signal that was not retained by the clock gate.

[0027] Optionally, the device is used to adjust the transmission delay on the timing-skewed transmission circuit in such a way that the center of the data signal transmitted on the timing-skewed transmission circuit is aligned with the sampling edge of the sampled signal:

[0028] A target delay unit is determined in the delay control unit set on the transmission circuit with timing offset, and the corresponding data signal is transmitted from the output position of the target delay unit. The center of the data signal transmitted from the output position of the target delay unit is aligned with the sampling edge of the sampling signal. A delay control unit is set on each transmission path in the N transmission circuits. The delay control unit includes a preset number of delay units connected in series. Each delay unit is used to adjust the transmission delay on the transmission circuit by a unit duration.

[0029] Optionally, the device is further used for:

[0030] After the transmission delay on the transmission circuit with timing offset in the N transmission circuits is adjusted, N target transmission circuits are obtained, wherein the center of the data signal transmitted on each of the N target transmission circuits is aligned with the sampling edge of the sampled signal.

[0031] In response to the acquired second read instruction, the data signals transmitted on the N target transmission circuits are sampled on the sampling edge of the sampling signal to obtain second sampled data. The second read instruction is used to read target data, wherein the target data is unknown and is represented by N bits. The N bits of the target data are transmitted as data signals on the N target transmission circuits. The second sampled data is data represented by N bits.

[0032] Optionally, the device is further used for:

[0033] When the target memory is configured in read register mode, the second read instruction is sent, wherein the target memory is divided into multiple double-byte registers, and the second read instruction is used to read the target data in the target double-byte register among the multiple double-byte registers through the N target transmission circuits.

[0034] Optionally, the device is configured to, in response to a received second read command, sample the data signals transmitted on the N target transmission circuits on the sampling edge of the sampling signal to obtain second sampled data, including:

[0035] In response to the acquired second read instruction, the 128-bit memory read data bus signal, the 16-bit read data mask signal, and the 16-bit data bus toggle signal transmitted on the 160 target transmission circuits are sampled on the sampling edge of the sampling signal to obtain the second sampled data.

[0036] Optionally, the device is used to adjust the transmission delay on the timing-skewed transmission circuit in such a way that the center of the data signal transmitted on the timing-skewed transmission circuit is aligned with the sampling edge of the sampled signal:

[0037] When the sampling edge is a rising edge, adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the rising edge of the sampling signal; or

[0038] When the sampling edge is a falling edge, the transmission delay on the transmission circuit with timing offset is adjusted until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the falling edge of the sampling signal.

[0039] Optionally, the device is used to adjust the transmission delay on the timing-skewed transmission circuit in such a way that the center of the data signal transmitted on the timing-skewed transmission circuit is aligned with the sampling edge of the sampled signal:

[0040] The transmission delay on the transmission circuit with timing offset is adjusted until the center point of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampled signal, wherein the center point is the center point of the time window in which the data signal is located; or

[0041] The transmission delay on the transmission circuit with timing offset is adjusted until the sampling edge of the sampling signal is located in the time sub-window corresponding to the data signal transmitted on the transmission circuit with timing offset, wherein the time sub-window is a sub-window that includes the center point in the time window.

[0042] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, and the computer program is configured to execute the above-described timing adjustment method when running.

[0043] According to another aspect of the embodiments of this application, a computer program product or computer program is provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the timing adjustment method described above.

[0044] According to another aspect of the embodiments of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the timing adjustment method described above through the computer program.

[0045] In this embodiment, a sampling signal is generated in response to a first read instruction. The first read instruction is used to read training data, which is known data represented by N bits, where N is a positive integer greater than or equal to 2. The data signals transmitted on N transmission circuits are sampled on the sampling edge of the sampling signal to obtain first sampled data. The N bits in the training data are transmitted as data signals on the N transmission circuits. The first sampled data is data represented by N bits. Based on the values ​​of the same bits in the training data and the first sampled data, the transmission circuits with timing offsets are identified among the N transmission circuits. The transmission delay on the transmission circuits with timing offsets is adjusted until the center of the data signal transmitted on the transmission circuits with timing offsets is aligned with the sampling edge of the sampling signal. By performing pin training for reading data, the offset between the data signal read by the memory device and the sampling signal can be adjusted, thereby ensuring that the sampling signal is aligned with the center of the data signal read from the data device. This achieves the technical effect of improving the accuracy of reading data and solves the technical problem in related technologies where the data signal and the sampling signal cannot be aligned, leading to incorrect data sampling. Attached Figure Description

[0046] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0047] Figure 1 This is a schematic diagram of an application environment for an optional timing adjustment method according to an embodiment of this application;

[0048] Figure 2 This is a flowchart illustrating an optional timing adjustment method according to an embodiment of this application;

[0049] Figure 3 This is a schematic diagram of an optional timing adjustment method according to an embodiment of this application;

[0050] Figure 4 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0051] Figure 5 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0052] Figure 6 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0053] Figure 7 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0054] Figure 8 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0055] Figure 9 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0056] Figure 10 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0057] Figure 11 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0058] Figure 12 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0059] Figure 13 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0060] Figure 14 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0061] Figure 15 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0062] Figure 16 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0063] Figure 17 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application;

[0064] Figure 18 This is a schematic diagram of an optional timing adjustment device according to an embodiment of this application;

[0065] Figure 19 This is a schematic diagram of the structure of an optional timing adjustment product according to an embodiment of this application;

[0066] Figure 20 This is a schematic diagram of the structure of an optional electronic device according to an embodiment of this application. Detailed Implementation

[0067] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0068] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0069] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows:

[0070] HBM: High-Bandwidth Memory.

[0071] MISR: Multiple-input Shift Register.

[0072] Loopback Test: A self-loop test.

[0073] At Speed: High-speed operating mode.

[0074] DWORD: Data Word.

[0075] Read Register Mode: Read register mode.

[0076] Training: Training.

[0077] RDQS: Read DQ Strobe, read data selection pulse.

[0078] The present application will be described below in conjunction with embodiments:

[0079] According to one aspect of an embodiment of the present application, a timing adjustment method is provided. Optionally, in this embodiment, the above timing adjustment method can be applied to a hardware environment composed of a server 101 and a terminal device 103 as shown in Figure 1 the figure. As shown in Figure 1 the figure, the server 101 is connected to the terminal 103 through a network and can be used to provide services for the terminal device or an application installed on the terminal device. The application can be a video application, an instant messaging application, a browser application, an educational application, a game application, etc. A database 105 can be set on the server or independently of the server to provide data storage services for the server 101. For example, a game data storage server. The above network can include, but is not limited to: a wired network, a wireless network. Among them, the wired network includes: a local area network, a metropolitan area network, and a wide area network. The wireless network includes: Bluetooth, WIFI, and other networks that implement wireless communication. The terminal device 103 can be a terminal configured with an application and can include, but is not limited to, at least one of the following: a mobile phone (such as an Android mobile phone, an iOS mobile phone, etc.), a laptop computer, a tablet computer, a handheld computer, a MID (Mobile Internet Devices, mobile Internet device), a PAD, a desktop computer, a smart TV, a smart voice interaction device, a smart home appliance, a vehicle-mounted terminal, an aircraft, etc. The above server can be a single server, a server cluster composed of multiple servers, or a cloud server. The application 107 using the above timing adjustment method is displayed through the terminal device 103 or other connected display devices.

[0080] Combined with Figure 1 shown in the figure, the above timing adjustment method can be implemented on the terminal device 103 through the following steps:

[0081] S1. In response to the acquired first read instruction on the terminal device 103, a sampling signal is generated. Among them, the first read instruction is used to read training data. The training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

[0082] S2, the terminal device 103 samples the data signals transmitted on the N transmission circuits on the sampling edge of the sampling signal to obtain the first sampled data, wherein the N bits in the training data are transmitted as data signals on the N transmission circuits, and the first sampled data is data represented by N bits.

[0083] S3, on the terminal device 103, based on the values ​​of the same bits in the training data and the first sampled data, determine the transmission circuits with timing offsets among the N transmission circuits;

[0084] S4, on the terminal device 103, adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampling signal.

[0085] Optionally, in this embodiment, the timing adjustment method described above can also be implemented via a server, for example, Figure 1 It is implemented in server 101 shown; or it is implemented jointly by the terminal device and the server.

[0086] The above is merely an example, and this embodiment does not impose any specific limitations.

[0087] Alternatively, as an alternative implementation method, such as Figure 2 As shown, the timing adjustment method described above includes:

[0088] S202, in response to the acquired first read instruction, generate a sampling signal, wherein the first read instruction is used to read training data, wherein the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

[0089] S204, sample the data signals transmitted on N transmission circuits on the sampling edge of the sampling signal to obtain the first sampled data, wherein N bits in the training data are transmitted as data signals on N transmission circuits, and the first sampled data is data represented by N bits;

[0090] S206, Based on the values ​​of the same bits in the training data and the first sampled data, determine the transmission circuits with timing offsets among the N transmission circuits;

[0091] S208, adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampled signal.

[0092] Optionally, in the embodiments of this application, the above timing adjustment method may be applied to any scenario that requires reading data through a memory device, such as the data reading process in application scenarios such as game applications, live streaming applications, video production applications, instant messaging applications, transportation applications, artificial intelligence, etc.

[0093] Artificial intelligence (AI) refers to the theories, methods, technologies, and application systems that utilize digital computers or computers-controlled machines to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive technology within computer science that attempts to understand the essence of intelligence and produce new intelligent machines that can react in a way similar to human intelligence. AI studies the design principles and implementation methods of various intelligent machines, enabling them to possess perception, reasoning, and decision-making capabilities.

[0094] Artificial intelligence (AI) is a comprehensive discipline encompassing a wide range of fields, including both hardware and software technologies. Fundamental AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies primarily include computer vision, speech processing, natural language processing, and machine learning / deep learning.

[0095] Machine Learning (ML) is a multidisciplinary field involving probability theory, statistics, approximation theory, convex analysis, and algorithm complexity theory. It specifically studies how computers can simulate or implement human learning behavior to acquire new knowledge or skills and reorganize existing knowledge structures to continuously improve their performance. Machine learning is the core of artificial intelligence and the fundamental way to endow computers with intelligence; its applications span all areas of artificial intelligence. Machine learning and deep learning typically include techniques such as artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and instructional learning.

[0096] With the research and advancement of artificial intelligence (AI) technology, AI is being studied and applied in various fields, such as smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, autonomous driving, drones, robots, smart healthcare, and smart customer service. It is believed that with the development of technology, AI will be applied in more fields and play an increasingly important role.

[0097] Optionally, in this embodiment, the first read instruction may include, but is not limited to, an instruction sent by the host for reading data. Taking an HBM device as an example, according to the relevant HBM protocol, the data read / write speed of an HBM 2E device can reach a maximum bit rate of 3.6 GHz. Since HBM transmits data on both the rising and falling edges of the clock, the actual communication clock frequency of HBM 2E is at most 1.8 GHz. At such a high operating frequency, if the data transmission is affected by noise interference on the data communication link, or if crosstalk occurs between data lines, it can easily lead to errors in data read / write operations in high-speed mode.

[0098] HBM devices typically organize read operations in bursts, with a read burst operation initiated by sending a READ command. Figure 3 This is a schematic diagram of an optional timing adjustment method according to an embodiment of this application, such as... Figure 3 As shown, after a READ instruction is sent, 8 bits of data are read on both the rising and falling edges. The burst length of the HBM READ instruction is either 2 or 4.

[0099] When HBM DRAM receives a READ command, it returns read data DQ, DM, and DBI to the HBM Host. Figure 4 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application. The format of the HBM DRAM returned data is as follows: Figure 4 As shown, Figure 4 The relevant timing parameters included are as follows:

[0100] 1.tDQSCK(min / max): The minimum and maximum time range between the rising edge (or falling edge) of RDQS_c and the rising edge (or falling edge) of CK_c;

[0101] 2.tDQSCK: Describes the time delay between the rising edge of RDQS and the rising edge of CK;

[0102] 3.tQSH: Describes the time delay during which the RDQS signal remains high;

[0103] 4.tQSL: Describes the time delay during which the RDQS signal remains low;

[0104] 5.tLZ(min / max): describes the minimum and maximum time range from the sustained high impedance state to the low impedance state of the read data;

[0105] 6. tHZ (min / max): Describes the minimum and maximum time range from the sustained low impedance state to the high impedance state of the data reading;

[0106] 7.tDQSQ: Describes the time delay between the rising edge of RDQS_t (or the falling edge of RDQS_c) and the reading of DQ, DM, and DBI data;

[0107] 8.tQH: Describes the time delay from the rising edge of RDQS_t (or the falling edge of RDQS_c) to the time it takes for the DQ, DM, and DBI data to remain stable after being read.

[0108] Figure 5 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application. If the HBM DRAM uses a length BL (Burst Length) of 2, the read data output timing is as follows: Figure 5 As shown, from Figure 5 As can be seen, the data reading continued for two consecutive cycles.

[0109] Figure 6 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application. If the HBM DRAM uses a BL (Burst Length) of 4, the read data output timing is as follows: Figure 6 As shown. From Figure 6 As can be seen, the data reading continued for four consecutive cycles.

[0110] The above is merely an example, and this embodiment does not impose any specific limitations.

[0111] Optionally, in the embodiments of this application, the above-mentioned generation of sampling signals may include, but is not limited to, assembling the corresponding sampling clock with the differential clock signals corresponding to CK_c or CK_t according to different services. That is, different sampling signals may include, but are not limited to, being generated based on the above-mentioned differential clock signals.

[0112] Figure 7 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application, such as... Figure 7 As shown, taking a single read operation using HBM as an example, the steps may include, but are not limited to, the following:

[0113] When the HBM Host initiates a read operation to the HBM DRAM, the HBM DRAM will return the read data to the HBM Host. Simultaneously, the HBM DRAM will also return an RDQS (Read Select Pulse) signal to the HBM Host that matches the read data. Figure 6 In the command, ACT is a one-time activation command, and PRE is a one-time precharge command. The HBM HOST will use this signal as the sampling signal for the read data. Therefore, if the sampling signal RDQS can be aligned with the center of the read data, the sampling accuracy will be the highest.

[0114] The above is merely an example, and this embodiment does not impose any specific limitations.

[0115] Optionally, in the embodiments of this application, the training data mentioned above is known and may include, but is not limited to, pre-configured data for training the read data pins. The training data may include, but is not limited to, data represented by N bits, for example, training data generated by 128-bit DQ, 16-bit DM and 16-bit DBI paths.

[0116] Optionally, in this embodiment, the sampling edge of the sampling signal may include, but is not limited to, the rising edge or falling edge of the sampling signal. The data signals transmitted on the N transmission circuits may include, but are not limited to, for data represented by N bits, each transmission circuit transmits one bit of data. The sampling of the data signals transmitted on the N transmission circuits may include, but is not limited to, when the read data is returned, selecting a pulse signal that matches the read data to sample the data signal and obtain the first sampled data.

[0117] It should be noted that the N bits in the above training data being transmitted as data signals on N transmission circuits can be understood as each bit of training data being transmitted as a data signal on the corresponding transmission circuit, so that the training data represented by N bits can be read through N transmission circuits.

[0118] Optionally, in the embodiments of this application, the first sampled data is data represented by N bits, which may include, but is not limited to, the first sampled data being regarded as the data to be read by the first read instruction.

[0119] Optionally, in the embodiments of this application, the values ​​of the same bits in the training data and the first sampled data may include, but are not limited to, the transmission of the corresponding bit data signal on each transmission channel during the transmission of N bits of data signal on N transmission circuits. At this time, the training data is known, and it is determined whether the data signal transmitted by the first sampled data on the N transmission circuits is the same as the value of the training data.

[0120] For example, the training data can be configured to transmit "1" as the value of the data signal on N transmission circuits, and it can be determined whether the value of the data signal transmitted on the N transmission circuits of the first sampled data is equal to 1. Then, the transmission circuits whose value of the data signal transmitted on the N transmission circuits is not equal to 1 are identified as the transmission circuits with timing offsets mentioned above.

[0121] Figure 8 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application, such as... Figure 8As shown, taking a single read operation using HBM as an example, the steps may include, but are not limited to, the following:

[0122] Figure 8 The diagram illustrates the use of CLK to sample Data. In the HBM read data scenario, CLK represents the RDQS signal returned by the HBM DRAM, and Data contains the DQ, DM, and DBI data returned by the HBM DRAM. In scenario I, the sampling edge of CLK is located at the data center position, resulting in the highest sampling accuracy. In scenarios II and III, misalignment occurs between the read data and the sampled RDQS signal, with an offset from the data center.

[0123] In case II, the clock sampling edge will drift out of the read data window; in case III, although the clock sampling edge does not drift out of the read data window, the sampling edge and the data setup (or hold timing) edge are too close, causing a setup (or hold timing) violation in this sampling. Both of these situations will lead to sampling errors in the read data.

[0124] When an error occurs while reading data from HBM DRAM, it will affect the correct execution of the entire HBM subsystem, and in severe cases, it may even affect the normal operation of the entire chip.

[0125] Therefore, the read data transmission circuits corresponding to II and III above are determined to be the transmission circuits with timing offsets.

[0126] Optionally, in the embodiments of this application, the above-mentioned adjustment of the transmission delay on the transmission circuit with timing offset may be achieved, including but not limited to, by adding a delay circuit to the transmission circuit with timing offset, for example, adding an inverter circuit.

[0127] Optionally, in this embodiment, the alignment of the center of the data signal transmitted on the transmission circuit with the sampling edge of the sampled signal until a timing offset exists may include, but is not limited to, the alignment of the center of the data signal transmitted on the transmission circuit with the sampling edge of the sampled signal with the sampling edge of the sampled signal being as follows: Figure 8 As shown in Figure I, the sampling edge of CLK is located at the center of the data signal of Data.

[0128] In this embodiment, a sampling signal is generated in response to a first read instruction. The first read instruction is used to read training data, which is known data represented by N bits, where N is a positive integer greater than or equal to 2. The data signals transmitted on N transmission circuits are sampled on the sampling edge of the sampling signal to obtain first sampled data. The N bits in the training data are transmitted as data signals on the N transmission circuits. The first sampled data is data represented by N bits. Based on the values ​​of the same bits in the training data and the first sampled data, the transmission circuits with timing offsets are identified among the N transmission circuits. The transmission delay on the transmission circuits with timing offsets is adjusted until the center of the data signal transmitted on the transmission circuits with timing offsets is aligned with the sampling edge of the sampling signal. By performing pin training for reading data, the offset between the data signal read by the memory device and the sampling signal can be adjusted, thereby ensuring that the sampling signal is aligned with the center of the data signal read from the data device. This achieves the technical effect of improving the accuracy of reading data and solves the technical problem in related technologies where the data signal and the sampling signal cannot be aligned, leading to incorrect data sampling.

[0129] As an optional approach, based on the values ​​of the same bits in the training data and the first sampled data, the transmission circuits with timing offsets among the N transmission circuits are identified, including:

[0130] S1, determine whether the values ​​of the same bits in the training data and the first sampled data are the same;

[0131] S2, In the case that there are M bits with different values ​​among N bits, M transmission circuits out of the N transmission circuits are determined as transmission circuits with timing offset. Among them, the M transmission circuits are used to transmit the data signals corresponding to the M bits, where M is greater than or equal to 1 and less than or equal to N.

[0132] Optionally, in the embodiments of this application, the determination of whether the values ​​of the same bits in the training data and the first sampled data are the same may include, but is not limited to, whether the value of bit1 in the training data is the same as the value of bit1 in the first sampled data. If they are the same, it is considered that there is no timing offset in the transmission circuit where bit1 is located. If they are different, it is considered that there is a timing offset in the transmission circuit where bit1 is located. And so on, bit2, bit3, ..., bitN all perform the above determination.

[0133] Optionally, in the embodiments of this application, the existence of M bits with different values ​​among N bits can be understood as M transmission circuits among N transmission circuits having timing offsets.

[0134] As an optional approach, the transmission delay on the transmission circuit with timing skew is adjusted until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal, including:

[0135] S1, perform the first round of adjustment on the transmission delay of the transmission circuit with timing offset in the N transmission circuits, until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampled signal.

[0136] S2, after the first round of adjustment, if there is a transmission circuit in the N transmission circuits whose transmitted data signal is not aligned with the target sampling edge, perform a second round of adjustment on the transmission delay of the transmission circuit whose transmitted data signal is not aligned with the target sampling edge, until the center of the transmitted data signal in each of the N transmission circuits is aligned with the target sampling edge, where the target sampling edge is the sampling edge that is aligned with the center of the transmitted data signal in the N transmission circuits the most times.

[0137] Optionally, in the embodiments of this application, the first round of adjustment may include, but is not limited to, aligning the center of the data signal transmitted on each of the N transmission circuits with a sampling edge of the sampling signal, that is, aligning the center of the data signal transmitted on each of the N transmission circuits with the same or different sampling edges.

[0138] For example, Figure 9 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application, such as... Figure 9 As shown, clock is the sampling signal, which includes multiple sampling edges (sampling edge 902, sampling edge 904, sampling edge 906). The centers of the data signals of bit0 and biti are not aligned with sampling edge 904, while the centers of the data signals of bit1 and bitj are aligned with sampling edge 904. At this time, the first round of adjustment mentioned above needs to be performed on bit0 and biti so that the centers of the data signals of bit0 and biti are aligned with at least one of the sampling edges 902, 904, and 906.

[0139] Optionally, in the embodiments of this application, the above-mentioned second round of adjustment may include, but is not limited to, first determining the target sampling edge that aligns most frequently with the center of the data signals transmitted on the N transmission circuits, and then moving the center of the data signals transmitted on the transmission circuits that are not aligned with the target sampling edge to align with the target sampling edge. Specifically, it may include, but is not limited to, using a delay unit with a duration corresponding to one sampling period to move the center of the data signals that are aligned with other sampling edges besides the target sampling edge to align with the target sampling edge.

[0140] For example, with Figure 9 For example, the centers of the data signals bit1 and bitj are aligned with the sampling edge 904. After the first round of adjustment, the centers of the data signals bit0 and biti are aligned with the sampling edges 902 and 906, respectively. At this time, by adjusting the transmission delay of the transmission circuits corresponding to the data signals of bit0 and biti, bit0 and biti are also aligned with the sampling edge 904, until the centers of the data signals transmitted on each of the N transmission circuits are aligned with the sampling edge 904.

[0141] Optionally, in this embodiment of the application, if the center of the data signal transmitted on each of the N transmission circuits obtained after the first round of adjustment is aligned with the target sampling edge, the N transmission circuits obtained after the first round of adjustment are determined as N target transmission circuits.

[0142] Through the embodiments of this application, the read data pins can be trained before the HBM chip initially operates. This ensures that sampling errors in the chip's read data path are avoided due to back-end timing non-convergence and HBM chip manufacturing defects during initial chip operation, guaranteeing the stability of the read data path during initial chip operation. When the HBM chip detects significant PVT drift, the software can configure the chip to train the read data pins, ensuring that the chip will not experience data transmission errors in the read data path due to PVT drift. The hardware-integrated periodic read data training mechanism can be used to periodically train the HBM chip, ensuring that the chip will not experience read data sampling errors during operation. Single-step read data training configured by the software is supported, so the entire chip's read data training can also be configured and completed independently by the software. Since the software can complete this action when the system is not busy, it ensures that the read data pins do not experience sampling errors while simultaneously maintaining the efficiency of the entire system.

[0143] This application employs an automated training method implemented with hardware circuitry. Alternatively, the entire training process can be accomplished using software-configured registers. Specifically, the Stepcounter value can be manually configured using software-configured registers, along with the Host's read data sending commands and the MR7 register configuration, to read and verify the content of the read data received from the HBM DRAM. Therefore, the software can independently initiate each step of the single-step training process based on the read data.

[0144] As an optional approach, the transmission delay of the transmission circuits with timing offsets in the N transmission circuits is adjusted in the first round until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampled signal, including:

[0145] Perform the following operations on each of the N transmission circuits that has a timing offset, where each transmission circuit with a timing offset is the current transmission circuit when performing the following operations:

[0146] When the data signal transmitted on the current transmission circuit corresponds to the high level of the sampling signal, the first edge of the time window where the data signal transmitted on the current transmission circuit is located is determined as the first position, and the second edge of the time window where the data signal is located is determined as the second position.

[0147] Increase the transmission delay on the current transmission circuit until the first edge moves from the first position to the target position, and determine the first delay amount of the increased transmission delay on the current transmission circuit, wherein the target position corresponds to the sampling edge of the sampled signal;

[0148] Reduce the transmission delay of the current transmission circuit until the second edge moves from the second position to the target position, and determine the second delay amount of the reduced transmission delay on the current transmission circuit;

[0149] Adjust the time window of the data signal transmitted on the current transmission circuit according to the first delay and the second delay, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampled signal.

[0150] Optionally, in this embodiment, the high level of the sampling signal corresponding to the data signal transmitted on the current transmission circuit may include, but is not limited to, any part of the time window in which the data signal is located coinciding with the high level interval of the sampling signal.

[0151] For example, Figure 10 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application, such as... Figure 10 As shown, in (1), the area from the left edge of the time window of the data signal to point A coincides with the high-level interval of the sampling signal. At this time, it is considered that the data signal corresponds to the high level of the sampling signal. In (2), the entire area from the left edge to the right edge of the time window of the data signal does not coincide with the high-level interval of the sampling signal. At this time, it is considered that the data signal corresponds to the low level of the sampling signal.

[0152] Optionally, in this embodiment of the application, the rising edge of the time window may be defined as the first edge, the rising right edge of the time window may be defined as the second edge, the first position is the initial position of the left edge, and the second position is the initial position of the right edge.

[0153] Optionally, in the embodiments of this application, the above-mentioned increase in transmission delay on the current transmission circuit may include, but is not limited to, adding a delay circuit on the current transmission circuit to increase transmission delay, and the above-mentioned reduction in transmission delay on the current transmission circuit may include, but is not limited to, reducing a delay circuit on the current transmission circuit to reduce transmission delay.

[0154] Optionally, in this embodiment, the movement of the first edge from the first position to the target position may include, but is not limited to, adding a delay circuit to shift the time window of the data signal transmitted on the current transmission circuit backward until the left edge of the time window aligns with the sampling edge of the sampled signal. The movement of the second edge from the second position to the target position may include, but is not limited to, reducing the delay circuit to shift the time window of the data signal transmitted on the current transmission circuit forward until the right edge of the time window aligns with the sampling edge of the sampled signal.

[0155] It should be noted that the amount of delay circuit added when the first edge moves from the first position to the target position is the first delay amount, and the amount of delay circuit reduced when the second edge moves from the second position to the target position is the second delay amount.

[0156] Optionally, in this embodiment, adjusting the time window of the data signal transmitted on the current transmission circuit according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampling signal, may include, but is not limited to, using half of the sum of the first delay amount and the second delay amount as the transmission delay that needs to be adjusted to align the center of the data signal transmitted on the current transmission circuit with the sampling edge of the sampling signal.

[0157] That is, by adjusting half of the sum of the first delay and the second delay, the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampling signal.

[0158] For example, Figure 11 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application, such as... Figure 11 As shown, during the first round of adjustment, the initial state of the bit for reading data (corresponding to the aforementioned current transmission circuit) is phase 0. At this time, the value of the bit read back should be 1 (corresponding to the high level of the sampling signal corresponding to the data signal transmitted on the aforementioned current transmission circuit). By continuously increasing the circuit delay of this bit by adjusting the Step Counter, eventually, the value of the bit read back will reach 0 (corresponding to the aforementioned target position). At this time, the value of the Step Counter is recorded as R_CNT (corresponding to the aforementioned first delay amount).

[0159] After that, the initial state of Phase 1 to Phase 0 is set, and the circuit delay of this bit is continuously reduced by adjusting the Step Counter. Eventually, the value of this bit read back should be 0 (corresponding to the aforementioned target position). At this time, the value of the Step Counter is recorded as L_CNT (corresponding to the aforementioned second delay amount).

[0160] At this point, it can be calculated that when the circuit delay of this bit is (R_CNT+L_CNT) / 2, this bit can achieve the purpose of aligning the sampling clock edge with the edge of the data signal time window.

[0161] Continue adjusting and calculating the circuit delay for each bit in this manner to align the sampling RDQS edge and the data edge for each read data bit. This completes the first round of adjustments.

[0162] As an optional approach, if, after the first round of adjustments, there are N transmission circuits in the network where the transmitted data signal is not aligned with the target sampling edge, a second round of adjustments is made to the transmission delay on those circuits until the center of the transmitted data signal on each of the N transmission circuits is aligned with the target sampling edge. This includes:

[0163] Repeat the following steps until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, wherein the current sampling edge is initialized to the sampling edge adjacent to the target sampling edge:

[0164] The first set of sampling edges in the sampling signal, excluding the target sampling edge, is turned off by clock gating, while the target sampling edge is retained.

[0165] Based on whether the center of the data signal transmitted on the N transmission circuits is aligned with the target sampling edge, determine whether there is a first group of data signals that is not aligned with the target sampling edge among the data signals transmitted on the N transmission circuits;

[0166] In the presence of the first set of data signals, the second set of sampling edges in the sampling signal, excluding the current sampling edge, is turned off by clock gating, while the current sampling edge is retained. The second set of sampling edges includes the target sampling edge, and the current sampling edge is different from the target sampling edge.

[0167] Based on whether the center of the first set of data signals is aligned with the current sampling edge, determine whether there is a second set of data signals in the first set of data signals that is not aligned with the second set of sampling edges;

[0168] If a target data signal is present in the first group of data signals, the transmission delay on the transmission circuit that transmits the target data signal is adjusted, wherein the center of the target data signal is aligned with the current sampling edge before the adjustment and with the target sampling edge after the adjustment.

[0169] If a second set of data signals exists, the current sampling edge will be updated to the sampling edge in the sampling signal that was not preserved by clock gating.

[0170] Optionally, in the embodiments of this application, the above-mentioned clock-gating is an important means of reducing the power consumption of microprocessors. It mainly targets the dynamic power consumption caused by register toggling. It can shut down one or more sampling cycles of the sampling signal to shut down the sampling edges that need to be shut down and retain the sampling edges that need to be retained.

[0171] Optionally, in this embodiment, each data signal in the first group of data signals is a data signal whose center is aligned with a sampling edge but not with a target sampling edge. When the first group of data signals exists, the second group of sampling edges in the sampling signal other than the current sampling edge is turned off by clock gating, the current sampling edge is retained, and the target sampling edge is also turned off. It is checked whether all the first group of data signals are aligned with the current sampling edge. The data signals aligned with the current sampling edge are used as the target data signals for transmission delay adjustment, so that the adjusted signals are not aligned with the current sampling edge but with the target sampling edge.

[0172] Optionally, in this embodiment of the application, each data signal in the second group of data signals is a data signal whose center is not aligned with the current sampling edge or the target sampling edge. In this case, by updating the current sampling edge to the sampling edge in the sampling signal that has not been retained by the clock gate, it is determined whether the first group of data signals exists in the second group of data signals, and the data signal aligned with the current sampling edge is used as the target data signal for transmission delay adjustment.

[0173] For example, Figure 12 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application, such as... Figure 12 As shown, Figure 12 A represents multiple transmission circuits in N transmission circuits whose center is aligned with the target sampling edge. Figure 12 B indicates that the first set of sampling edges, excluding the target sampling edge, is shut off by clock gating, while the target sampling edge is retained. The system determines whether a first set of data signals not aligned with the target sampling edge exists among the data signals transmitted on the N transmission circuits, based on whether the center of the data signals transmitted on the N transmission circuits is aligned with the target sampling edge. Figure 12C indicates that, in the presence of the first set of data signals, the second set of sampling edges in the sampling signal, excluding the current sampling edge, is shut down by clock gating, while the current sampling edge is retained. Depending on whether the center of the first set of data signals is aligned with the current sampling edge, if the target data signal exists in the first set of data signals, the transmission delay on the transmission circuit that transmits the target data signal is adjusted.

[0174] Optionally, in the embodiments of this application, the above-mentioned updating the current sampling edge to the sampling edge that has not been retained by clock gating in the sampling signal when there is a second set of data signals can be understood as updating the current sampling edge to the sampling edge that is closest to the target sampling edge and has not been retained by clock gating.

[0175] As an optional approach, the transmission delay on the transmission circuit with timing skew is adjusted until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal, including:

[0176] In a delay control unit set on a transmission circuit with timing offset, a target delay unit is determined, and the corresponding data signal is transmitted from the output position of the target delay unit. The center of the data signal transmitted from the output position of the target delay unit is aligned with the sampling edge of the sampling signal. A delay control unit is set on each transmission path in N transmission circuits. The delay control unit includes a preset number of delay units connected in series. Each delay unit is used to adjust the transmission delay on the transmission circuit by a unit duration.

[0177] Optionally, in this embodiment, the delay control unit may be implemented, including but not limited to, a delay control circuit. This delay control circuit supports dynamic adjustment of the delay circuit on the read data transmission path, allowing for increasing or decreasing the delay on the read data path. A delay circuit for adjusting the path delay of each read data bit is added to the read data transmission path.

[0178] For example, Figure 13 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application, such as... Figure 13 As shown, the read data path comprises a 128-bit DQ, a 16-bit DM, and a 16-bit DBI path. The DE (Delay Element) unit can include 128 DEs, each containing four inverter circuits. Each DE in this delay control unit is followed by a tapped interface (corresponding to the aforementioned output location). Figure 14 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application, such as... Figure 14As shown, the Step Counter can be used to control the value of the read data bits from a specific tap output. Therefore, the path delay of the read data can be adjusted, meaning the relative position of the read data and the RDQS sampling edge can be moved and adjusted.

[0179] Figure 15 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application. The schematic diagram of the application environment for the aforementioned timing adjustment is as follows: Figure 15 As shown, the HBM Host comprises four circuit parts: HBM mode configuration, read command sending unit, read data path delay control circuit, and read data training unit. The read data training unit is responsible for controlling the other three modules and comparing the read data to complete the entire read data training process.

[0180] As an alternative approach, the method also includes:

[0181] After adjusting the transmission delay on the transmission circuits with timing offsets in N transmission circuits, N target transmission circuits are obtained. The center of the data signal transmitted on each of the N target transmission circuits is aligned with the sampling edge of the sampled signal.

[0182] In response to the acquired second read instruction, the data signals transmitted on the N target transmission circuits are sampled on the sampling edge of the sampling signal to obtain the second sampled data. The second read instruction is used to read the target data, which is unknown and is represented by N bits. The N bits of the target data are transmitted as data signals on the N target transmission circuits. The second sampled data is data represented by N bits.

[0183] Optionally, in this embodiment, once the pin training of the N transmission circuits is completed, that is, once the transmission delay on the transmission circuit with timing offset among the N transmission circuits is adjusted, the aforementioned N target transmission circuits can begin to be used to transmit unknown target data.

[0184] As an alternative approach, the method also includes:

[0185] When the target memory is configured in read register mode, a second read instruction is sent, wherein the target memory is divided into multiple double-byte registers, and the second read instruction is used to read the target data in the target double-byte registers from the multiple double-byte registers through N target transmission circuits.

[0186] Optionally, in this embodiment, the target memory may include, but is not limited to, HBM memory, the second read instruction is used to read target data, and the HBM mode configuration unit is used to configure the DWORD MISR circuit to DWORD read register mode (corresponding to the aforementioned read register mode). This configuration is accomplished by configuring the HBM mode register MR7.

[0187] For example, Figure 16 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application. The specific mode of MR7 is as follows: Figure 16 As shown, the steps to configure the HBM DWORD to read register mode are as follows:

[0188] The value of MR7 is configured as 8'b00000001, where OP0 is 1, indicating that DWORD Loopback mode is enabled; OP[5:3] is 3'b000, resetting the default value in the DWORD register to 0xAAAAAh. The remaining bits are the default values.

[0189] The value of MR7 is configured as 8'b00010011, where OP0 is 1, indicating that DWORD Loopback mode is enabled; OP[2:1] is 2'b01, indicating that the value in the MISR register is read. Since this value was reset in step 1, its value is 0xAAAAAh; OP[5:3] is 3'b010, configuring the DWORD register to read or write register mode. The remaining bits are default values.

[0190] At this point, the HBM DRAM has been configured in DWORD read register mode, and the value in the DWORD register (corresponding to the aforementioned target data) can be read by sending a read command.

[0191] As an optional approach, in response to the acquired second read command, the data signals transmitted on the N target transmission circuits are sampled on the sampling edge of the sampling signal to obtain the second sampled data, including:

[0192] In response to the acquired second read command, the 128-bit memory read data bus signal, the 16-bit read data mask signal, and the 16-bit data bus toggle signal transmitted on the 160 target transmission circuits are sampled on the sampling edge of the sampling signal to obtain the second sampled data.

[0193] Optionally, in this embodiment of the application, the 128-bit memory read data bus signal transmitted on the above-mentioned 160 target transmission circuits may include, but is not limited to, a 128-bit DQ signal, the 16-bit read data mask signal may include, but is not limited to, a 16-bit DBI signal, and the 16-bit data bus toggle signal may include, but is not limited to, a 16-bit DM signal.

[0194] It should be noted that the 128-bit DWORD of the HBM data path is designed to be divided into DWORD0, DWORD1, DWORD2 and DWORD3. Within each DWORD, according to the width of the MISR algorithm, it is further divided into Byte0, Byte1, Byte2 and Byte3, a total of 4 data units for comparison.

[0195] For example, Figure 17 This is a schematic diagram of another optional timing adjustment method according to an embodiment of this application, such as... Figure 17 As shown, within each Byte, bits 19 to 0 represent the falling edge data and rising edge data of DBI, respectively; each bit of the 8-bit DQ represents the falling edge data and rising edge data; and each bit of the DM represents the falling edge data and rising edge data. Each Byte in the DWORD contains a 20-bit value. When the DWORD register is reset, this value will become 0xAAAAAh. The read instruction sending unit is responsible for sending read instructions to the HBM DRAM.

[0196] As an optional approach, the transmission delay on the transmission circuit with timing skew is adjusted until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal, including:

[0197] When the sampling edge is a rising edge, adjust the transmission delay on the transmission circuit with timing skew until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the rising edge of the sampling signal; or

[0198] When the sampling edge is a falling edge, adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the falling edge of the sampling signal.

[0199] Optionally, in the embodiments of this application, the sampling edge may include, but is not limited to, rising edge and falling edge. Data sampling and reading can be achieved by either rising edge or falling edge, or by simultaneously using rising edge and falling edge.

[0200] As an optional approach, the transmission delay on the transmission circuit with timing skew is adjusted until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal, including:

[0201] Adjust the transmission delay on the transmission circuit with timing skew until the center point of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal, where the center point is the center point of the time window in which the data signal is located; or

[0202] Adjust the transmission delay on the transmission circuit with timing offset until the sampling edge of the sampled signal is located in the time sub-window corresponding to the data signal transmitted on the transmission circuit with timing offset, wherein the time sub-window is a sub-window including the center point of the time window.

[0203] It is understood that in the specific embodiments of this application, data such as user information are involved. When the above embodiments of this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0204] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0205] According to another aspect of the embodiments of this application, a timing adjustment apparatus for implementing the above-described timing adjustment method is also provided. For example... Figure 18 As shown, the device includes:

[0206] The generation module 1802 is used to generate a sampling signal in response to the acquired first read instruction, wherein the first read instruction is used to read training data, wherein the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

[0207] The sampling module 1804 is used to sample the data signals transmitted on N transmission circuits on the sampling edge of the sampling signal to obtain first sampled data, wherein the N bits in the training data are transmitted as data signals on the N transmission circuits, and the first sampled data is data represented by N bits;

[0208] The determination module 1806 is used to determine the transmission circuits with timing offsets among the N transmission circuits based on the values ​​of the same bits in the training data and the first sampled data.

[0209] The adjustment module 1808 is used to adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampling signal.

[0210] As an optional solution, the device is used to determine the transmission circuits with timing offsets among the N transmission circuits based on the values ​​of the same bits in the training data and the first sampled data in the following manner: determining whether the values ​​of the same bits in the training data and the first sampled data are the same; if there are M bits with different values ​​among the N bits, determining the M transmission circuits among the N transmission circuits as the transmission circuits with timing offsets, wherein the M transmission circuits are used to transmit the data signals corresponding to the M bits, where M is greater than or equal to 1 and less than or equal to N.

[0211] As an alternative, the device is used to adjust the transmission delay on the timing-skewed transmission circuit in such a way that the center of the data signal transmitted on the timing-skewed transmission circuit is aligned with the sampling edge of the sampled signal:

[0212] The transmission delay of the transmission circuit with timing offset in the N transmission circuits is adjusted in the first round until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampling signal.

[0213] If, after the first round of adjustment, there is a transmission circuit in the N transmission circuits whose transmitted data signal is not aligned with the target sampling edge, a second round of adjustment is performed on the transmission delay of the transmission circuit whose transmitted data signal is not aligned with the target sampling edge, until the center of the transmitted data signal in each of the N transmission circuits is aligned with the target sampling edge, wherein the target sampling edge is the sampling edge that is aligned with the center of the transmitted data signal in the N transmission circuits the most times.

[0214] As an optional solution, the apparatus is used to perform a first round of adjustment on the transmission delay of the transmission circuits with timing offsets among the N transmission circuits in the following manner, until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampled signal:

[0215] Perform the following operations on each of the N transmission circuits that has a timing offset, wherein each of the transmission circuits that has a timing offset is the current transmission circuit when performing the following operations:

[0216] When the data signal transmitted on the current transmission circuit corresponds to the high level of the sampling signal, the first edge of the time window where the data signal transmitted on the current transmission circuit is located is determined as the first position, and the second edge of the time window where the data signal is located is determined as the second position.

[0217] Increase the transmission delay on the current transmission circuit until the first edge moves from the first position to the target position, and determine a first delay amount of the increased transmission delay on the current transmission circuit, wherein the target position corresponds to the sampling edge of the sampled signal;

[0218] Reduce the transmission delay of the current transmission circuit until the second edge moves from the second position to the target position, and determine a second delay amount that reduces the transmission delay on the current transmission circuit;

[0219] The time window of the data signal transmitted on the current transmission circuit is adjusted according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampled signal.

[0220] As an optional solution, the device is used to perform a second round of adjustment on the transmission delay of the transmission circuits in which the transmitted data signal is not aligned with the target sampling edge, in the case where, after the first round of adjustment, there are transmission circuits in the N transmission circuits where the transmitted data signal is not aligned with the target sampling edge, until the center of the transmitted data signal in each of the N transmission circuits is aligned with the target sampling edge:

[0221] Repeat the following operation until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, wherein the current sampling edge is initialized as the sampling edge adjacent to the target sampling edge:

[0222] The first group of sampling edges in the sampling signal, excluding the target sampling edge, is turned off by clock gating, while the target sampling edge is retained.

[0223] Based on whether the center of the data signal transmitted on the N transmission circuits is aligned with the target sampling edge, determine whether there is a first group of data signals that is not aligned with the target sampling edge among the data signals transmitted on the N transmission circuits;

[0224] In the presence of the first set of data signals, the second set of sampling edges in the sampling signal, excluding the current sampling edge, is closed by the clock gating, while the current sampling edge is retained. The second set of sampling edges includes the target sampling edge, and the current sampling edge is different from the target sampling edge.

[0225] Based on whether the center of the first group of data signals is aligned with the current sampling edge, it is determined whether there is a second group of data signals in the first group of data signals that is not aligned with the second group of sampling edges;

[0226] If a target data signal is present in the first group of data signals, the transmission delay on the transmission circuit that transmits the target data signal is adjusted, wherein the center of the target data signal is aligned with the current sampling edge before the adjustment and with the target sampling edge after the adjustment.

[0227] In the presence of the second set of data signals, the current sampling edge is updated to the sampling edge in the sampling signal that was not retained by the clock gate.

[0228] As an alternative, the device is used to adjust the transmission delay on the timing-skewed transmission circuit in such a way that the center of the data signal transmitted on the timing-skewed transmission circuit is aligned with the sampling edge of the sampled signal:

[0229] A target delay unit is determined in the delay control unit set on the transmission circuit with timing offset, and the corresponding data signal is transmitted from the output position of the target delay unit. The center of the data signal transmitted from the output position of the target delay unit is aligned with the sampling edge of the sampling signal. A delay control unit is set on each transmission path in the N transmission circuits. The delay control unit includes a preset number of delay units connected in series. Each delay unit is used to adjust the transmission delay on the transmission circuit by a unit duration.

[0230] As an optional solution, the device is also used for:

[0231] After the transmission delay on the transmission circuit with timing offset in the N transmission circuits is adjusted, N target transmission circuits are obtained, wherein the center of the data signal transmitted on each of the N target transmission circuits is aligned with the sampling edge of the sampled signal.

[0232] In response to the acquired second read instruction, the data signals transmitted on the N target transmission circuits are sampled on the sampling edge of the sampling signal to obtain second sampled data. The second read instruction is used to read target data, wherein the target data is unknown and is represented by N bits. The N bits of the target data are transmitted as data signals on the N target transmission circuits. The second sampled data is data represented by N bits.

[0233] As an optional solution, the device is also used for:

[0234] When the target memory is configured in read register mode, the second read instruction is sent, wherein the target memory is divided into multiple double-byte registers, and the second read instruction is used to read the target data in the target double-byte register among the multiple double-byte registers through the N target transmission circuits.

[0235] As an optional solution, the device is configured to, in response to a received second read command, sample the data signals transmitted on the N target transmission circuits on the sampling edge of the sampling signal to obtain second sampled data, including:

[0236] In response to the acquired second read instruction, the 128-bit memory read data bus signal, the 16-bit read data mask signal, and the 16-bit data bus toggle signal transmitted on the 160 target transmission circuits are sampled on the sampling edge of the sampling signal to obtain the second sampled data.

[0237] As an alternative, the device is used to adjust the transmission delay on the timing-skewed transmission circuit in such a way that the center of the data signal transmitted on the timing-skewed transmission circuit is aligned with the sampling edge of the sampled signal:

[0238] When the sampling edge is a rising edge, adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the rising edge of the sampling signal; or

[0239] When the sampling edge is a falling edge, the transmission delay on the transmission circuit with timing offset is adjusted until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the falling edge of the sampling signal.

[0240] As an alternative, the device is used to adjust the transmission delay on the timing-skewed transmission circuit in such a way that the center of the data signal transmitted on the timing-skewed transmission circuit is aligned with the sampling edge of the sampled signal:

[0241] The transmission delay on the transmission circuit with timing offset is adjusted until the center point of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampled signal, wherein the center point is the center point of the time window in which the data signal is located; or

[0242] The transmission delay on the transmission circuit with timing offset is adjusted until the sampling edge of the sampling signal is located in the time sub-window corresponding to the data signal transmitted on the transmission circuit with timing offset, wherein the time sub-window is a sub-window that includes the center point in the time window.

[0243] According to one aspect of this application, a computer program product is provided, comprising a computer program / instructions containing program code for performing the methods shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication section 1909, and / or installed from a removable medium 1911. When the computer program is executed by a central processing unit 1901, it performs various functions provided in embodiments of this application.

[0244] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0245] Figure 19 A schematic block diagram of a computer system architecture for implementing an electronic device according to embodiments of the present application is shown.

[0246] It should be noted that, Figure 19 The computer system 1900 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0247] like Figure 19 As shown, the computer system 1900 includes a central processing unit (CPU) 1901, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 1902 or programs loaded from storage section 1908 into random access memory (RAM) 1903. The RAM 1903 also stores various programs and data required for system operation. The CPU 1901, ROM 1902, and RAM 1903 are interconnected via a bus 1904. An input / output interface 1905 (I / O interface) is also connected to the bus 1904.

[0248] The following components are connected to the input / output interface 1905: an input section 1906 including a keyboard, mouse, etc.; an output section 1907 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1908 including a hard disk, etc.; and a communication section 1909 including a network interface card such as a local area network card, modem, etc. The communication section 1909 performs communication processing via a network such as the Internet. A drive 1190 is also connected to the input / output interface 1905 as needed. Removable media 1911, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on the drive 1190 as needed so that computer programs read from them can be installed into the storage section 1908 as needed.

[0249] Specifically, according to embodiments of this application, the processes described in the various method flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1909, and / or installed from removable medium 1911. When the computer program is executed by central processing unit 1901, it performs various functions defined in the system of this application.

[0250] According to another aspect of the embodiments of this application, an electronic device for implementing the above-described timing adjustment method is also provided. This electronic device may be... Figure 1 The terminal device or server shown. This embodiment uses this electronic device as an example for illustration. Figure 20 As shown, the electronic device includes a memory 2002 and a processor 2004. The memory 2002 stores a computer program, and the processor 2004 is configured to execute the steps in any of the above method embodiments via the computer program.

[0251] Optionally, in this embodiment, the aforementioned electronic device may be located in at least one of a plurality of network devices in a computer network.

[0252] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0253] S1, in response to the acquired first read instruction, generates a sampling signal, wherein the first read instruction is used to read training data, wherein the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

[0254] S2, sample the data signals transmitted on N transmission circuits on the sampling edge of the sampling signal to obtain the first sampled data, wherein N bits in the training data are transmitted as data signals on N transmission circuits, and the first sampled data is data represented by N bits;

[0255] S3, based on the values ​​of the same bits in the training data and the first sampled data, determine the transmission circuits with timing offsets among the N transmission circuits;

[0256] S4, adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampled signal.

[0257] Alternatively, as those skilled in the art will understand, Figure 20 The structure shown is for illustrative purposes only. Electronic devices can also be smartphones (such as Android phones, iOS phones, etc.), tablets, PDAs, mobile internet devices (MIDs), PADs, and other terminal devices. Figure 20 This does not limit the structure of the aforementioned electronic devices or electronic equipment. For example, electronic devices or electronic equipment may also include components that are more... Figure 20 The more or fewer components shown (such as network interfaces, etc.), or having the same Figure 20 The different configurations shown.

[0258] The memory 2002 can be used to store software programs and modules, such as the program instructions / modules corresponding to the timing adjustment method and apparatus in this embodiment. The processor 2004 executes various functional applications and data processing by running the software programs and modules stored in the memory 2002, thereby realizing the aforementioned timing adjustment method. The memory 2002 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 2002 may further include memory remotely located relative to the processor 2004, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. Specifically, the memory 2002 may be used, but is not limited to, to store training data, target data, and other information. As an example, such as... Figure 20 As shown, the memory 2002 may include, but is not limited to, the generation module 1802, sampling module 1804, determination module 1806, and adjustment module 1808 from the timing adjustment device. Furthermore, it may include, but is not limited to, other module units from the timing adjustment device, which will not be elaborated upon in this example.

[0259] Optionally, the aforementioned transmission device 2006 is used to receive or send data via a network. Specific examples of the network may include wired and wireless networks. In one example, the transmission device 2006 includes a Network Interface Controller (NIC), which can be connected to other network devices and a router via a network cable to communicate with the Internet or a local area network. In another example, the transmission device 2006 is a Radio Frequency (RF) module used for wireless communication with the Internet.

[0260] In addition, the aforementioned electronic device also includes: a display 2008 for displaying the aforementioned data signals; and a connection bus 2010 for connecting the various module components in the aforementioned electronic device.

[0261] In other embodiments, the aforementioned terminal device or server can be a node in a distributed system, wherein the distributed system can be a blockchain system, which is a distributed system formed by connecting multiple nodes through network communication. The nodes can form a peer-to-peer (P2P) network, and any form of computing device, such as a server, terminal, or other electronic device, can become a node in the blockchain system by joining this peer-to-peer network.

[0262] According to one aspect of this application, a computer-readable storage medium is provided, from which a processor of a computer device reads computer instructions, and the processor executes the computer instructions, causing the computer device to perform the timing adjustment method provided in the various alternative implementations of the timing adjustment aspect described above.

[0263] Optionally, in this embodiment, the computer-readable storage medium may be configured to store a computer program for performing the following steps:

[0264] S1, in response to the acquired first read instruction, generates a sampling signal, wherein the first read instruction is used to read training data, wherein the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

[0265] S2, sample the data signals transmitted on N transmission circuits on the sampling edge of the sampling signal to obtain the first sampled data, wherein N bits in the training data are transmitted as data signals on N transmission circuits, and the first sampled data is data represented by N bits;

[0266] S3, based on the values ​​of the same bits in the training data and the first sampled data, determine the transmission circuits with timing offsets among the N transmission circuits;

[0267] S4, adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampled signal.

[0268] Optionally, in this embodiment, those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0269] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0270] If the integrated units in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in the aforementioned computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause one or more computer devices (which may be personal computers, servers, or network devices, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0271] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0272] In the several embodiments provided in this application, it should be understood that the disclosed client can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between units or modules, and may be electrical or other forms.

[0273] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0274] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0275] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A timing adjustment method, characterized in that, include: In response to the acquired first read instruction, a sampling signal is generated, wherein the first read instruction is used to read training data, wherein the training data is known data represented by N bits, where N is a positive integer greater than or equal to 2; The data signals transmitted on N transmission circuits are sampled on the sampling edge of the sampling signal to obtain the first sampled data, wherein the N bits in the training data are transmitted as data signals on the N transmission circuits, and the first sampled data is data represented by the N bits; Based on the values ​​of the same bits in the training data and the first sampled data, determine the transmission circuits with timing offsets among the N transmission circuits; Adjusting the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampled signal includes: performing a first round of adjustment on the transmission delay of the transmission circuit with timing offset among the N transmission circuits until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampled signal; if, after performing the first round of adjustment, there are transmission circuits among the N transmission circuits whose transmitted data signal is not aligned with the target sampling edge, performing a second round of adjustment on the transmission delay of the transmission circuits whose transmitted data signal is not aligned with the target sampling edge until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, wherein the target sampling edge is the sampling edge that aligns with the center of the data signal transmitted on the N transmission circuits the most times.

2. The method according to claim 1, characterized in that, The step of determining the transmission circuits with timing offsets among the N transmission circuits based on the values ​​of the same bits in the training data and the first sampled data includes: Determine whether the values ​​of the same bits in the training data and the first sampled data are the same; If there are M bits with different values ​​among the N bits, the M transmission circuits among the N transmission circuits are determined as the transmission circuits with timing offset, wherein the M transmission circuits are used to transmit the data signals corresponding to the M bits, where M is greater than or equal to 1 and less than or equal to N.

3. The method according to claim 1, characterized in that, The first round of adjustment of the transmission delay on the transmission circuits with timing offsets among the N transmission circuits, until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampled signal, includes: Perform the following operations on each of the N transmission circuits that has a timing offset, wherein each of the transmission circuits that has a timing offset is the current transmission circuit when performing the following operations: When the data signal transmitted on the current transmission circuit corresponds to the high level of the sampling signal, the first edge of the time window where the data signal transmitted on the current transmission circuit is located is determined as the first position, and the second edge of the time window where the data signal is located is determined as the second position. Increase the transmission delay on the current transmission circuit until the first edge moves from the first position to the target position, and determine a first delay amount of the increased transmission delay on the current transmission circuit, wherein the target position corresponds to the sampling edge of the sampled signal; Reduce the transmission delay on the current transmission circuit until the second edge moves from the second position to the target position, and determine a second delay amount by which the transmission delay on the current transmission circuit is reduced; Adjust the time window of the data signal transmitted on the current transmission circuit according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampled signal.

4. The method according to claim 1, characterized in that, In the case where, after the first round of adjustments, there are N transmission circuits in the network where the transmitted data signal is not aligned with the target sampling edge, a second round of adjustments is made to the transmission delay of the transmission circuits where the transmitted data signal is not aligned with the target sampling edge, until the center of the transmitted data signal on each of the N transmission circuits is aligned with the target sampling edge, including: Repeat the following operation until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, wherein the current sampling edge is initialized as the sampling edge adjacent to the target sampling edge: The first group of sampling edges in the sampling signal, excluding the target sampling edge, is turned off by clock gating, while the target sampling edge is retained. Based on whether the center of the data signal transmitted on the N transmission circuits is aligned with the target sampling edge, determine whether there is a first group of data signals that is not aligned with the target sampling edge among the data signals transmitted on the N transmission circuits; In the presence of the first set of data signals, the second set of sampling edges in the sampling signal, excluding the current sampling edge, is closed by the clock gating, while the current sampling edge is retained. The second set of sampling edges includes the target sampling edge, and the current sampling edge is different from the target sampling edge. Based on whether the center of the first group of data signals is aligned with the current sampling edge, it is determined whether there is a second group of data signals in the first group of data signals that is not aligned with the second group of sampling edges; If a target data signal is present in the first group of data signals, the transmission delay on the transmission circuit that transmits the target data signal is adjusted, wherein the center of the target data signal is aligned with the current sampling edge before the adjustment and with the target sampling edge after the adjustment; In the presence of the second set of data signals, the current sampling edge is updated to the sampling edge in the sampling signal that was not retained by the clock gate.

5. The method according to claim 1, characterized in that, Adjusting the transmission delay on the transmission circuit with timing skew until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal includes: A target delay unit is determined in the delay control unit set on the transmission circuit with timing offset, and the corresponding data signal is transmitted from the output position of the target delay unit. The center of the data signal transmitted from the output position of the target delay unit is aligned with the sampling edge of the sampling signal. A delay control unit is set on each transmission path in the N transmission circuits. The delay control unit includes a preset number of delay units connected in series. Each delay unit is used to adjust the transmission delay on the transmission circuit by a unit duration.

6. The method according to claim 1, characterized in that, The method further includes: After the transmission delay on the transmission circuit with timing offset in the N transmission circuits is adjusted, N target transmission circuits are obtained, wherein the center of the data signal transmitted on each of the N target transmission circuits is aligned with the sampling edge of the sampled signal. In response to the acquired second read instruction, the data signals transmitted on the N target transmission circuits are sampled on the sampling edge of the sampling signal to obtain second sampled data. The second read instruction is used to read target data, wherein the target data is unknown and is represented by N bits. The N bits of the target data are transmitted as data signals on the N target transmission circuits, and the second sampled data is the data represented by the N bits.

7. The method according to claim 6, characterized in that, The method further includes: When the target memory is configured in read register mode, the second read instruction is sent, wherein the target memory is divided into multiple double-byte registers, and the second read instruction is used to read the target data in the target double-byte register among the multiple double-byte registers through the N target transmission circuits.

8. The method according to claim 6, characterized in that, In response to the acquired second read command, the data signals transmitted on the N target transmission circuits are sampled on the sampling edge of the sampling signal to obtain second sampled data, including: In response to the acquired second read instruction, the 128-bit memory read data bus signal, the 16-bit read data mask signal, and the 16-bit data bus toggle signal transmitted on the 160 target transmission circuits are sampled on the sampling edge of the sampling signal to obtain the second sampled data.

9. The method according to any one of claims 1 to 8, characterized in that, Adjusting the transmission delay on the transmission circuit with timing skew until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal includes: When the sampling edge is a rising edge, adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the rising edge of the sampling signal; or When the sampling edge is a falling edge, the transmission delay on the transmission circuit with timing offset is adjusted until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the falling edge of the sampling signal.

10. The method according to any one of claims 1 to 8, characterized in that, Adjusting the transmission delay on the transmission circuit with timing skew until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal includes: The transmission delay on the transmission circuit with timing offset is adjusted until the center point of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampled signal, wherein the center point is the center point of the time window in which the data signal is located; or The transmission delay on the transmission circuit with timing offset is adjusted until the sampling edge of the sampling signal is located in the time sub-window corresponding to the data signal transmitted on the transmission circuit with timing offset, wherein the time sub-window is a sub-window that includes the center point in the time window.

11. A timing adjustment device, characterized in that, include: The generation module is used to generate a sampling signal in response to the acquired first read instruction, wherein the first read instruction is used to read training data, wherein the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2; A sampling module is used to sample the data signals transmitted on N transmission circuits on the sampling edge of the sampling signal to obtain first sampled data, wherein the N bits in the training data are transmitted as data signals on the N transmission circuits, and the first sampled data is data represented by the N bits; The determination module is used to determine the transmission circuits with timing offsets among the N transmission circuits based on the values ​​of the same bits in the training data and the first sampled data. An adjustment module is used to adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampled signal. This includes: performing a first round of adjustment on the transmission delay of the transmission circuit with timing offset among the N transmission circuits until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampled signal; if, after performing the first round of adjustment, there are transmission circuits among the N transmission circuits whose transmitted data signal is not aligned with the target sampling edge, performing a second round of adjustment on the transmission delay of the transmission circuits whose transmitted data signal is not aligned with the target sampling edge until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, wherein the target sampling edge is the sampling edge that aligns with the center of the data signal transmitted on the N transmission circuits the most times.

12. The apparatus according to claim 11, characterized in that, The step of determining the transmission circuits with timing offsets among the N transmission circuits based on the values ​​of the same bits in the training data and the first sampled data includes: Determine whether the values ​​of the same bits in the training data and the first sampled data are the same; If there are M bits with different values ​​among the N bits, the M transmission circuits among the N transmission circuits are determined as the transmission circuits with timing offset, wherein the M transmission circuits are used to transmit the data signals corresponding to the M bits, where M is greater than or equal to 1 and less than or equal to N.

13. The apparatus according to claim 11, characterized in that, The first round of adjustment of the transmission delay on the transmission circuits with timing offsets among the N transmission circuits, until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampled signal, includes: Perform the following operations on each of the N transmission circuits that has a timing offset, wherein each of the transmission circuits that has a timing offset is the current transmission circuit when performing the following operations: When the data signal transmitted on the current transmission circuit corresponds to the high level of the sampling signal, the first edge of the time window where the data signal transmitted on the current transmission circuit is located is determined as the first position, and the second edge of the time window where the data signal is located is determined as the second position. Increase the transmission delay on the current transmission circuit until the first edge moves from the first position to the target position, and determine a first delay amount of the increased transmission delay on the current transmission circuit, wherein the target position corresponds to the sampling edge of the sampled signal; Reduce the transmission delay on the current transmission circuit until the second edge moves from the second position to the target position, and determine a second delay amount by which the transmission delay on the current transmission circuit is reduced; Adjust the time window of the data signal transmitted on the current transmission circuit according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampled signal.

14. The apparatus according to claim 11, characterized in that, In the case where, after the first round of adjustments, there are N transmission circuits in the network where the transmitted data signal is not aligned with the target sampling edge, a second round of adjustments is made to the transmission delay of the transmission circuits where the transmitted data signal is not aligned with the target sampling edge, until the center of the transmitted data signal on each of the N transmission circuits is aligned with the target sampling edge, including: Repeat the following operation until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, wherein the current sampling edge is initialized as the sampling edge adjacent to the target sampling edge: The first group of sampling edges in the sampling signal, excluding the target sampling edge, is turned off by clock gating, while the target sampling edge is retained. Based on whether the center of the data signal transmitted on the N transmission circuits is aligned with the target sampling edge, determine whether there is a first group of data signals that is not aligned with the target sampling edge among the data signals transmitted on the N transmission circuits; In the presence of the first set of data signals, the second set of sampling edges in the sampling signal, excluding the current sampling edge, is closed by the clock gating, while the current sampling edge is retained. The second set of sampling edges includes the target sampling edge, and the current sampling edge is different from the target sampling edge. Based on whether the center of the first group of data signals is aligned with the current sampling edge, it is determined whether there is a second group of data signals in the first group of data signals that is not aligned with the second group of sampling edges; If a target data signal is present in the first group of data signals, the transmission delay on the transmission circuit that transmits the target data signal is adjusted, wherein the center of the target data signal is aligned with the current sampling edge before the adjustment and with the target sampling edge after the adjustment; In the presence of the second set of data signals, the current sampling edge is updated to the sampling edge in the sampling signal that was not retained by the clock gate.

15. The apparatus according to claim 11, characterized in that, Adjusting the transmission delay on the transmission circuit with timing skew until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal includes: A target delay unit is determined in the delay control unit set on the transmission circuit with timing offset, and the corresponding data signal is transmitted from the output position of the target delay unit. The center of the data signal transmitted from the output position of the target delay unit is aligned with the sampling edge of the sampling signal. A delay control unit is set on each transmission path in the N transmission circuits. The delay control unit includes a preset number of delay units connected in series. Each delay unit is used to adjust the transmission delay on the transmission circuit by a unit duration.

16. The apparatus according to claim 11, characterized in that, The device further includes: After the transmission delay on the transmission circuit with timing offset in the N transmission circuits is adjusted, N target transmission circuits are obtained, wherein the center of the data signal transmitted on each of the N target transmission circuits is aligned with the sampling edge of the sampled signal. In response to the acquired second read instruction, the data signals transmitted on the N target transmission circuits are sampled on the sampling edge of the sampling signal to obtain second sampled data. The second read instruction is used to read target data, wherein the target data is unknown and is represented by N bits. The N bits of the target data are transmitted as data signals on the N target transmission circuits, and the second sampled data is the data represented by the N bits.

17. The apparatus according to claim 16, characterized in that, The device further includes: When the target memory is configured in read register mode, the second read instruction is sent, wherein the target memory is divided into multiple double-byte registers, and the second read instruction is used to read the target data in the target double-byte register among the multiple double-byte registers through the N target transmission circuits.

18. The apparatus according to claim 16, characterized in that, In response to the acquired second read command, the data signals transmitted on the N target transmission circuits are sampled on the sampling edge of the sampling signal to obtain second sampled data, including: In response to the acquired second read instruction, the 128-bit memory read data bus signal, the 16-bit read data mask signal, and the 16-bit data bus toggle signal transmitted on the 160 target transmission circuits are sampled on the sampling edge of the sampling signal to obtain the second sampled data.

19. The apparatus according to any one of claims 11 to 18, characterized in that, Adjusting the transmission delay on the transmission circuit with timing skew until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal includes: When the sampling edge is a rising edge, adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the rising edge of the sampling signal; or When the sampling edge is a falling edge, the transmission delay on the transmission circuit with timing offset is adjusted until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the falling edge of the sampling signal.

20. The apparatus according to any one of claims 11 to 18, characterized in that, Adjusting the transmission delay on the transmission circuit with timing skew until the center of the data signal transmitted on the transmission circuit with timing skew is aligned with the sampling edge of the sampled signal includes: The transmission delay on the transmission circuit with timing offset is adjusted until the center point of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampled signal, wherein the center point is the center point of the time window in which the data signal is located; or The transmission delay on the transmission circuit with timing offset is adjusted until the sampling edge of the sampling signal is located in the time sub-window corresponding to the data signal transmitted on the transmission circuit with timing offset, wherein the time sub-window is a sub-window that includes the center point in the time window.

21. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein the program can be executed by a terminal device or computer at runtime as described in any one of claims 1 to 10.

22. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method described in any one of claims 1 to 10.

23. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to execute the method described in any one of claims 1 to 10 through the computer program.

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