Control system for suppressing peak of output voltage and current of power amplifier

Abstract

The invention provides a control system for suppressing peak of output voltage and current of a power amplifier. The system comprises a PS signal processing module, a PL signal processing module and a high-voltage power circuit, wherein the PS is configured to receive a bus signal issued by an upper computer, execute digital Gaussian filtering processing on the bus signal and then transmit the bus signal to the PL signal processing module; meanwhile, relevant data of the power amplifier are collected and uploaded; the PL signal processing module is configured to receive a signal which is issued by the PS and is subjected to digital Gaussian filtering processing, and pre-process the signal; and transmitting the processed signal to a high-voltage power circuit to control the high-voltage power circuit to execute power conversion operation on the load. According to the method provided by the invention, smooth transition is realized at the phase jump position of the signal by adjusting the parameters of the digital Gaussian filter, so that the peak of the output voltage and current of the power amplifier is inhibited, the stress of a post-stage high-voltage power circuit device is reduced, the post-stage output power is effectively improved, and the stability of the power amplifier is improved.

Description

Technical Field

[0001] This application relates to the field of digital signal processing technology, and in particular to a control system for suppressing voltage and current spikes in the output voltage of a power amplifier. Background Technology

[0002] In current fields such as underwater exploration, communication, navigation, and marine resource exploration, underwater acoustic systems are indispensable core tools. Their working principle involves using underwater acoustic transducers to convert electrical signals into acoustic signals that propagate in the water and receive the returned acoustic signals. Power amplifiers are the core devices that drive various loads (such as transducers, antennas, and loudspeakers), and their performance directly determines the efficiency of the entire system.

[0003] With technological advancements, the power demands of underwater acoustic systems are increasing, particularly in communication and sonar systems where improving output power is of paramount importance. In underwater acoustic detection systems, power amplifiers drive transducers to radiate sound waves, and their output power directly affects the transducer's source level (radiated sound power level). Suppressing voltage and current spikes at the power amplifier's output to increase its effective output power remains a core research and development direction in underwater acoustics.

[0004] In underwater acoustic communication, signal generation, modulation, or transmission inevitably involves phase jumps due to factors such as modulation methods (e.g., PSK, BPSK phase modulation), sudden switching (e.g., multi-frequency signal switching, pulse signal initiation), or load disturbances. Phase jumps manifest as a step change in signal phase within a very short time (e.g., a 180° abrupt change), leading to drastic waveform jumps in the time domain (e.g., instantaneous reversal of a sinusoidal signal). This, in turn, introduces a large number of high-frequency harmonic components through Fourier transform (i.e., the "spectral diffusion" effect of phase jumps). When power amplifiers process these signals, the phase jump characteristics cause envelope fluctuations, resulting in significant voltage and current surges at the amplifier's output, triggering protection shutdown. For example, transformers are prone to magnetic saturation short circuits at voltage and current spikes, causing a surge in primary current and triggering protection. When the power amplifier output triggers protection, it often fails to reach the maximum output power required by the design, thus failing to meet the transducer's sound source emission level requirements.

[0005] Therefore, achieving high-quality, high-power signal amplification is crucial for the operation of power amplifiers. Effectively suppressing voltage and current spikes in the power amplifier output caused by signal phase transitions, thereby further increasing the power amplifier's output power and ensuring stable drive of the transducer to meet the corresponding sound source level, is an important means of improving the performance of underwater acoustic systems. Summary of the Invention

[0006] This application provides a control system for suppressing voltage and current spikes at the output of a power amplifier. To solve the above-mentioned technical problems, this application adopts the following technical methods: This application provides a control system for suppressing voltage and current spikes at the output of a power amplifier, comprising: The system includes PS and PL signal processing modules and a high-voltage power circuit; among which: The PS is configured to: receive bus signals from the host computer, perform digital Gaussian filtering on the bus signals and then transmit them to the PL signal processing module; at the same time, collect and upload relevant data of the power amplifier. The PL signal processing module is configured to: receive the signal sent by the PS after digital Gaussian filtering, perform preprocessing on it, and transmit the processed signal to the high-voltage power circuit to control the high-voltage power circuit to perform power conversion operation on the load.

[0007] Optionally, the PS includes a configuration management module, a network data interaction module, and a digital Gaussian filter processing module; wherein: The configuration management module is configured to: receive bus signals from the host computer, perform initialization and configuration management on the PS according to the bus signals, convert the bus signals into network data packets, and forward the network data packets to the network data interaction module; The network data interaction module is configured to: receive network data packets sent by the configuration management module, perform frame format parsing and preprocessing on the network data packets, and send the parsed and preprocessed signal data to the digital Gaussian filter processing module; The digital Gaussian filter processing module is configured to receive signal data sent by the network data interaction module, perform digital Gaussian filtering on it, and send the filtered signal data to the PL signal processing module.

[0008] Optionally, the configuration management module includes a peripheral driver initialization unit, an interrupt initialization unit, a memory configuration management unit, and a data encapsulation and forwarding unit; wherein: The peripheral driver initialization unit is configured to perform peripheral driver initialization processing on the PS (processing system) based on the received bus control signals. The interrupt initialization unit is configured to: configure the interrupt priority parameters of the network data interaction module according to the received bus control signals; The memory configuration management unit is configured to: divide the DDR3 memory into functional partitions and manage partition access permissions based on the received bus control signals; The data encapsulation and forwarding unit is configured to encapsulate the received bus data signals into network data packets according to a preset frame format and forward them to the network data interaction module.

[0009] Optionally, the network data interaction module includes a data verification unit and a preprocessing unit. The network data packet includes the digital Gaussian filter parameter set to be transmitted, the phase transition signal, the transmit start / stop command, and the transmit power level parameters; wherein: The data verification unit is configured to: perform verification and rejection processing on the received network data packets, filter valid signal data frames; parse the valid signal data frames according to the preset frame format protocol, extract various types of signal data, and store the various types of signal data into the corresponding partitions of DDR3 memory respectively; The preprocessing unit is configured to: call the phase transition signal stored in the corresponding partition of the DDR3 memory, perform boundary extension and outlier filtering preprocessing on it; and send the preprocessed phase transition signal, together with the digital Gaussian filter parameter group, transmit start / stop command and transmit power level parameters stored in the corresponding partition of the DDR3 memory, to the digital Gaussian filter processing module.

[0010] Optionally, the digital Gaussian filter processing module includes a parameter group switching unit, a filter coefficient retrieval unit, a window data reading unit, a multiply-accumulate operation unit, a sliding window processing unit, an error calibration unit, and a block iterative processing unit; wherein: The parameter group switching unit is configured to: receive transmit power level parameters and transmit start / stop commands, determine the appropriate filter parameter specifications based on the transmit power level parameters, and switch to the corresponding filter parameter group in conjunction with the trigger signal of the transmit start / stop command; The filter coefficient calling unit is configured to: call the filter coefficient plug-in pre-stored in DDR3 memory that matches the current power level based on the filter parameter group determined by the parameter group switching unit; The window data reading unit is configured to: read N points of data in the current window from the DDR3 circular buffer, centered on the current data point to be processed; and for boundary data points, call the preset extension data to extract window data that matches the Gaussian kernel size. The multiply-accumulate operation unit is configured to: read N filter coefficients corresponding to the current filter parameter group from the DDR3 memory coefficient area, multiply the window data with the corresponding filter coefficients point by point, and then perform an accumulation operation to obtain the filter value of the current data point; The sliding window processing unit is configured to slide the data processing window to the next data point to be processed, trigger the multiply-accumulate unit to repeatedly perform the multiply-accumulate operation until the filtering operation of all data points in the current data block is completed. The error calibration unit is configured to: perform calibration processing on rounding and truncation errors generated during the filtering operation; perform outlier filtering processing on the calibrated filtered data again to prevent errors in the filtered data; and write the final calibrated filtering result into the DDR3 memory filtering result area. The block iterative processing unit is configured to read the next block of preprocessed data from DDR3 memory, and sequentially trigger the parameter group switching unit, window data reading unit, multiply-accumulate operation unit, sliding window processing unit and error calibration unit to repeat the above processing steps until all block preprocessed data has completed filtering processing.

[0011] Optionally, the PS and PL signal processing modules of the system achieve bidirectional data interaction via an AXI bus; the PL signal processing module includes a data processing module, a PWM modulation module, and a PLL phase-locked loop module; wherein: The data processing module is configured to: receive the filtered signal data transmitted from the digital Gaussian filter processing module, perform preprocessing on it, and transmit it to the PWM modulation module; at the same time, it collects various operating data inside the power amplifier and transmits them to the PS via the AXI bus; The PWM modulation module is configured to: receive the transformed signal data sent by the data processing module, convert it into a PWM drive signal; and send the PWM drive signal to the high-voltage power circuit to drive the high-voltage power circuit to perform power conversion on the load. The PLL (phase-locked loop) module is configured to generate and output the relevant clock signals required by all processing logic in the system to achieve timing synchronization of each module.

[0012] Optionally, the data processing module in the PL signal processing module includes a data verification unit and an amplitude limiting conversion unit; wherein: The data verification unit is configured to receive the filtered signal data transmitted by the digital Gaussian filter processing module, perform validity verification processing on it, and transmit the verified signal data to the amplitude limiting conversion unit. The amplitude limiting conversion unit is configured to receive the verified signal data transmitted by the data verification unit, perform amplitude limiting conversion on it, and transmit the amplitude-limited signal data to the PWM modulation module.

[0013] This application has the following beneficial effects: The method proposed in this application, by adjusting the parameters of the digital Gaussian filter, enables a smooth transition at the phase transition of the signal, thereby suppressing the spikes in the output voltage and current of the power amplifier, reducing the stress on the high-voltage power circuit devices in the subsequent stage, effectively improving the output power of the subsequent stage, and enhancing the stability of the power amplifier. Attached Figure Description

[0014] Figure 1 The time-domain waveforms and phase change diagrams of the fitting switching signals at various power levels are provided for embodiments of this application. Figure 1 (a) is a time-domain waveform diagram of the jump signal for each power level; Figure 1 (b) is a time-domain waveform diagram of the jump signal for each power level; Figure 2 A detailed unfolded diagram of the time-domain waveform and phase change diagram of the fitting switching signal for each power level provided in the embodiments of this application; Figure 2 (a) A detailed unfolded diagram of the time-domain waveform of the jump signal for each power level; Figure 2 (b) A detailed unfolded diagram of the time-domain waveform of the jump signal for each power level; Figure 3 The spectral characteristics of the signals before and after digital Gaussian filtering at various power levels are provided for the embodiments of this application. Figure 4 A structural block diagram of a control system for suppressing output voltage and current spikes of a power amplifier, provided in an embodiment of this application; Figure 5 This is a structural block diagram of the configuration management module provided in an embodiment of this application; Figure 6 This is a structural block diagram of the network data interaction module provided in an embodiment of this application; Figure 7 This is a structural block diagram of the digital Gaussian filter processing module provided in an embodiment of this application; Figure 8 This is a structural block diagram of the data processing module provided in an embodiment of this application. Detailed Implementation

[0015] To facilitate understanding by those skilled in the art, the present application will be further described below in conjunction with embodiments and accompanying drawings. The content mentioned in the embodiments is not intended to limit the present application.

[0016] The phase transition phenomenon of a signal is essentially a drastic change in the time-domain waveform, which in turn triggers "spectral spread" in the frequency domain. This phase transition can cause steep edges in the signal waveform at the moment of transition (e.g., a sine wave instantly jumps from a positive peak to a negative peak). Such a step signal is undesirable at the output of a power amplifier, as it easily causes spectral leakage and spikes in the power amplifier's output voltage and current, potentially triggering protection shutdown or even damaging components.

[0017] A digital Gaussian filter is a low-pass filter in the frequency domain, effectively suppressing high-frequency components in a signal. Signal jumps (abrupt changes in the time domain) typically correspond to high-frequency components. By selecting a Gaussian filter with an appropriate bandwidth to suppress these high-frequency components, the signal spectrum can be controlled in the frequency domain, reducing spectral spread caused by jumps and thus improving the signal's phase continuity.

[0018] This application provides a control system for suppressing voltage and current spikes in the output of a power amplifier, which consists of two parts: a simulation model design of a digital Gaussian filter on the MATLAB simulation platform and a program design of a digital Gaussian filter on the ZYNQ series SoC digital processor platform.

[0019] The design steps for a digital Gaussian filter simulation model on the MATLAB simulation platform include: 1. Analysis of the characteristics of a digital Gaussian filter reveals that it is a typical LTI system. The filtering process is equivalent to the convolution of the input signal with a discrete Gaussian kernel. , where h[n] is the discrete Gaussian kernel (weights decay exponentially with distance). The LTI system does not introduce new frequency components, suppresses noise only through weighted averaging, and is not canceled out by the weights of surrounding stationary signals, thus preserving the step trend of the transition. The discrete-time Fourier transform (DTFT) of the discrete Gaussian kernel is approximately a Gaussian low-pass function: ,in The standard deviation of the Gaussian kernel is given, and Ts = 1 / fs is the sampling period. It is the angular frequency. Its cutoff frequency is... By adjusting It can precisely match the frequency characteristics of transitions, balancing noise reduction and transition preservation. A digital Gaussian filter is a linear filter that discretizes a continuous Gaussian function and uses it as a filter kernel (unit impulse response). This kernel is then convolved with the input signal to achieve smooth signal noise reduction. Assume the signal phase is... The signal after passing through the Gaussian filter is ,in For Gaussian kernel, This represents convolution. Convolution is essentially a weighted average of the signal, with the weights determined by a Gaussian kernel. Near transition points, the weighted average mixes the phase value of that point with the phase values ​​of surrounding points, thus smoothing the transition. In signal processing, it is generally desirable for filters not to introduce phase distortion. Gaussian filters are even functions, so their phase response is zero, but typical convolution introduces delay. To achieve zero-phase filtering, bidirectional filtering (i.e., forward filtering followed by reverse filtering, such as using the `filtfilt` function) can be used, resulting in a zero-phase-shift filter.

[0020] 2. Design a digital Gaussian filter model using the MATLAB simulation platform, and analyze the signal characteristics of a signal with phase transitions and the signal after filtering with the digital Gaussian filter. Since the output voltage and current spikes of the power amplifier are caused by signal phase transitions, the higher the output power, the larger the voltage and current transition spikes, thus requiring smoother filtering. The design model can dynamically adjust the parameters of the digital Gaussian filter according to the power level, so that the power amplifier maintains low distortion of the original signal at low power output, and keeps the voltage and current phase transition spikes smaller and the transition smoother at high power output. The specific design steps are as follows: 1. Generate phase transition signals of different power levels The excitation signal UI1, which carries a phase transition, is simulated using MATLAB. This signal can simulate the phase transition signal at the input of the power amplifier. Its characteristic parameters are: sampling frequency Fs = 96 kHz, total sampling time T_sum = 1e-2 s, and carrier signal F0 = 2 kHz. (The last sentence appears to be incomplete and possibly refers to a different simulation or simulation.) T_sum, 0.4 T_sum, 0.6 T_sum, 0.8 The T_sum time interval generates transition points with phase angles of 140°, -120°, -180°, and -270°. Based on the excitation signal UI1, the amplitude transformation of the transition signal is performed using correlation coefficients Coeff1=0.2, Coeff2=0.5, and Coeff3=1 to generate three transition signals of low, medium, and high power levels, Uo1, Uo2, and Uo3, respectively.

[0021] The `gaussdesign` function can be used to call a function kernel for filtering. Its characteristic parameters are the bandwidth-symbol-time product `bt`, the filter truncation symbol length `span`, and the number of symbol samples `sps`. A suitable `bt` value is determined for each power level. A larger `span` makes the filter closer to an ideal Gaussian filter, but increases computational complexity. `sps` is consistent with the system's oversampling rate. The `bt` value selection is based on the voltage level. The bandwidth is determined by the `bt` product; the smaller the `bt` product, the wider the filter bandwidth, the wider the time-domain pulse, and the better the smoothing effect. A larger `bt` product results in a narrower frequency-domain bandwidth and a steeper pulse shaping.

[0022] Design parameters for digital Gaussian filters with three power levels. For the low power level, a larger bt value is chosen to maintain signal quality; the calculated design parameters are bt=0.88, span=6, and sps3=8. For the medium power level, a medium bt value is chosen to balance filtering and signal quality; the calculated design parameters are bt=0.78, span=6, and sps3=8. For the high power level, due to the greater voltage and current stress and spikes caused by phase transitions during high-power output, a smoother filtering is required; therefore, a smaller bt value is chosen; the calculated design parameters are bt=0.68, span=6, and sps3=8. The above parameters are set, and digital Gaussian filters are used to digitally filter the power signals of levels Uo1, Uo2, and Uo3. The digitally filtered signals are then subjected to group delay compensation using the filtfilt function. The filtfilt function is a zero-phase forward-backward filtering function that can eliminate the phase shift introduced by ordinary filtering functions.

[0023] Apply Hilbert transform to Uo1, Uo2, and Uo3 respectively Obtain the entanglement phase The range is Then, the instantaneous phase is obtained by unwinding the entangled phase. After unwinding the signals at power levels Uo1, Uo2, and Uo3, it is easier to calculate their linear phase degree. The sum of squared residuals (the degree to which the phase deviates from linearity) The total sum of squares (the total degree of phase fluctuation) Phase mean .

[0024] Fit the time-domain waveforms and phase changes of the switching signals at each power level, as follows: Figure 1 , Figure 2 As shown. Figure 1 (a) Comparison of waveforms of phase-jump signals at different power levels before and after digital Gaussian filtering. Figure 1 (b) is the phase angle (in radians) at the moment of signal transition. Figure 2 For detailed unfolded diagrams, Figure 2 (a) The magnified comparison at the phase transition point is clearly visible. The peaks of the signal before and after the digital Gaussian filter at the phase transition point have changed significantly. From the time domain perspective, the transition point after the digital Gaussian filter has shown a smooth transition, which helps to reduce the stress on the voltage and current at the output of the power amplifier and suppress voltage and current peaks. Figure 2 (b) To fit the phase linearity of the signals before and after digital Gaussian filtering at each power level, the linear phase ratios R1^2 of the Uo1 signal and the filtered signal are 0.9991 and 0.9991, respectively; the linear phase ratios R2^2 of the Uo2 signal and the filtered signal are 0.9991 and 0.9993, respectively; and the linear phase ratios R3^2 of the Uo3 signal and the filtered signal are 0.9991 and 0.9990, respectively. The closer R^2 is to 1, the better the linearity. All filtered signals satisfy the linear phase characteristic.

[0025] Analyze the spectral characteristics of the signals before and after digital Gaussian filtering at various power levels, such as... Figure 3 As shown, from the frequency domain perspective, the signal spectrum filtered by the digital Gaussian filter has no other frequency components, preserving the original frequency information and enabling low-distortion transmission of effective information.

[0026] Derive the coefficients of the digital Gaussian filter Leveraging the features of the ZYNQ series SoCs, the parameters of digital Gaussian filters designed on the MATLAB simulation platform can be easily imported into the ZYNQ digital processor platform for implementation. The relevant design parameters of the digital Gaussian filter can be exported using the fopen and fprintf functions, generating a coe file from the correlation coefficients. This file can be easily updated and used by the digital processor.

[0027] To solve the above technical problems, such as Figure 4 As shown, this application employs a control system for suppressing voltage and current spikes at the output of a power amplifier. Its core utilizes a PS (processing system) plus a PL signal processing module. The specific working process is as follows: The PS (Processing System) is the core of this power amplifier output spike suppression control system. Its core value lies in achieving precise execution of host computer commands and high-quality optimization of phase transition signals through modular collaboration of "configuration-analysis-filtering," providing reliable input for the subsequent PL signal processing module and suppressing voltage and current spikes in the power conversion process from the source. The PS is configured to: receive bus signal data from the host computer, perform digital Gaussian filtering on the signal data, and then transmit it to the PL signal processing module; simultaneously, it acquires the power amplifier's operating data (such as output parameters, fault status, etc.) through a dedicated AXI communication interface and uploads it to the host computer, forming a closed-loop control of "command issuance-status feedback."

[0028] To achieve the above functions, such as Figure 4 As shown, the PS integrates three core sub-modules: a configuration management module, a network data interaction module, and a digital Gaussian filter processing module. These sub-modules are closely interconnected, forming a complete signal processing chain. The specific configuration and implementation are as follows: Configuration Management Module: Core of System Initialization and Data Transformation The configuration management module is the fundamental module for PS startup, operation, and data input. It is responsible for converting host computer bus signals into internal data recognizable by the system, and simultaneously initializing and configuring hardware resources. This module is configured to: receive bus signals from the host computer; perform comprehensive initialization and resource management on the PS according to the configuration instructions within the signals; encapsulate the data portion of the signals into standardized network data packets; and forward them to the network data interaction module. For example... Figure 5 As shown, it integrates a peripheral driver initialization unit, an interrupt initialization unit, a memory configuration management unit, and a data encapsulation and forwarding unit. The functions of each unit are implemented as follows: The peripheral driver initialization unit is configured to: extract peripheral configuration instructions from the bus control signals, perform driver initialization processing on various peripherals of the PS (such as bus interface, data acquisition interface, DDR memory controller, etc.), so that the peripheral hardware enters the working state according to the preset protocol, and ensures smooth hardware path for data transmission and acquisition.

[0029] The interrupt initialization unit is configured to set the interrupt priority of the network data interaction module according to the interrupt configuration parameters in the bus control signals. By setting critical tasks such as data reception and parsing as high priority, it ensures that network data processing is not blocked when multiple modules are running concurrently, thus improving system real-time performance.

[0030] The memory configuration management unit is configured to respond to memory planning instructions in the bus control signals, perform functional partitioning of DDR3 memory, clearly define dedicated partitions such as parameter configuration area, raw signal area, ring buffer, and filtering result area, and configure independent read and write permissions and address mappings for each partition to avoid data storage conflicts between different modules and improve memory access efficiency.

[0031] The data encapsulation and forwarding unit is configured to: separate the data portion and control commands from the bus signals, encapsulate the data signals into network data packets according to a preset frame format (including frame header, data type, valid data, and check bits), and forward them to the network data interaction module through the internal high-speed link, providing standardized input for subsequent parsing and processing.

[0032] Network data interaction module: Data verification and preprocessing hub The network data interaction module is a crucial link between the configuration management module and the digital Gaussian filter processing module. Its core function is to filter valid data, optimize signal quality, and complete data integration. This module is configured to: receive network data packets sent by the configuration management module, perform frame format parsing and preprocessing, and transmit the compliant signal data to the digital Gaussian filter processing module. Figure 6 As shown, it integrates a data verification unit and a preprocessing unit. The network data packets it processes cover digital Gaussian filter parameter sets, phase transition signals, transmit start / stop commands, and transmit power level parameters. The functions of each unit are as follows: The data verification unit is configured to: perform integrity verification on the received network data packets using the CRC cyclic redundancy check algorithm, and remove invalid data packets with transmission errors or broken frame structures; parse valid data frames according to the preset frame format protocol, accurately extract four types of core data, and store them in the corresponding pre-partitioned partitions of DDR3 memory according to the memory partitioning rules, while recording the storage address for subsequent retrieval.

[0033] The preprocessing unit is configured to: call the phase transition signal stored in DDR3 memory through memory address index and perform targeted preprocessing on it—use a symmetric extension algorithm to complete the boundary de-extension to avoid boundary distortion in subsequent filtering; filter outliers and remove distorted data points through threshold judgment method; after preprocessing, summarize the optimized phase transition signal with the filter parameter group, transmit start / stop command and power level parameters stored in DDR3 memory to form a complete filter input dataset and send it to the digital Gaussian filter processing module.

[0034] The digital Gaussian filter processing module is the core functional module of the PS (Power Signal Processor) for signal noise reduction and optimization. Its core value lies in dynamically matching filter parameters and suppressing noise in phase-change signals through precise calculations, providing a high-quality signal for subsequent power control. This module is configured to: receive signal data transmitted from the network data interaction module, perform digital Gaussian filtering, and then transmit the result to the PL (Power Probe) signal processing module. Figure 7 As shown, it integrates seven functional units: parameter group switching unit, filter coefficient retrieval unit, window data reading unit, multiplication and accumulation operation unit, sliding window processing unit, error calibration unit, and block iterative processing unit. Each unit works together to form a pipeline processing link. The specific functions are implemented as follows: The parameter group switching unit is configured to receive the transmit power level parameters and transmit start / stop commands from the summary data, determine the specifications such as filter bandwidth and smoothing coefficient based on the power level parameters, and automatically switch to the corresponding filter parameter group in combination with the triggering logic of the transmit start / stop commands to ensure that the filter configuration is accurately matched with the system operating conditions.

[0035] The filter coefficient calling unit is configured to: use the parameter group determined by the parameter group switching unit as the index, call the target digital filter coefficient plug-in pre-stored in the corresponding power level partition through the DDR3 memory high-speed interface, and ensure the integrity of the coefficients through a verification mechanism during the call.

[0036] The window data reading unit is configured to: read N consecutive data points (N is the same as the Gaussian kernel size) from the DDR3 circular buffer, with the current data point to be processed as the center; for boundary data points, call the preset symmetric extension data to fill the window, and finally form a standardized window data that matches the Gaussian kernel.

[0037] The multiply-accumulate unit is configured to read the N-point filter coefficients corresponding to the current parameter group, use a hardware acceleration architecture to multiply the window data with the coefficients point by point and then accumulate them to quickly obtain the filter value of the current data point. The operation latency is controlled at the microsecond level to meet real-time requirements.

[0038] The sliding window processing unit is configured to slide the window one point along the signal sequence after the current data point is processed, triggering the multiply-accumulate operation unit to repeatedly perform the operation until all data points of the current data block are processed, thereby achieving continuous signal filtering.

[0039] The error calibration unit is configured to: perform error calibration on the current data block filter value, correct rounding error using rounding method and truncation error using low-order padding method; filter outliers again after calibration, and finally write high-quality results into the DDR3 filter result area.

[0040] The block iterative processing unit is configured as follows: as the core of process control, it reads the next block of data to be processed. If a power level or start / stop command update is detected, it will first trigger the parameter group to switch again. Then, it will trigger each functional unit to repeat the processing process in sequence until all block data has been filtered.

[0041] The PL signal processing module is a key execution unit in this system, connecting the PS (Power Supply) and the high-voltage power circuit. Its core value lies in converting the high-quality digitally filtered signal output by the PS into control signals that can directly drive power devices, while simultaneously providing real-time feedback on the power amplifier's operating status. It establishes a bidirectional data interaction link with the PS via an AXI bus, ensuring both high-speed signal transmission and closed-loop feedback of operating data. The PL signal processing module is configured to: receive the digitally Gaussian filtered signal data from the PS; perform preprocessing on it to adapt to the high-voltage power circuit; and transmit the processed drive signal to the high-voltage power circuit to precisely control its power conversion operation on the load.

[0042] To achieve the above functions, such as Figure 4 As shown, the PL signal processing module integrates three major functional sub-modules: a data processing module, a PWM modulation module, and a PLL phase-locked loop module. Each sub-module works collaboratively, undertaking the responsibilities of signal optimization, drive generation, and timing control, respectively. The specific configuration and implementation are as follows: Data processing module: The data processing module is the "signal input center and data feedback core" of the PL, responsible for interfacing with the PS output signal and acquiring the power amplifier status. Its overall configuration is as follows: it receives filtered signal data transmitted from the digital Gaussian filter processing module, performs preprocessing on it, and transmits it to the PWM modulation module; simultaneously, it acquires various internal operating data of the power amplifier (such as output voltage, current, device temperature, fault indicators, etc.) through a dedicated acquisition interface, and transmits the data back to the PS via the AXI bus, providing a basis for closed-loop control of the PS and the host computer. Figure 8 As shown, this module integrates a data verification unit and a limiting conversion unit. The functions of each unit are implemented as follows: The data verification unit is configured to: receive the filtered signal data transmitted by the PS, and perform validity verification using a dual verification mechanism of frame header matching + CRC check. First, the target data frame is filtered by the frame header identifier, and then the CRC check is performed on the data frame to eliminate the bit error data that may be introduced during transmission. The valid signal data that passes the verification is transmitted to the amplitude limiting conversion unit in real time to ensure the reliability of the data processed subsequently.

[0043] The amplitude limiting conversion unit is configured to: receive the verified signal data transmitted by the data verification unit, perform preprocessing based on the input characteristics of the high-voltage power circuit—controlling the signal amplitude within the safe driving range of the power module through the amplitude limiting algorithm to avoid damage to the power devices by excessive signal amplitude; simultaneously perform signal format conversion, converting the digital signal output by the PS into a parallel data format that can be directly computed within the PL; and transmit the standardized signal data after amplitude limiting conversion to the PWM modulation module to provide an adaptive input for precise modulation.

[0044] The PWM modulation module is the "power drive generation unit" of the PL. Its core function is to convert the optimized signal into a PWM drive signal that can be recognized by the high-voltage power circuit. It is configured to: receive the transformed signal data sent by the data processing module; based on the power control command (such as the output power level), convert it into a PWM drive signal with an adjustable duty cycle through the built-in PWM generator; and send the PWM drive signal to the high-voltage power circuit through the optocoupler isolation interface. This precisely controls the on / off timing and duty cycle of the power switches such as IGBTs and MOSFETs inside the module, thereby driving the high-voltage power circuit to perform stable power conversion on the load according to preset requirements, and suppressing the generation of voltage and current spikes from the control level.

[0045] The PLL (Phase-Locked Loop) module is the "timing control core" of the power supply (PL). It is configured to generate a reference clock via an external crystal oscillator, which, after frequency multiplication and division by the PLL circuit, outputs the relevant clock signals required by all system processing logic (such as the PS-PL interaction clock, PWM modulation clock, and data acquisition clock). The phase deviation of all clock signals is controlled within 1ns to ensure strict synchronization of the timing of data interaction between the PS and PL, PWM modulation and power switching actions, and operational data acquisition, avoiding power signal conversion distortion and spikes caused by timing errors.

[0046] In summary, the method proposed in this application, by adjusting the parameters of the digital Gaussian filter, enables a smooth transition at the phase transition of the signal, thereby suppressing the spikes in the output voltage and current of the power amplifier, reducing the stress on the high-voltage power circuit devices in the subsequent stage, effectively improving the output power of the subsequent stage, and enhancing the stability of the power amplifier.

[0047] The above embodiments are preferred implementations of this application. In addition, this application can be implemented in other ways. Any obvious substitutions without departing from the concept of this technical solution are within the protection scope of this application.

[0048] To facilitate understanding by those skilled in the art of the improvements made by this application compared to the prior art, some of the accompanying drawings and descriptions have been simplified, and for clarity, some other elements have been omitted from this application. Those skilled in the art should realize that these omitted elements may also constitute the content of this application.

Claims

1. A control system for suppressing voltage and current spikes at the output of a power amplifier, characterized in that, include: The system includes PS and PL signal processing modules and a high-voltage power circuit; among which: The PS is configured to: receive bus signals from the host computer, perform digital Gaussian filtering on the bus signals and then transmit them to the PL signal processing module; at the same time, collect and upload relevant data of the power amplifier. The PL signal processing module is configured to: receive the signal sent by the PS after digital Gaussian filtering, perform preprocessing on it, and transmit the processed signal to the high-voltage power circuit to control the high-voltage power circuit to perform power conversion operation on the load.

2. The system according to claim 1, characterized in that, PS includes a configuration management module, a network data interaction module, and a digital Gaussian filter processing module; among which: The configuration management module is configured to: receive bus signals from the host computer, perform initialization and configuration management on the PS according to the bus signals, receive and convert the bus signals into network data packets, and forward the network data packets to the network data interaction module; The network data interaction module is configured to: receive network data packets sent by the configuration management module, perform frame format parsing and preprocessing on the network data packets, and send the parsed and preprocessed signal data to the digital Gaussian filter processing module; The digital Gaussian filter processing module is configured to receive signal data sent by the network data interaction module, perform digital Gaussian filtering on it, and send the filtered signal data to the PL signal processing module.

3. The system according to claim 2, characterized in that, The configuration management module includes a peripheral driver initialization unit, an interrupt initialization unit, a memory configuration management unit, and a data encapsulation and forwarding unit; among which: The peripheral driver initialization unit is configured to perform peripheral driver initialization processing on the PS based on the received bus control signals. The interrupt initialization unit is configured to: configure the interrupt priority parameters of the network data interaction module according to the received bus control signals; The memory configuration management unit is configured to: divide the DDR3 memory into functional partitions and manage partition access permissions based on the received bus control signals; The data encapsulation and forwarding unit is configured to encapsulate the received bus data signals into network data packets according to a preset frame format and forward them to the network data interaction module.

4. The system according to claim 3, characterized in that, The network data interaction module includes a data verification unit and a preprocessing unit. The network data packet includes the digital Gaussian filter parameter set to be transmitted, the phase transition signal, the transmit start / stop command, and the transmit power level parameters; wherein: The data verification unit is configured to: perform verification and rejection processing on the received network data packets, filter valid signal data frames; parse the valid signal data frames according to the preset frame format protocol, extract various types of signal data, and store the various types of signal data into the corresponding partitions of DDR3 memory respectively; The preprocessing unit is configured to: call the phase transition signal stored in the corresponding partition of the DDR3 memory, perform boundary extension and outlier filtering preprocessing on it; and send the preprocessed phase transition signal, together with the digital Gaussian filter parameter group, transmit start / stop command and transmit power level parameters stored in the corresponding partition of the DDR3 memory, to the digital Gaussian filter processing module.

5. The system according to claim 4, characterized in that, The digital Gaussian filter processing module includes a parameter group switching unit, a filter coefficient retrieval unit, a window data reading unit, a multiply-accumulate operation unit, a sliding window processing unit, an error calibration unit, and a block iterative processing unit; among which: The parameter group switching unit is configured to: receive transmit power level parameters and transmit start / stop commands, determine the appropriate filter parameter specifications based on the transmit power level parameters, and switch to the corresponding filter parameter group in conjunction with the trigger signal of the transmit start / stop command; The filter coefficient calling unit is configured to: call the filter coefficient plug-in pre-stored in DDR3 memory that matches the current power level based on the filter parameter group determined by the parameter group switching unit; The window data reading unit is configured to: read N points of data in the current window from the DDR3 circular buffer, centered on the current data point to be processed; and for boundary data points, call the preset extension data to extract window data that matches the Gaussian kernel size. The multiply-accumulate operation unit is configured to: read N filter coefficients corresponding to the current filter parameter group from the DDR3 memory coefficient area, multiply the window data with the corresponding filter coefficients point by point, and then perform an accumulation operation to obtain the filter value of the current data point; The sliding window processing unit is configured to slide the data processing window to the next data point to be processed, trigger the multiply-accumulate unit to repeatedly perform the multiply-accumulate operation until the filtering operation of all data points in the current data block is completed. The error calibration unit is configured to: perform calibration processing on rounding and truncation errors generated during the filtering operation; perform outlier filtering processing on the calibrated filtered data again to prevent errors in the filtered data; and write the final calibrated filtering result into the DDR3 memory filtering result area. The block iterative processing unit is configured to read the next block of preprocessed data from DDR3 memory, and sequentially trigger the parameter group switching unit, window data reading unit, multiply-accumulate operation unit, sliding window processing unit and error calibration unit to repeat the above processing steps until all block preprocessed data has completed filtering processing.

6. The system according to claim 5, characterized in that, The system's PS and PL signal processing modules achieve bidirectional data interaction via the AXI bus; the PL signal processing module includes a data processing module, a PWM modulation module, and a PLL phase-locked loop module; wherein: The data processing module is configured to: receive the filtered signal data transmitted from the digital Gaussian filter processing module, perform preprocessing on it, and transmit it to the PWM modulation module; at the same time, it collects various operating data inside the power amplifier and transmits them to the PS via the AXI bus; The PWM modulation module is configured to: receive the transformed signal data sent by the data processing module, convert it into a PWM drive signal; and send the PWM drive signal to the high-voltage power circuit to drive the high-voltage power circuit to perform power conversion on the load. The PLL (phase-locked loop) module is configured to generate and output the relevant clock signals required by all processing logic in the system to achieve timing synchronization of each module.

7. The system according to claim 6, characterized in that, The data processing module in the PL signal processing module includes a data verification unit and an amplitude limiting conversion unit; wherein: The data verification unit is configured to receive the filtered signal data transmitted by the digital Gaussian filter processing module, perform validity verification processing on it, and transmit the verified signal data to the amplitude limiting conversion unit. The amplitude limiting conversion unit is configured to receive the verified signal data transmitted by the data verification unit, perform amplitude limiting conversion on it, and transmit the amplitude-limited signal data to the PWM modulation module.

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