Host recovery for stuck condition

Abstract

This disclosure relates to host recovery for a stuck condition. A host system can transmit a first command for a memory system to transition from a first power mode to a second power mode (e.g., a low power mode). In some cases, the host system can transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system can activate a timer associated with a timeout condition for exiting the second power mode and can determine that a duration indicated by the timer expires. In some examples, the host system can transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 648,399, filed January 19, 2022, entitled "HOST RECOVERY FOR A STUCK CONDITION," and U.S. Provisional Patent Application No. 63 / 162,335, filed March 17, 2021, entitled "HOST RECOVERY FOR A STUCK CONDITION," each of which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to host recovery for stuck conditions. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even without an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a controller configured such that the apparatus: transmits a first command for a memory system to transition from a first power mode to a second power mode, the first power mode being associated with executing the received command and the second power mode being associated with disabling one or more components associated with the memory system; transmits a second command for the memory system to exit the second power mode based on the transmission of the first command; activates a timer associated with a timeout condition for exiting the second power mode based on the transmission of the second command to exit the second power mode; determines, based on the activation of the timer, that a duration indicated by the timer has expired; and transmits a third command for the memory system to perform a hardware reset operation based on the determination that the duration of the timer has expired.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: transmit a first command for a memory system to transition from a first power mode to a second power mode, the first power mode being associated with executing the received command and the second power mode being associated with disabling one or more components associated with the memory system; based on transmitting the first command, transmit a second command for the memory system to exit the second power mode; based on transmitting the second command to exit the second power mode, activate a timer associated with a timeout condition for exiting the second power mode; based on activating the timer, determine that a duration indicated by the timer has expired; and based on determining that the timer's duration has expired, transmit a third command for the memory system to perform a hardware reset operation.

[0008] Describe a method. The method may include: transmitting a first command for a memory system to transition from a first power mode to a second power mode, the first power mode being associated with executing the received command and the second power mode being associated with disabling one or more components associated with the memory system; transmitting a second command for the memory system to exit the second power mode based on transmitting the first command; activating a timer associated with a timeout condition for exiting the second power mode based on transmitting the second command to exit the second power mode; determining, based on activating the timer, that a duration indicated by the timer has expired; and transmitting a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer has expired. Attached Figure Description

[0009] Figure 1This document describes instances of systems that support host recovery for stuck conditions, based on examples disclosed herein.

[0010] Figure 2 This document describes an example of a flowchart supporting host recovery for stuck conditions, based on examples disclosed herein.

[0011] Figure 3 A block diagram illustrating a host system that supports host recovery for stuck conditions, based on examples disclosed herein.

[0012] Figure 4 The flowchart illustrates one or more methods for supporting host recovery under stuck conditions, based on examples disclosed herein. Detailed Implementation

[0013] In some systems, the memory system can be powered down (e.g., enter hibernation mode), thereby saving power and resources associated with operating the memory system. In this case, the memory system can be prevented from operating during the discharge time used to enter hibernation mode. The memory system can receive a request to power on (e.g., enter active mode) during the discharge time, which can interrupt the memory system when it is powered down. For example, a user can double-tap the power button of the device. The first press of the power button causes the host system to enter hibernation mode, and the second press of the power button causes the host system to exit hibernation mode. The double-tap of the power button causes the memory system to attempt to exit hibernation mode before the discharge time is completed. If the memory system fails to fully power down (e.g., enter hibernation mode) before moving back to a higher power mode (e.g., active mode) in response to receiving a power-on request, the memory system may experience a stuck condition. In this case, if the memory system receives a power-on request before the discharge time expires (e.g., receives the request during the duration of the discharge time), the memory system may experience an increased latency for operation, which can lead to a performance degradation of the memory system.

[0014] Interruptions to the memory system during a power-down cycle (e.g., entering hibernation mode) can cause the memory system to experience a jam condition, under which the memory system may be unable to transmit or receive commands or perform operations. If the memory system is interrupted during a power-down cycle, the voltage of the memory system may fail to meet a voltage threshold condition. For example, the voltage of the memory system may be greater than 100mV, indicating that the memory system has not been fully powered down during the discharge time. In this case, the memory system may be unable to perform operations associated with the memory system, thereby increasing the latency of other operations associated with the host system and reducing read, write, and erase speeds and efficiency. In some cases, the host system may cause the memory system to undergo a power cycle to resolve the jam condition. However, power cycles can take a long time. Therefore, techniques for detecting jam conditions and reducing the latency of resolving jam conditions are desirable.

[0015] This describes systems, apparatus, and techniques for performing recovery procedures in response to stuck conditions. In some cases, the host system may transmit a command to enter a hibernation mode. The host system may isolate the memory system from a voltage supply and then connect the memory system to the voltage supply directly in response to input received from a user device, thereby disconnecting and turning the memory system on and off respectively. The host system may transmit a command to enter an active mode after connecting the memory system to the voltage supply. In some cases, the host system may detect that the memory system has failed to wake up (e.g., enter active mode) in response to transmitting a command to enter active mode. In this case, the host system may activate a timer and determine that the duration of the timer expires before receiving an indication that the memory system is in active mode, thereby indicating that the memory system may have experienced a stuck condition. The host system may transmit a command to perform a hardware reset operation (e.g., a recovery operation) directly in response to determining that the duration of the timer has expired. The hardware reset operation may be different from a power cycling operation.

[0016] The memory system can recover from a stuck condition by receiving a command to perform a hardware reset and then performing the hardware reset operation. The host system can receive a response from the memory system after transmitting a command to perform a hardware reset operation and indicating that the memory system is available for operation. The host system can transmit commands to perform access operations, such as read and write operations. This technique can increase the overall performance of the memory system, thereby reducing latency for other operations associated with the memory system. Directly transmitting a command to perform a hardware reset operation in response to the detection of a stuck condition improves the overall efficiency of the memory system, resulting in improved read, write, and erase speeds, reduced power consumption, improved processing time, and the like.

[0017] Firstly, in reference Figure 1The features of this disclosure are described within the context of the system. (Referencing...) Figure 2 The features of this disclosure are described in the context of the flowchart. These and other features of this disclosure are further illustrated by reference. Figures 3 to 4 The device diagrams and flowcharts related to host recovery for stuck conditions are described and are presented in the context of the device diagrams and flowcharts.

[0018] Figure 1 This describes an instance of system 100 that supports host recovery for stuck conditions, based on examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing means.

[0021] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled and communicate with the memory device 130 to perform operations at the memory device 130 that are generally referred to as access operations, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic for the operation of the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or another memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or another memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and said data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0028] although Figure 1 The example of memory system 110 described herein includes memory system controller 115; however, in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described herein, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, memory cells within different blocks 170 can be operated on in parallel, as long as the different blocks 170 are in different planes 165. In some cases, parallel operations in different planes 165 may be subject to one or more limitations, such as performing the same operation on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit (e.g., a set of memory cells) of memory that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit (e.g., a set of memory cells) of memory that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0036] System 100 may include any number of non-transitory computer-readable media supporting host recovery for stuck conditions. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0037] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system. Alternatively, memory system 110 may include non-volatile memory.

[0038] The host system 105 can perform a recovery operation for a stuck condition. For example, the host system 105 can transmit a command to the memory system 110 to switch from an active mode (e.g., a first power mode) to a hibernation mode (e.g., a second power mode). In this case, the memory system 110 can enter hibernation mode, and the host system 105 can transmit a command to exit hibernation mode and enter active mode. The host system 105 can detect a timeout condition after exiting hibernation mode. For example, the host system 105 can activate a timer associated with the timeout condition in response to transmitting the command to exit hibernation mode. The host system 105 can determine that the duration indicated by the timer has expired. In this case, the host system 105 can transmit a command to perform a hardware reset to the memory system 110. The hardware reset operation can be configured to perform a recovery operation for a stuck condition, thereby allowing the memory system to experience improved read, write, and erase speeds, reduced power consumption, and improved processing time. The hardware reset operation can be different from the power cycling operation.

[0039] Figure 2 This describes an example of flowchart 200 supporting host recovery for stuck conditions, based on examples disclosed herein. Operation of flowchart 200 can be implemented by any device or component thereof as described herein. For example, operation of flowchart 200 can be performed by, as referenced... Figure 1The host system described herein may be implemented. Alternative instances of the following may be implemented, in which some steps are performed in a different order or not at all. Some steps may also include additional features not mentioned below. Flowchart 200 illustrates the techniques in which the host system may perform recovery operations for stuck conditions.

[0040] Aspects of flowchart 200 may be implemented by a controller and other components. Alternatively, aspects of flowchart 200 may be implemented as instructions stored in a controller (e.g., a controller coupled to a host system). For example, the instructions, when executed by the controller (e.g., host system controller 106), may cause the controller to perform the operations of flowchart 200.

[0041] In some systems, a user can double-tap the power button on a user device (e.g., containing a memory system), which can power the memory system on and off for a limited time. In this scenario, the memory system can be interrupted when the user device receives a second tap to power it off (e.g., enter hibernation mode). If the memory system is interrupted during a power-down cycle, it may experience a stuck condition where it may be unable to transmit, receive, or operate commands. In this case, the memory system may undergo a power cycle to reset itself, resulting in increased latency for operation. A stuck condition may also occur if the voltage associated with the memory system fails to meet a threshold that initializes the memory system, thus indicating that the memory system fails to enter hibernation mode (e.g., complete power-down).

[0042] A stuck condition may occur if the memory system fails to fully power down before returning to a higher power mode (e.g., powering on). For example, a user of a mobile device might press a button to power off the device, but then immediately press the button again to power it down (e.g., wake it up). In some cases, if the memory system does not have sufficient time to fully power down, it may fail to reinitialize immediately after power-on. Performing power cycling to resolve stuck conditions can increase the wake-up time associated with the memory system, potentially increasing it from a few milliseconds to hundreds of milliseconds. A technique can be described for the host system to detect timeout conditions after sending an activation command. If a timeout condition is detected, the host system can use a write-protect pin to transmit a command for a hardware reset operation.

[0043] At position 205, a hibernation command can be transmitted. For example, the host system can transmit a first command to the memory system to switch from a first power mode to a second power mode. The first command can be an instance of a hibernation command, an idle command, a power-down command, a low-power mode command, a power-off command, or a combination thereof. The first power mode can be an instance of an active mode, a wake-up mode, a power-on mode, or a combination thereof. In some instances, the first power mode can be associated with executing the received command. The second power mode can be an instance of a hibernation mode, an idle mode, a power-down mode, a low-power mode, a power-off mode, or a combination thereof. In some cases, the second power mode can be associated with disabling one or more components associated with the memory system. In this case, the second power mode may consume less power from the memory system than the first power mode. The host system can transmit the command in response to a user pressing a power button on a user device containing the memory system. The memory system can receive the command and directly respond to the received command by entering the second power mode (e.g., power-down). The first command can be an instance of a self-service user (SSU) command.

[0044] At 210, the voltage can be adjusted to the memory system. For example, the host system can isolate the memory system from the voltage associated with at least one power supply to the memory system in response to transmitting a first command. In this case, the host system can disconnect the voltage associated with at least one power supply (e.g., VCC). In some cases, the user device associated with the memory system can receive a disconnection indication. For example, the user can press the power button on the user device containing the memory system. The memory system can receive the indication, and the host system can isolate the memory system from the voltage.

[0045] In some cases, the user device associated with the memory system may receive an activation indication. For example, a user may press a power button on a user device containing the memory system. The memory system may receive the indication, and the host system may connect the memory system to a voltage associated with at least one power source associated with the memory system. In this case, the host system may activate the memory system during a power-down cycle, thereby interrupting the operation of the memory system to prepare for hibernation mode and introducing a jamming condition. In some cases, switching the voltage (e.g., VCC) on and off during hibernation mode can save power associated with the memory system and increase the efficiency of the memory system.

[0046] At 215, an activation command may be transmitted. For example, the host system may transmit a second command for the memory system to exit a second power mode in response to connecting the memory system to a voltage. The second command may be an instance of an activation command, a wake-up command, a power-on command, or a combination thereof. The host system may also transmit a command for the memory system to enter a first power mode. In this case, the memory system may enter the first power mode (e.g., active mode). In some cases, transmitting the second command may be based on transmitting the first command and / or isolating the memory system from the voltage. The second command may be an instance of an SSU command.

[0047] At 220, a timer can be activated. For example, the host system can activate a timer associated with a timeout condition for exiting a second power mode in response to the transmission of a second command. The host system can detect the timeout condition and start the timer after sending the second command. The timeout condition can be an instance of the duration during which the host system can retrieve a message from the memory system after the host system transmits the second command. In some instances, the host system can inform the memory system of a shutter time frame (e.g., the duration of the timer). The host system can send an activation (e.g., start timer) command. The timeout condition can be a specified period of time that can be allowed to elapse in the memory system before a specified event (e.g., a hardware reset operation) occurs.

[0048] At point 225, it can be determined whether an indication was received while the timer was active. For example, the host system can determine whether the timer has expired. In some cases, the host system can determine whether the timer has expired and can determine whether an indication has been received based on the timer's expiration. In some instances, the host system can determine that the duration indicated by the timer expired after the timer was activated. In other instances, the host system can determine that the duration indicated by the timer did not expire after the timer was activated. In some cases, determining whether a time has expired can be an instance of determining whether a timeout condition has occurred.

[0049] At point 225, the host system may determine that no indication can be received while the timer is active. In response to determining that the duration indicated by the timer has expired, the host system may not receive from the memory system a message (e.g., an indication) indicating that the memory system is ready to receive a command (e.g., an access command). For example, the memory system may prevent message transmission to the host system during the timer's duration. In this case, if no message is received from the memory system at the host system within the duration indicated by the timer, the timer may expire. In some cases, determining that the duration indicated by the timer has expired may be an instance of an indication received at the host system. For example, the duration indicated by the timer may be an instance of an indication. The duration indicated by the timer may be predetermined based on activating the timer (e.g., it may be set by a fine-tuning parameter or another operating parameter stored in the memory system). For example, the host system may activate the timer and indicate a ten-minute duration. In this case, if the host system does not receive an indication from the memory system within ten minutes, the timer may expire.

[0050] In some cases, at 225, the host system may determine a voltage satisfaction threshold associated with at least one voltage supply to the memory system based on determining that a duration indicated by a timer has expired. For example, the host system may determine whether the voltage of a memory cell associated with the memory system is below 0.5 volts in response to determining that the timer has expired. If the voltage of a memory cell associated with the memory system is below 0.5 volts, then it can be determined that the memory system is fully powered down. If the voltage of a memory cell associated with the memory system is above 0.5 volts, then it can be determined that the memory system is not fully powered down, thus indicating that a jamming condition may have occurred.

[0051] At point 225, the host system can determine that the memory system receives a second command during a second duration for transitioning from a first power mode to a second power mode. For example, the host system can determine that the memory system wakes up (e.g., enters the first power mode) and is not fully powered down during the discharge time. The discharge time can be an instance of the duration for entering the second power mode. For example, the discharge time can be 100 milliseconds (ms).

[0052] At 230, a reset command can be transmitted. A reset command can be transmitted based on the determination that no indication was received while the timer was active. For example, the host system can transmit a third command for the memory system to perform a hardware reset operation in response to determining that the timer's duration has expired. In this case, the host system can issue a hardware reset operation after detecting a timeout condition and determining that the timer has expired. The memory system can receive the third command and perform a hardware reset operation in response to receiving the third command. In some cases, issuing a hardware reset operation can be based on determining that a voltage meets a threshold (e.g., a voltage higher than 0.5 volts). In other instances, issuing a hardware reset operation can be based on determining that the memory system received a second command during a second duration (e.g., the memory system wakes up within 100 milliseconds after receiving the first command).

[0053] In some instances, the host system may directly activate the write protection pin associated with the memory system in response to determining that a duration indicated by a timer has expired. For example, the host system may activate the write protection pin as part of a hardware reset operation. In this case, the memory system can use the write protection pin and perform a hardware reset operation in response to activating the write protection pin. For example, the hardware reset operation can use the pin as a NAND hardware reset.

[0054] A hardware reset operation can reset one or more memory dies associated with write protection pins maintained at a voltage below a threshold voltage. In this case, the hardware reset operation can be triggered by bringing the write protection pins to a low voltage (e.g., below a threshold voltage). A hardware reset operation can differ from a power cycle. A power cycle can involve isolating the memory system from one or more voltage supplies and reinitializing one or more operating parameters of the memory system. A power cycle can bring the entire memory system and its components into an initial power-on state. A power cycle can cause the memory system to reload parameters (e.g., tuning parameters or operating parameters) from non-volatile memory devices into volatile memory devices (e.g., caches, buffers, and SRAMs) used to operate the memory system. A power cycle brings the memory system into a power-on state. A hardware reset operation can initialize fewer parameters than a power cycle operation.

[0055] A hardware reset operation can be used to place a target area of ​​a memory system in known conditions similar to a power-on initialization state. If the memory system becomes unresponsive during a stuck condition, a hardware reset operation can provide a way to restore the NAND device (e.g., a memory device) of the memory system. A hardware reset operation can be triggered by reducing the voltage of the write protection pin to below a voltage threshold for the duration of the hardware reset operation. A hardware reset operation can reset each memory die of the memory system coupled to an access line that transmits a write protection signal, wherein the signal is below the voltage threshold.

[0056] A hardware reset operation in response to determining that a timer has expired (e.g., a timeout condition has occurred) prevents the memory system from recirculating power back to the memory system and completing a full power cycle, thereby reducing the latency and startup time for operation. The hardware reset operation can resolve (e.g., release) a jamming condition, allowing the host system to connect the memory system to a voltage associated with at least one power supply connected to the memory system.

[0057] At 235, an indication can be received. For example, the host system can receive an indication from the memory system after a duration indicated by a timer has expired. An indication can also be received in response to issuing a hardware reset operation. In this case, the host system can receive a message from the memory system indicating that the memory system is ready to receive commands (e.g., access commands). The indication can be an instance of an SSU response.

[0058] At position 240, access commands can be transmitted. For example, the host system can transmit a command to perform an access operation in response to receiving an instruction. The access command can be an instance of a read command or a write command. In this case, the memory system can receive the access command and perform the access operation. The access operation can be an instance of a read operation or a write operation.

[0059] In other instances, at 225, the host system may determine that an indication was received while the timer was active. For example, the host system may determine, based on the activation of the timer, that the duration indicated by the timer has not expired. For example, the host system may receive an indication from the memory system that the memory system is ready to receive commands (e.g., access commands) before the timer expires. The host system may search for an indication (e.g., a message) from the memory system before the duration indicated by the timer expires.

[0060] For example, before receiving an instruction, the host system may transmit a fourth command for the memory system to transition from a first power mode to a second power mode. The fourth command may be an instance of a hibernation command, an idle command, a power-down command, a low-power mode command, a power-off command, or a combination thereof. The first power mode may be an instance of an active mode, a wake-up mode, a power-on mode, or a combination thereof. In some instances, the first power mode may be associated with executing the received command. The second power mode may be an instance of a hibernation mode, an idle mode, a power-down mode, a low-power mode, a power-off mode, or a combination thereof. In some cases, the second power mode may be associated with disabling one or more components associated with the memory system. In this case, the second power mode may consume less power from the memory system than the first power mode.

[0061] The host system may then transmit a fifth command for the memory system to exit the second power mode based on the transmission of the fourth command. The fifth command may be an instance of an activation command, a wake-up command, a power-on command, or a combination thereof. The host system may also transmit a command for the memory system to enter a first power mode. In this case, the memory system may enter the first power mode (e.g., power-on). In some cases, the host system may receive an indication from the memory system during a duration indicated by a timer, based on the transmission of the fifth command to exit the second power mode.

[0062] At 245, the memory system can deactivate the timer before the duration indicated by the timer expires in response to receiving an instruction. In this case, if the host system receives an instruction before the timer expires, the host system can cancel the timer.

[0063] At point 250, a reset command cannot be transmitted. For example, the host system may prevent the transmission of a third command used to perform a hardware reset operation on the memory system. In some cases, preventing the transmission of a third command may be a direct response to stopping a timer. In some cases, the host system may transmit an access command to the memory system after receiving instruction 250, similar to the features described with reference to references 240 and 245.

[0064] Figure 3 A block diagram 300 illustrates a host system 320 supporting host recovery for stuck conditions, based on examples disclosed herein. The host system 320 may be as described in the references... Figures 1 to 2Examples of aspects of the described host system. Host system 320 or its various components may be examples of various aspects of components for performing host recovery in response to stuck conditions, as described herein. For example, host system 320 may include a hibernation component 325, an activity component 330, a timeout component 335, a timer component 340, a reset component 345, a voltage component 350, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0065] The hibernation component 325 may be configured or otherwise supported to support means for transmitting a first command for the memory system to transition from a first power mode to a second power mode, the first power mode being associated with executing the received command and the second power mode being associated with disabling one or more components associated with the memory system. The activation component 330 may be configured or otherwise supported to support means for transmitting a second command for the memory system to exit the second power mode, at least in part based on transmitting the first command. The timeout component 335 may be configured or otherwise supported to support means for activating a timer associated with a timeout condition for exiting the second power mode, at least in part based on transmitting the second command to exit the second power mode. The timer component 340 may be configured or otherwise supported to support means for determining, at least in part based on activating the timer, the duration indicated by the timer. The reset component 345 may be configured or otherwise supported to support means for transmitting a third command for the memory system to perform a hardware reset operation, at least in part based on determining that the duration of the timer has expired.

[0066] In some instances, the reset component 345 may be configured or otherwise supported to include means for receiving an indication from the memory system after a duration indicated by a timer has expired, at least in part, based on the issuance of a hardware reset operation. In some instances, the activation component 330 may be configured or otherwise supported to include means for transmitting a command to perform an access operation, at least in part, based on the receipt of an indication.

[0067] In some instances, voltage component 350 may be configured or otherwise support a means for determining a voltage satisfaction threshold associated with at least one voltage supply to the memory system based at least in part on determining the expiration of a duration indicated by a timer, wherein issuing a hardware reset operation is based at least in part on determining the voltage satisfaction threshold.

[0068] In some instances, the active component 330 may be configured or otherwise supported to determine that the memory system has received a second command during a second duration for transitioning from a first power mode to a second power mode, wherein issuing a hardware reset operation is based at least in part on determining that the memory system has received a second command during the second duration.

[0069] In some instances, the hibernation component 325 may be configured or otherwise supported to support means for transmitting a fourth command for the memory system to transition from a first power mode to a second power mode. In some instances, the activity component 330 may be configured or otherwise supported to support means for transmitting a fifth command for the memory system to exit the second power mode, at least in part based on transmitting the fourth command. In some instances, the timeout component 335 may be configured or otherwise supported to support means for receiving an indication from the memory system during a duration indicated by a timer, at least in part based on transmitting the fifth command to exit the second power mode. In some instances, the timer component 340 may be configured or otherwise supported to support means for deactivating the timer at least in part based on receiving an indication to deactivate the timer before the duration indicated by the timer expires, wherein preventing the transmission of the third command is at least in part based on deactivating the timer.

[0070] In some instances, the reset component 345 may be configured or otherwise support a component for activating a write protection pin associated with the memory system, at least in part based on determining that a duration indicated by a timer has expired.

[0071] In some instances, voltage component 350 may be configured or otherwise support a means for isolating the memory system from at least one power source associated with the memory system, at least in part based on transmitting a first command, wherein transmitting a second command is at least in part based on isolating the memory system from the voltage.

[0072] In some instances, voltage component 350 may be configured or otherwise support a component for connecting the memory system to a voltage associated with at least one power source connected to the memory system, at least in part based on transmitting a first command, wherein transmitting a second command is at least in part based on connecting the memory system to the voltage.

[0073] In some instances, a hardware reset operation resets one or more memory dies associated with write protection pins that are maintained at voltages below a threshold voltage.

[0074] In some instances, the hardware reset operation differs from a power cycle, which includes isolating the memory system from one or more voltage supplies and reinitializing one or more operating parameters of the memory system.

[0075] Figure 4 The flowchart illustrates a method 400 for supporting host recovery from a stuck condition, based on examples disclosed herein. The operation of method 400 can be implemented by a host system or its components as described herein. For example, the operation of method 400 can be performed by, as referenced... Figures 1 to 3The described host system performs the function. In some instances, the host system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the host system may use dedicated hardware to perform aspects of the described function.

[0076] At 405, a first command may be transmitted. For example, the method may include transmitting a first command for the memory system to transition from a first power mode to a second power mode, the first power mode being associated with executing the received command and the second power mode being associated with disabling one or more components associated with the memory system. Operation at 405 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 3 The described hibernation component 325 performs the operation of 405.

[0077] At 410, a second command may be transmitted. For example, the method may include transmitting a second command for the memory system to exit a second power mode, at least in part based on the transmission of the first command. Operation 410 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 3 The described active component 330 performs the operation of 410.

[0078] At 415, a timer can be activated. For example, the method may include activating a timer associated with a timeout condition for exiting the second power mode, based at least in part on a second command to exit the second power mode transmitted. Operation at 415 can be performed according to examples disclosed herein. In some instances, it can be performed by, as referenced... Figure 3 The described timeout component 335 performs the operation of 415.

[0079] At 420, the duration can be determined. For example, the method may include determining the expiration of the duration indicated by the timer based at least in part on the activation of a timer. Operation at 420 can be performed according to examples disclosed herein. In some instances, it can be performed by, as referenced... Figure 3 The described timer component 340 performs the operation of 420.

[0080] At 425, a third command may be transmitted. For example, the method may include transmitting a third command for performing a hardware reset operation on the memory system, at least in part based on determining that the duration of a timer has expired. Operation at 425 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 3 The described reset component 345 performs the operation of 425.

[0081] In some instances, the device as described herein may perform one or more methods, such as method 400. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting a first command for a memory system to transition from a first power mode to a second power mode, the first power mode being associated with executing the received command and the second power mode being associated with disabling one or more components associated with the memory system; transmitting a second command for the memory system to exit the second power mode, at least in part based on transmitting the first command; activating a timer associated with a timeout condition for exiting the second power mode, at least in part based on transmitting the second command to exit the second power mode; determining, at least in part based on activating the timer, that a duration indicated by the timer has expired; and transmitting a third command for the memory system to perform a hardware reset operation, at least in part based on determining that the duration of the timer has expired.

[0082] Some examples of the method 400 and apparatus described herein may further include operations, features, circuits, logic, components, or instructions for: receiving an indication from the memory system after the duration indicated by the timer has expired, at least in part based on issuing the hardware reset operation; and transmitting a command to perform an access operation, at least in part based on receiving the indication.

[0083] Some examples of the method 400 and apparatus described herein may further include operations, features, circuits, logic, components, or instructions for determining a voltage satisfaction threshold associated with at least one voltage supply to the memory system, at least in part based on determining that the duration indicated by the timer has expired, wherein issuing the hardware reset operation may be at least in part based on determining that the voltage satisfies the threshold.

[0084] Some examples of the method 400 and device described herein may further include operations, features, circuits, logic, components, or instructions for determining that the memory system receives the second command during a second duration for transitioning from the first power mode to the second power mode, wherein issuing the hardware reset operation may be based at least in part on determining that the memory system received the second command during the second duration.

[0085] Some examples of the method 400 and apparatus described herein may further include operations, features, circuits, logic, components, or instructions for: transmitting a fourth command for the memory system to transition from a first power mode to a second power mode; transmitting a fifth command for the memory system to exit the second power mode, at least in part based on transmitting the fourth command; receiving an instruction from the memory system during the duration indicated by the timer, at least in part based on transmitting the fifth command to exit the second power mode; and deactivating the timer before the duration indicated by the timer expires, at least in part based on receiving the instruction, wherein preventing the transmission of the third command may be at least in part based on deactivating the timer.

[0086] Some examples of the method 400 and device described herein may further include operations, features, circuits, logic, components, or instructions for activating a write protection pin associated with the memory system, at least in part, based on determining that the duration indicated by the timer has expired.

[0087] Some examples of the method 400 and apparatus described herein may further include operations, features, circuits, logic, components, or instructions for isolating the memory system from a voltage associated with at least one power source of the memory system, at least in part, based on transmitting the first command, wherein transmitting the second command may be at least in part based on isolating the memory system from the voltage.

[0088] Some examples of the methods 400 and devices described herein may further include operations, features, circuits, logic, components, or instructions for connecting the memory system to a voltage associated with at least one power source connected to the memory system, at least in part based on transmitting the first command, wherein transmitting the second command may be at least in part based on connecting the memory system to the voltage.

[0089] In some instances of the method 400 and device described herein, the hardware reset operation resets one or more memory dies associated with write protection pins that can be maintained at voltages below a threshold voltage.

[0090] In some instances of the method 400 and device described herein, the hardware reset operation may differ from a power cycle that includes isolating the memory system from one or more voltage supplies and reinitializing one or more operating parameters of the memory system.

[0091] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0092] The information and signals described herein can be represented using any of a variety of techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some figures may illustrate signals as single signals; however, the signals may represent signal buses, which may have various bit widths.

[0093] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if there exists any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the flow of signals between connected components for a period of time.

[0094] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. If, for example, a component of a controller couples other components together, then the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0095] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, components separated by a switch located between two components are isolated from each other when the switch is open. If a controller isolates two components, then the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0096] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0097] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0098] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action that is independent of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other condition or action.

[0099] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0100] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. These terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0101] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatus are shown in block diagram form to avoid obscuring the concept of the described instances.

[0102] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0103] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distribution such that different parts of the functions are implemented in different physical locations.

[0104] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0105] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0106] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or another remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0107] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein but is intended to embody the broadest scope conforming to the principles and novel features disclosed herein.

Claims

1. A device for memory operations, comprising: A controller configured to cause the device to: Transmit a first command for the memory system to switch from a first power mode to a second power mode, the first power mode being associated with executing the received command and the second power mode being associated with disabling one or more components associated with the memory system; The second command for the memory system to exit the second power mode is transmitted, at least in part, based on the transmission of the first command; The timer associated with the timeout condition for exiting the second power mode is activated at least in part based on the second command to exit the second power mode. The expiration of the duration indicated by the timer is determined at least in part based on the activation of the timer; as well as A third command for performing a hardware reset operation on the memory system is transmitted, at least in part based on determining that the duration of the timer has expired.

2. The device of claim 1, wherein the controller is further configured such that the device: At least in part, based on receiving an indication from the memory system after the duration indicated by the timer has expired following the issuance of the hardware reset operation; and The command to perform the access operation is transmitted at least in part based on receiving the instruction.

3. The device of claim 1, wherein the controller is further configured such that the device: A voltage satisfaction threshold associated with at least one voltage supply to the memory system is determined at least in part based on determining that the duration indicated by the timer has expired, wherein issuing the hardware reset operation is at least in part based on determining that the voltage satisfies the threshold.

4. The device of claim 1, wherein the controller is further configured such that the device: It is determined that the memory system receives the second command during a second duration for transitioning from the first power mode to the second power mode, wherein issuing the hardware reset operation is based at least in part on determining that the memory system receives the second command during the second duration.

5. The device of claim 1, wherein the controller is further configured such that the device: Transmit a fourth command for the memory system to switch from the first power mode to the second power mode; The fifth command for the memory system to exit the second power mode is transmitted, at least in part, based on the transmission of the fourth command; The fifth command to exit the second power mode is received from the memory system during the duration indicated by the timer, at least in part based on the transmission. as well as The timer is deactivated at least in part based on receiving the instruction to deactivate it before the duration indicated by the timer expires, wherein the prevention of transmission of the third command is at least in part based on deactivating the timer.

6. The device according to claim 1, wherein, To transmit the third command, the controller is further configured such that the device: The write protection pin associated with the memory system is activated at least in part based on determining that the duration indicated by the timer has expired.

7. The device of claim 1, wherein the controller is further configured such that the device: The transmission of the second command is at least partially based on isolating the memory system from at least one power source associated with the memory system, wherein the transmission of the second command is at least partially based on isolating the memory system from the voltage.

8. The device of claim 1, wherein the controller is further configured such that the device: The transmission of the second command is at least partially based on connecting the memory system to a voltage associated with at least one power source connected to the memory system, wherein the transmission of the second command is at least partially based on connecting the memory system to the voltage.

9. The device of claim 1, wherein the hardware reset operation resets one or more memory dies associated with a write protection pin maintained at a voltage below a threshold voltage.

10. The device of claim 1, wherein the hardware reset operation is different from a power cycle, the power cycle comprising isolating the memory system from one or more voltage supplies and reinitializing one or more operating parameters of the memory system.

11. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Transmit a first command for the memory system to switch from a first power mode to a second power mode, the first power mode being associated with executing the received command and the second power mode being associated with disabling one or more components associated with the memory system; The second command for the memory system to exit the second power mode is transmitted, at least in part, based on the transmission of the first command; The timer associated with the timeout condition for exiting the second power mode is activated at least in part based on the second command to exit the second power mode. The expiration of the duration indicated by the timer is determined at least in part based on the activation of the timer; as well as A third command for performing a hardware reset operation on the memory system is transmitted, at least in part based on determining that the duration of the timer has expired.

12. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: At least in part, based on receiving an indication from the memory system after the duration indicated by the timer has expired following the issuance of the hardware reset operation; and The command to perform the access operation is transmitted at least in part based on receiving the instruction.

13. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A voltage satisfaction threshold associated with at least one voltage supply to the memory system is determined at least in part based on determining that the duration indicated by the timer has expired, wherein issuing the hardware reset operation is at least in part based on determining that the voltage satisfies the threshold.

14. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: It is determined that the memory system receives the second command during a second duration for transitioning from the first power mode to the second power mode, wherein issuing the hardware reset operation is based at least in part on determining that the memory system receives the second command during the second duration.

15. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Transmit a fourth command for the memory system to switch from the first power mode to the second power mode; The fifth command for the memory system to exit the second power mode is transmitted, at least in part, based on the transmission of the fourth command; The fifth command to exit the second power mode is received from the memory system during the duration indicated by the timer, at least in part based on the transmission. as well as The timer is deactivated at least in part based on receiving the instruction to deactivate it before the duration indicated by the timer expires, wherein the prevention of transmission of the third command is at least in part based on deactivating the timer.

16. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to transmit the third command, the third command, when executed by the processor of the electronic device, cause the electronic device to: The write protection pin associated with the memory system is activated at least in part based on determining that the duration indicated by the timer has expired.

17. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The transmission of the second command is at least partially based on isolating the memory system from at least one power source associated with the memory system, wherein the transmission of the second command is at least partially based on isolating the memory system from the voltage.

18. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The transmission of the second command is at least partially based on connecting the memory system to a voltage associated with at least one power source connected to the memory system, wherein the transmission of the second command is at least partially based on connecting the memory system to the voltage.

19. The non-transitory computer-readable medium of claim 11, wherein the hardware reset operation resets one or more memory dies associated with a write protection pin maintained at a voltage below a threshold voltage.

20. The non-transitory computer-readable medium of claim 11, wherein the hardware reset operation is different from a power cycle, the power cycle comprising isolating the memory system from one or more voltage supplies and reinitializing one or more operating parameters of the memory system.

21. A method for memory operations, comprising: Transmit a first command for the memory system to switch from a first power mode to a second power mode, the first power mode being associated with executing the received command and the second power mode being associated with disabling one or more components associated with the memory system; The second command for the memory system to exit the second power mode is transmitted, at least in part, based on the transmission of the first command; The timer associated with the timeout condition for exiting the second power mode is activated at least in part based on the second command to exit the second power mode. The expiration of the duration indicated by the timer is determined at least in part based on the activation of the timer; as well as A third command for performing a hardware reset operation on the memory system is transmitted, at least in part based on determining that the duration of the timer has expired.

22. The method of claim 21, further comprising: At least in part, the hardware reset operation is initiated after an instruction is received from the memory system after the duration indicated by the timer has expired; as well as The command to perform the access operation is transmitted at least in part based on receiving the instruction.

23. The method of claim 21, further comprising: A voltage satisfaction threshold associated with at least one voltage supply to the memory system is determined at least in part based on determining that the duration indicated by the timer has expired, wherein issuing the hardware reset operation is at least in part based on determining that the voltage satisfies the threshold.

24. The method of claim 21, further comprising: It is determined that the memory system receives the second command during a second duration for transitioning from the first power mode to the second power mode, wherein issuing the hardware reset operation is based at least in part on determining that the memory system receives the second command during the second duration.

25. The method of claim 21, further comprising: Transmit a fourth command for the memory system to switch from the first power mode to the second power mode; The fifth command for the memory system to exit the second power mode is transmitted, at least in part, based on the transmission of the fourth command; The fifth command to exit the second power mode is received from the memory system during the duration indicated by the timer, at least in part based on the transmission. as well as The timer is deactivated at least in part based on receiving the instruction to deactivate it before the duration indicated by the timer expires, wherein the prevention of transmission of the third command is at least in part based on deactivating the timer.

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