Error handling flow management in memory devices

Abstract

This disclosure relates to error handling flow management in a memory device. Systems and methods comprising a memory device and a processing means operatively coupled to the memory device are disclosed. The processing means is capable of performing operations including: detecting read errors relating to data residing in a block of the memory device, wherein the block is associated with a voltage offset interval; determining an order of a plurality of error handling operations to be performed to recover the data associated with the read error, wherein the order is specified in a metadata table and based on the voltage offset interval associated with the block; and performing at least one of the plurality of error handling operations in the order specified in the metadata table.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to error handling flow management in memory devices. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a system comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: detecting a read error relating to data residing in a block of the memory device, wherein the block is associated with a voltage offset interval; determining an order of a plurality of error handling operations to be performed to recover data associated with the read error, wherein the order is specified in a metadata table and based on the voltage offset interval associated with the block; and performing at least one of the plurality of error handling operations in the order specified in the metadata table.

[0004] In another aspect, this disclosure relates to a method comprising: detecting a read error relating to data residing in a block of the memory device, wherein the block is associated with a voltage offset interval; performing at least one of a plurality of error handling operations in an order specified by a metadata table, wherein the order of the plurality of error handling operations is based on the voltage offset interval associated with the block; and performing an adjustment to the error handling stream.

[0005] In another aspect, this disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means operatively coupled to a memory, perform operations including: detecting a read error with respect to data residing in a block of the memory means, wherein the block is associated with a voltage offset interval; determining an order of a plurality of error handling operations to be performed to recover the data associated with the read error, wherein the order is specified in a metadata table and based on the voltage offset interval associated with the block; and performing at least one of the plurality of error handling operations in the order specified in the metadata table. Attached Figure Description

[0006] This disclosure will be more fully understood in light of the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 The illustration schematically depicts a time-voltage shift of a three-level memory cell capable of storing three data bits by programming a memory cell to eight charge states, the eight charge states being different from the amount of charge on the floating gate of the cell.

[0009] Figure 3 Example graphs illustrating the dependence of threshold voltage offset on programming time (i.e., the time elapsed since the block was programmed) according to some embodiments of this disclosure.

[0010] Figure 4 This describes the instance metadata maintained by the memory subsystem controller according to aspects of this disclosure.

[0011] Figure 5 This is a flowchart of an example method for error handling flow management implemented according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0013] This disclosure pertains to error handling flow management in memory devices. The memory subsystem may be a memory device, a memory module, or a mixture of both. The following description, in conjunction with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0014] The memory subsystem can utilize one or more memory devices (including any combination of different types of non-volatile memory devices and / or volatile memory devices) to store data provided by the host system. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. Each memory device may contain one or more arrays of memory cells. A memory cell (“cell”) is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. The logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0015] Various data operations can be performed by the memory subsystem. These data operations can be host-initiated. For example, the host system can initiate data operations (such as write, read, erase, etc.) on the memory subsystem. The host system can send access requests (such as write commands, read commands) to the memory subsystem to store data on a memory device located on the memory subsystem and to read data from a memory device on the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (such as logical block address (LBA), namespace) for the host data, which is the location associated between the host system and the host data. The logical address information (such as LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (such as error correction code (ECC) codeword parity data), data version (such as distinguishing between new and old data being written), valid bitmaps (whose LBAs or logical transfer units contain valid data), etc.

[0016] A memory device comprises multiple memory cells capable of storing one or more bits of information, depending on the type of memory cell. A memory cell can be programmed (written into the memory cell) by applying a voltage to it, causing a charge to be held within the cell; this voltage is called the "threshold voltage" and is denoted as Vt.

[0017] High-quality memory devices can have a narrow distribution compared to the operating range of the control voltages allowed by the cells of the device. Therefore, multiple distributions (with "valleys" between them) can fit precisely into an operating voltage window that allows each cell to store and reliably detect multiple bits, such as 2 for a TLC. 3 = 8 distributions (7 valleys), 2 for MLC 2 = 4 distributions (3 valleys), etc. Voltage intervals (“valley margins”) are interspersed between the distributions, wherein no (or very few) memory cells in the device have their threshold voltages. Therefore, such valley margins can be used to separate various charge states by applying a read voltage corresponding to each valley, and the logic state of the cell can be determined by detection during a read operation. This effectively allows a single memory cell to store multiple bits of information: in 2 N A memory cell operating under a distribution (also known as a hierarchy) can store N bits of information. During a read operation, a 2 N -1 reading voltage to distinguish 2 N A distribution. Specifically, this can be achieved by displaying the measured threshold voltage V of the memory cell. T A read operation is performed by comparing the voltage level with one or more reference voltage levels corresponding to a known valley (e.g., the valley center) of the memory device.

[0018] Due to a phenomenon known as slow charge loss (SCL), the threshold voltage V of a memory cell decreases as the cell's charge diminishes. T This can vary over time, and the process is sometimes referred to as "time-to-voltage shift" (TVS). The terms "stored charge loss" and "system charge loss" are also used in SCL. Since a typical cell stores negatively charged particles (electrons), the loss of electrons causes the voltage threshold to shift along the voltage axis towards the lower limit voltage threshold V. T Shifting. The threshold voltage can be changed rapidly (immediately after the memory cell is programmed), while simultaneously changing in a roughly logarithmic linear or power-law manner (ΔV) relative to the time t elapsed since the cell programming event. T (t)=-C*t b The voltage is slowed down over a longer period of time. In some embodiments of this disclosure, this can be achieved by maintaining a track of the time elapsed since the programming event and environmental conditions such as temperature for a particular memory partition (block, plane, etc.), and by offsetting the voltage per valley value used during a read operation by ΔV. T Correlation to mitigate TVS, where the standard "baseline read level" threshold voltage V T (Immediately following the programming, this is displayed by the cell) The change is the voltage offset: V T →V T +ΔV T , where ΔV T It is negative due to charge loss. Although TVS is a continuous process and is related to ΔV T The compensation for (t) can change over time, but in some embodiments, a discrete number of offset "intervals" can be used to achieve sufficient accuracy of the offset. Blocks can be associated with intervals using metadata (e.g., programmed within a specified time window and under similar environmental conditions, such as temperature). Since the time elapsed since programming and the temperature conditions are among the major factors affecting the TVS, it can be inferred that blocks associated with the same interval will exhibit a similar distribution of threshold voltages for their memory cells, and therefore the same voltage offset will need to be applied to the base read level for read operations.

[0019] The memory subsystem controller may periodically perform a calibration process to associate blocks with one of intervals. Each interval may in turn be associated with a set of voltage offsets to be applied for read operations. The block-to-interval association is referred to herein as Auxiliary Read Metadata (ARM), representing a portion of the broader state metric of the memory device. The state metric may also include the number of abandoned physical memory blocks (or other partitions), the number of times various physical blocks have been erased, the configuration type of cells in various memory partitions (e.g., single-level cells vs. multi-level cells), or any other type of information indicating the state of the memory device. The ARM may be stored in a metadata table maintained by the memory subsystem controller.

[0020] According to embodiments of this disclosure, TVS of programmed partitions grouped into families can be selectively tracked. Based on the grouping into families, an appropriate interval-specific read (voltage) offset is applied to the base read (voltage) level during a read operation. The base read level may also be stored in the metadata of the memory device. Upon receiving a read command, the memory subsystem controller may perform the following operations: identify the family associated with the memory partition identified by the logical address specified in the read command; identify the current interval associated with the identified family; determine a set of read offsets for the identified interval; calculate a new read voltage by superimposing the read offsets associated with the identified interval to the base read level; and execute the read voltage using the new read voltage, as described in more detail below.

[0021] A "read error" refers to the memory subsystem's failure to verify one or more data items retrieved from the memory device in response to a read command. Read errors can be associated with host-initiated read operations or system-initiated scan operations and can be attributed to reasons such as: the measured threshold voltage V exhibited by the memory cell. T Read errors can occur due to TVS (Transient Voltage Surge) causing a mismatch between the read voltage level and the requested data, or due to noise or interference. In a read error, a bit error in the read data exceeds the bit error that basic ECC (Electronic Code Correction) can correct, causing ECC failure and consequently a read error. In response to a read error, the memory subsystem can execute an error handling stream to attempt data recovery. The error handling stream may contain one or more error handling operations for data items retrieved from the memory device. Error handling operations may include one or more read retries using different parameters (e.g., variations in read voltage) compared to the initial read operation performed on the memory cell. Error handling operations may also include "deep error handling techniques," such as forward error correction (FEC) with various versions of reliability information, Hybrid Automatic Repeat Request (HARQ), etc.

[0022] In some implementations, the memory subsystem controller may use a default (e.g., static) error handling flow, where the order of error handling operations performed during the error handling flow remains the same for all blocks of the memory device. For example, upon entering the error handling flow, the memory subsystem controller may first perform a set of relatively low-latency steps, such as performing a predetermined number of read retries using different, relatively small (e.g., not exceeding a predefined threshold) read offsets applied to the base read level. In response to a low-latency step that successfully recovers data, the memory subsystem controller may exit the error handling flow to restart read and write operations. In response to a low-latency step that fails to recover data, the memory subsystem controller may perform the next error handling operation specified in the error handling flow. For example, the memory subsystem controller may perform higher-latency steps, such as applying a larger read offset compared to the read offset used in the low-latency steps, or using deep error handling techniques (e.g., FEC, HARQ, etc.) to recover data.

[0023] However, error handling operations can be time-consuming and impact the performance of the memory subsystem. Error handling operations can increase read times and / or degrade performance, as observed by the host system. The more frequently error handling operations are triggered, the slower the memory system's performance becomes, because fewer read and write operations are available to execute. Furthermore, specific points in the error handling flow where the memory subsystem is prevented from receiving other commands from the host reduce the availability of the memory subsystem to perform other read or write operations.

[0024] This disclosure improves the efficiency of error handling operations by implementing a memory subsystem controller capable of adjusting the order and parameters of error handling operations in an error handling stream within a memory device. Specifically, the memory subsystem controller can implement different error handling streams for different intervals. In one example, the association between intervals and different error handling streams can be determined during memory subsystem manufacturing, during memory subsystem programming and / or calibration, or dynamically by the memory subsystem controller. For instance, the error handling stream associated with interval 1 might instruct the memory subsystem controller to first execute error handling operation 1, then proceed to error handling operation 2 in response to error handling operation 1 failing to recover data, and finally proceed to error handling operation 3 in response to error handling operation 2 failing to recover data; while the error handling stream associated with interval 2 might instruct the memory subsystem controller to first execute error handling operation 2, then proceed to error handling operation 1 in response to error handling operation 2 failing to recover data, and finally proceed to error handling operation 3 in response to error handling operation 1 failing to recover data. Each error handling operation (e.g., error handling operation 1, error handling operation 2, error handling operation 3) may include issuing instructions to the memory subsystem controller to perform one or more read retries by applying one or more read offsets to the base read, by using deep error handling techniques, etc.

[0025] In other instances, the memory subsystem controller may reorder error handling operations in the default error handling stream based on the interval number associated with the block that experienced a read error. For example, a default error handling stream may be implemented for the memory subsystem during manufacturing and / or programming. In response to a detected read error, the memory subsystem controller may determine which interval is associated with the block that experienced the read error, determine the order of error handling operations associated with the interval using a metadata table, and execute the error handling operations of the default error handling stream in the order specified by the metadata. In some embodiments, the memory subsystem controller may dynamically modify the order of error handling operations associated with each interval. In one instance, the memory subsystem controller may maintain error handling statistics based on the read error rate for each interval (e.g., the number of read commands that trigger error handling for a predetermined number of host reads). In response to the read error rate meeting a threshold criterion, the memory subsystem controller may adjust one or more operations in the error handling stream. In one instance, the memory subsystem controller may modify the order of error handling operations in the error handling stream using the success rate of each error handling operation in the error handling stream (e.g., the error handling operations may be reordered based on their success rate in recovering data) and / or latency data associated with each error handling operation in the error handling stream. In another instance, the memory subsystem controller may modify one or more error handling operations in the error handling stream, for example, by adjusting the read offset used in the error handling operation or using a larger number of page samples (valley samples of the programmed distribution associated with each read level threshold, used by the memory subsystem controller for calibration operations). In some embodiments, the memory subsystem controller may implement a closed feedback loop to determine which modifications are successful in recovering data. Based on this feedback, the memory subsystem controller may update the error handling stream for future error handling.

[0026] The advantages of this disclosure include, but are not limited to, improving the performance of the memory subsystem by reducing the latency of the error handling stream performed by the memory subsystem. This improves the reliability of the memory subsystem and reduces its power consumption. Furthermore, it increases the lifespan of the memory subsystem. Although embodiments are described using memory cells of NAND flash memory, aspects of this disclosure are applicable to other types of memory subsystems.

[0027] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0028] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0029] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment or a networked commercially available device), or such a computing device that includes memory and processing power.

[0030] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, and magnetic connections.

[0031] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0032] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0033] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0034] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0035] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0036] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0037] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0038] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0039] In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0040] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0041] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may additionally include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0043] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] Memory subsystem 110 includes an error handling flow management component 113 that can be used to implement error avoidance strategies according to embodiments of the present disclosure. In some embodiments, memory subsystem controller 115 includes at least a portion of the error handling flow management component 113. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, error handling flow management component 113 is part of host system 120, an application, or an operating system. Error handling flow management component 113 may manage block families associated with memory device 130, as described in more detail below.

[0045] Figure 2 This illustration schematically demonstrates how, according to some embodiments of the present disclosure, memory cells can be programmed into eight charge states Q. k (Also known as a hierarchy) The time-voltage shift (TVS) of a three-level memory cell (TLC) storing three data bits, the amount of charge on the storage gate of the eight charge state phase difference cells. Threshold voltage P (V T Q k The distribution of ) and the 7 valley margins VM n Separate. Programmed as the k-th charge state (Q) k Each cell can store a specific combination of 3 bits. For example, the charge state Q kIt can store binary combinations of 101, as depicted. Other mappings from Qk to 3 bits are also possible. This charge state Q k Valley margin VM can be detected during read operations. k Internal control gate voltage V CG Sufficient to open the cell to source-drain current while maintaining the previous valley margin VM k-1 The control gate voltage is insufficient to open the cell to the source-drain current. Memory cells can be configured to store N=1 bits (SLC), N=2 bits (MLC), N=3 bits (TLC), N=4 bits (QLC), etc., depending on how much distribution can be fitted within the operating range of the control gate voltage (and with a sufficiently large valley margin). Even Figure 2 The operations described in this disclosure, which describe TLC, can still be applied to any N-bit memory cell.

[0046] Memory cells are typically joined by word lines (wires electrically connected to the cell's control gate) and, in one configuration (by selecting consecutive bit lines connected to the cell's source and drain electrodes), are programmed together as memory pages (e.g., 16KB or 32KB pages). As an example, Figure 2 This illustrates a scenario where 3 bits are programmed in 3 passes. Other programming sequences, such as 1-pass and 2-pass programming, can also be stored. Figure 2 In the example shown, during a read operation, the memory controller 115 can determine the control gate voltage V applied within the sixth valley margin VM6. CG The control gate voltage within the seventh valley margin VM7 is sufficient to open the cell to the source-drain current, and thus sufficient to open the cell. Therefore, the memory controller 115 can determine that the cell is in charge state Q7 corresponding to logic state 010 (i.e., XP:0, UP:1, LP:0).

[0047] use Figure 2 The solid line in the diagram depicts the distribution of threshold voltages that the memory cells have immediately after programming. Over time, due to slow charge loss, the distribution shifts (typically towards V). T The lower values), as indicated by the shifted valley values ​​shown by the dashed lines. Therefore, the threshold voltage of various memory cells is shifted by a certain value ΔV. T The value may depend on the time elapsed since programming, environmental conditions (e.g., ambient temperature), etc. For the optimal read operation, the controller 115 (or the error handling stream management component 113) can therefore correspond to an offset V. R →V R+ΔV (where ΔV is typically less than zero) adjusts the base read level, the corresponding offset being the same as (or approximately the same as) the time voltage shift. In one embodiment, the offset can be determined (or estimated) as the difference between the center of the valley margin immediately following programming (e.g., center 202 of VM7) and the center of the same but shifted valley margin at a later time (e.g., new center 204). Figure 2 The diagram illustrates that TVS with different distributions (valleys) and valley margins can differ from each other. Figure 2 In the typical scenario described, TVS is large for larger charges Q and small for smaller charges.

[0048] like Figure 2 As shown, TVS in the memory device is a continuous process. However, in some embodiments, sufficient accuracy of the voltage offset can be achieved using a set of discrete intervals and a corresponding set of discrete voltage offsets ΔV. In such embodiments, TVS can be addressed by setting several discrete intervals (e.g., five, eight, twenty, etc.) associated with various memory partitions. As an example, suppose that for valley 7, the desired optimal read position shift is 500 mV. In the case of six intervals, the offset of valley 7 can be defined as equally spaced, for example, 0 mV, 100 mV, 200 mV, 300 mV, 400 mV, 500 mV. Similarly, offsets for other valley values ​​can be defined. Interval offsets can be defined as not equally spaced but following different intervals. Interval-related data can be stored in metadata table 210. The association between various memory partitions (grouped into families, as described in more detail below) and intervals can be stored in family-interval association 212; the family-interval association can change dynamically over time. For example, as memory cells continue to lose charge over time, due to temperature changes and program / erase cycles (PECs), corresponding memory partitions (groups into families) can be moved sequentially from lower-level partitions to higher-level partitions with larger voltage offset values. The partition-offset association 214 may also be stored in the metadata table 210. In some embodiments, the partition-offset association 214 may be static, but the family-partition association 212 may be adjusted (based on memory partition calibration) to account for the actual charge loss of the memory cells in the corresponding partition. In some embodiments, the family-partition association 212 may store the logical address of the memory partition, such as the LBA of the corresponding block, while the association between the LBA and the corresponding physical block address (PBA) may be stored outside the metadata table 210, for example, separately within a memory translation table stored in local memory 119 or one of the memory devices 130, 140. However, in some embodiments, the family-partition association 212 may additionally include LBA-to-PBA translations or store direct PBA-to-partition associations. Figure 2The number of intervals, interval-offset correlation 214, and partition-interval correlation are schematically depicted using curved arrows. These can be based on the calibration of the memory device (or a similar type of memory device, for example, during design and manufacturing) to maximize performance and minimize read errors during read operations.

[0049] Threshold voltage offset depends on the time after programming (TAP). TAP is the time elapsed since the cell was written and is the first-level driver of the TVS. TAP can be estimated (e.g., inferred from data state metrics) or measured directly (e.g., from the controller clock). Cells, blocks, pages, block families, etc., are new (or relatively new) with (relatively) small TAPs and old (or relatively old) with (relatively) large TAPs. A time slice is the duration between two TAP points during which measurements can be performed (e.g., performing a reference calibration 8 to 12 minutes after programming). A time slice can be referenced by its center point (e.g., 10 minutes).

[0050] Memory devices can be grouped into block families, such that each block family contains one or more blocks programmed within a specified time window and possibly a specified temperature window. As mentioned above, since the elapsed time and temperature after programming are the main factors affecting time-voltage shift, it is assumed that all blocks and / or partitions within a single block family will exhibit similar threshold voltage distributions in the memory cells, and therefore will require the same voltage offset for read operations. TVS also depends on the program erase cycle; however, for wear leveling, all blocks will have similar PEC, and therefore PEC is not a differentiating factor for TVS among blocks within a block family.

[0051] Block families can be created asynchronously relative to block programming events. In an illustrative example, whenever a specified time period Δt (e.g., a predetermined number of minutes) has elapsed since the creation of the last block family, or whenever the reference temperature of a memory cell (which is updated at specified time intervals) has changed by more than a specified threshold ΔΘ (e.g., 10°C, 30°C, or any other value) since the creation of the current block family, then... Figure 1 The memory subsystem controller 115 can create (“enable”) new block families. Similarly, a family can be “deactivated” (and a new family can be created) after a time Δt has elapsed since the family was created or when the reference temperature (in either direction) has changed by more than ΔΘ. The memory subsystem controller 115 can maintain identifiers for active block families associated with one or more blocks being programmed.

[0052] The newly created block families can be associated with interval 0. Subsequently, the memory subsystem controller can periodically perform a calibration process to offset each die of each block family against a predefined threshold voltage offset interval (within...). Figure 3In the illustrative example, for a single valley value in the range 0-9, where the offset becomes more negative downwards along the y-axis (e.g., the offset of range 9 would have a higher magnitude compared to range 2, and both offsets are negative), it is associated with one of these values, and subsequently with the voltage offset to be applied for the read operation. The association between blocks and block families, as well as between block families and dies, and the threshold voltage offset range can be stored in the corresponding metadata tables maintained by the memory subsystem controller.

[0053] The voltage distribution is attributed to the temporal change in slow charge loss (SCL), which causes a drift in the threshold voltage level. According to various embodiments of this disclosure, time-varying voltage shifts are selectively tracked for programmed blocks grouped by block family, and an appropriate voltage offset based on block affiliation to a particular block family is applied to the base read level to perform a read operation.

[0054] Figure 3 This illustration schematically depicts a set of predefined threshold voltage offset intervals (intervals 0 to 9) for a specific valley value according to embodiments of the present disclosure. Figure 3 To illustrate, the threshold voltage offset graph 300 can be subdivided into multiple threshold voltage offset intervals, such that each interval corresponds to a predetermined range of threshold voltage offset. Although Figure 3 The illustrative example defines ten intervals (0-9), but in other implementations, various other numbers of intervals may be used (e.g., 64 intervals). Based on a periodically performed calibration process, the memory subsystem controller associates each die of each block family with a threshold voltage offset interval, which defines a set of threshold voltage offsets that will be applied to the base voltage read level to perform a read operation, as described in more detail below.

[0055] Figure 4 The instance metadata maintained by the memory subsystem controller according to aspects of this disclosure is illustrated schematically. In some embodiments, the error handling flow management component 113 may maintain error handling metadata table 410 and error handling metadata table 420. In some embodiments, error handling metadata tables 410 and 420 may be stored in the memory of the memory subsystem (e.g., at memory devices 130, 140, local memory 119, etc.) and may be referenced by the error handling flow management component 113 to determine the error handling flow associated with a particular offset range.

[0056] As described by error handling metadata table 410, each interval may be associated with a corresponding error handling stream (e.g., F0, F1…F5). As described by error handling metadata table 420, an error handling stream may be associated with a specific set of error handling operations to be executed in a specific order (e.g., operation order), parameter values ​​(e.g., read level adjustment values) for each error handling operation in each error handling stream (e.g., OP1 parameter, OP2 parameter, OP3 parameter, etc.), and the success rate (e.g., OP1 success rate, OP2 success rate, OP3 success rate) for each error handling operation in each error handling stream. Error handling metadata tables 410 and 420 may be two separate metadata tables or combined into a single metadata table.

[0057] Error handling flow management component 113 can perform error handling operations associated with the error handling flow for blocks of the same block family associated with the same interval. In some embodiments, the association between intervals and corresponding error handling flows can be determined and set during the fabrication of memory subsystem 110 or during programming and / or calibration of memory subsystem 110. Thus, each interval can be associated with an error handling flow having a specific set of error handling operations to be performed in a specific order.

[0058] In some embodiments, the memory subsystem controller 115 can dynamically set the error handling flow for each interval by reordering the error handling operations of the default error handling flow of the memory subsystem 110. The default error handling flow may refer to the error handling flow set for each block of the memory subsystem during programming and / or calibration of the memory subsystem 110, and / or the error handling flow initially associated with each interval (e.g., F0, F1…F5). The reordering of error handling operations may be based on the success rate (e.g., SR) of each error handling operation in each interval. F0-OP1 SR F0-OP2 SR F0-OP3 (For example, the percentage of data successfully recovered exceeding a threshold criterion, the percentage of data successfully recovered for each error handling operation compared to others, etc.). The error handling stream management component 113 can track the success rate of each error handling operation via the metadata table 420 by maintaining a per-interval (or per-error handling stream) counter for each example of an error handling operation that successfully recovered data and a per-interval counter for each example of an error handling operation that failed to recover data.

[0059] In an illustrative example, a default error handling flow may instruct the error handling flow management component 113 to execute error handling operation 1, followed by error handling operation 2, and then error handling operation 3. For a block associated with interval 3, error handling operation 1 may have a success rate lower than that of error handling operations 2 and 3, error handling operation 2 may have a success rate greater than that of error handling operations 1 and 3, and error handling operation 3 may have a success rate greater than that of error handling operation 1 but less than that of error handling operation 2. Therefore, the error handling flow management component 113 may reorder the error handling flow (F3) of interval 3 to instruct the error handling flow management component 113 to execute error handling operation 2 in response to a read error on a block associated with interval 3, followed by error handling operation 3, and then error handling operation 1. In some embodiments, multiple intervals may be associated with the same error handling flow.

[0060] In another illustrative example, the error handling stream management component 113 can track the success rate of sequences of two or more error handling operations by maintaining a per-interval counter for each sequence of error handling operations that successfully recovered data and a per-interval counter for each sequence of error handling operations that failed to recover data. Therefore, the error handling stream management component 113 can dynamically reorder the error handling operations of the default error handling stream based on the success rate of the sequences of error handling operations per interval (e.g., the percentage of successfully recovered data exceeding a threshold criterion, the percentage of each error handling operation that successfully recovered data compared to each other, etc.).

[0061] As discussed above, each error handling stream (e.g., F0, F1…F5) may contain different error handling operations that will be executed in a predetermined order by the error handling stream management component 113 before the desired data is successfully recovered from a read operation. Error handling operations may include one or more read retries using different parameters, such as applying different read offsets to the base read level, deep error handling techniques such as FEC and HARQ, etc. In some embodiments, one error handling operation may include a first set of read retries applying a set of read offsets to the base read level, and another error handling operation may include a second set of read retries applying different sets (with different values) of read offsets to the base read level. One or more error handling operations in one error handling stream may not be included in another error handling stream, and vice versa.

[0062] In an illustrative example, an interval associated with a newer block family (i.e., a recently created block family experiencing a large TVS due to the log-linear nature of SCL, where charge loss immediately following programming is faster than charge loss at a later time) can be associated with an error handling stream in which error handling operations include relatively large read level adjustments (e.g., applying a read offset greater than a predetermined threshold to the base read level) due to blocks in the newer block family experiencing relatively large shifts in threshold voltage (e.g., the threshold voltage changes rapidly immediately following memory cell programming). Thus, by performing a relatively broad read level adjustment instead of a relatively narrow one (e.g., the value of the broad read level adjustment is greater than the value of the narrow read level adjustment), the error handling stream management component 113 can increase the probability of successful data recovery from read level adjustments using the initial error handling operations of the error handling stream. In some embodiments, an interval (e.g., a relatively old interval due to a relatively large TVS) can be assigned an error handling stream in which the error handling stream management component 113 first performs a deep error handling technique (e.g., using hard and soft information). In response to the failure of the deep error handling technology to recover the desired data, the error handling stream management component 113 may then perform a read level adjustment operation.

[0063] In some embodiments, the error handling stream management component 113 may track error handling statistics for each interval. For example, the error handling stream management component 113 may maintain a record of the read error rate, such as the number of read commands that trigger error handling per predetermined number of read commands. In response to an error handling statistic indicating a decrease in the successful read operation rate (e.g., the number of read commands that trigger error handling per predetermined number of read commands exceeds a predetermined threshold), the error handling stream management component 113 may perform corrective actions on one or more operations of the error handling stream.

[0064] In some embodiments, the correction action may include the error handling stream management component 113 calibrating the read level adjustment of one or more error handling operations of the error handling stream. For example, the error handling stream management component 113 may adjust the read offset until data is recovered or until a predetermined number of read retries are performed.

[0065] In some embodiments, the calibration action may include the error handling flow management component 113 increasing the number of page samples used for a calibration procedure (e.g., continuous read level calibration (cRLC)). CRLC is a procedure used by the memory subsystem controller 115 to set and / or adjust the read level threshold of a memory cell by centering the read level threshold between two programming distributions using multiple page samples. By increasing the number of page samples used, the error handling flow management component 113 can increase the calibration accuracy of memory devices undergoing degradation (e.g., aging memory devices, memory devices experiencing hot or cold conditions, etc.).

[0066] In some embodiments, the correction action may include the error handling flow management component 113 determining the proximity of the time-of-programming (TAP) of one or more blocks in a block family (or said block family) associated with the interval to the TAP of adjacent intervals. The error handling flow management component 113 may then adjust the read offset used in the error handling operation of the associated interval based on the error handling operation of the nearest neighbor interval. Figure 3 For reference, an adjacent interval is an interval that immediately precedes or follows another interval (e.g., intervals 0 and 2 are adjacent intervals of interval 1, intervals 4 and 6 are adjacent intervals of interval 5, etc.). In an illustrative example, the error handling flow management component 113 may determine, based on the TAP value of the block (or block family), that one or more blocks in the block family associated with interval 5 are closer to interval 4 than interval 6. The error handling flow management component 113 may then adjust the read offset used in the error handling operation associated with interval 5 to the read offset used in the error handling operation associated with interval 4.

[0067] In some embodiments, the error handling stream management component 113 may configure the order of error handling operations in the error handling stream based on intervals and the programmable erase cycles associated with one or more blocks in a block family associated with the interval. Specifically, older intervals are those where the read level points to data with a relatively large TAP. Blocks in older intervals with relatively high programmable erase cycles may have relatively large voltage shifts and relatively narrow distribution valleys. Therefore, deep error handling techniques may have a relatively higher probability of achieving data recovery compared to error handling operations involving read level adjustments. Thus, the error handling stream management component 113 may dynamically adjust the order of error handling operations in the error handling stream based on intervals (e.g., interval numbers) and programmable erase cycles exceeding a threshold criterion for one or more blocks in a block family. By way of illustrative example only, in response to 10 or more blocks in interval 6 or higher having at least 1000 programmable erase cycles, the error handling stream management component 113 may dynamically adjust the error handling stream to initiate deep error handling techniques.

[0068] In some embodiments, the error handling stream management component 113 may implement a closed feedback loop to determine which modifications were successful in data recovery. Based on the feedback, the error handling stream management component 113 may update the error handling stream. Specifically, the error handling stream management component 113 may track the success rate of data recovery for each error handling operation in the error handling stream. The error handling stream management component 113 may then compare the success rate of each of the error handling operations with each other. Based on the comparison (e.g., which error handling operation has a higher success rate), the error handling stream management component 113 may reorder the error handling operations in the error handling stream (e.g., the error handling operation with the highest success rate may be executed first, the error handling operation with the second highest success rate may be executed second, and so on). The error handling stream management component 113 may use a table (e.g., a metadata table, logarithm, etc.) to track the success rate of each error handling operation in each interval.

[0069] In one example, in response to the error handling flow management component 113 determining that a subsequent error handling operation in the error handling flow has a higher success rate of successfully recovering data compared to a previous error handling operation in the error handling flow, the error handling flow management component 113 may adjust the error handling flow to begin a second error handling operation instead of the first error handling operation. The error handling flow management component 113 may continuously implement a closed feedback loop throughout the lifetime of the memory subsystem 110.

[0070] Some error handling operations may have high success rates but also high latency. For example, deep error handling techniques, such as HARQ operations, may have high success rates in recovering data but also high latency compared to, for example, read offset operations. Therefore, in some embodiments, the error handling stream management component 113 may track latency data for each error handling operation and reorder error handling operations in the error handling stream based on the latency data and / or the success rate of each error handling operation. The latency data may be stored in a data table or library of the memory subsystem 110 and may be determined and set during the manufacture of the memory subsystem 110 or during the programming and / or calibration of the memory subsystem 110. In some embodiments, the error handling stream management component 113 may reorder error handling operations based on latency data and success rate data. In some embodiments, the error handling stream management component 113 may use a set of rules involving assigning weights and values ​​between 0 and 1 to the latency data and the success rate data of each error handling operation in the error handling stream, and combining the weighted data to produce a position value for each error handling operation. Error handling stream management component 113 can sort error handling operations based on their corresponding position values. Different scales and any scoring values ​​can be used with each error handling operation to determine each position value. In other embodiments, error handling stream management component 113 may use machine learning methods, statistical data-based methods, or any other method to sort error handling operations in the error handling stream based on success rate data and latency data.

[0071] Figure 5 This is a flowchart of an example method 500 for error handling flow management implemented by a memory subsystem controller operating according to some embodiments of the present disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The error handling flow management component 113 executes. Although shown in a specific sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, in some embodiments, one or more operations may be omitted. Therefore, not all of the illustrated operations are required in each embodiment, and other processing flows are possible.

[0072] At operation 510, the processing logic detects read errors regarding data residing in a block of the memory device. In some embodiments, the block may be part of a block family associated with a voltage offset range.

[0073] At operation 520, the processing logic determines the order of error handling operations to be executed to recover data associated with the read error. For example, the processing logic may use metadata tables (e.g., metadata tables 410 and / or 420) to determine which error handling stream is associated with the voltage offset range, and the order (and parameters) of the error handling operations specified by the error handling stream.

[0074] At operation 530, the processing logic executes at least one error handling operation from the error handling stream. For example, the processing logic may execute the first error handling operation from the error handling stream. In response to the error handling operation failing to recover the data, the processing logic may execute the second error handling operation from the error handling stream, and so on.

[0075] At operation 540, the processing logic may perform adjustments to the error handling stream. For example, the adjustments may be made in response to one or more error handling operations in the error handling stream failing to recover data, satisfying a threshold criterion, etc. In some embodiments, the processing logic may adjust the order of error handling operations in the error handling stream. For example, the order may be adjusted based on the number of program-erase operations performed on the block exceeding a predetermined criterion, the success rate of error handling operations recovering data, and / or latency, etc. In some embodiments, the processing logic may maintain a record of the read error rate for a voltage offset interval, and in response to detecting that the read error rate meets a threshold criterion, the processing logic may adjust the read voltage offset associated with the error handling operation. In some embodiments, the processing logic may determine the proximity of the TAP value of the block to the TAP values ​​of adjacent voltage offset intervals, and adjust the read voltage offset based on the error handling stream associated with the adjacent voltage offset intervals. In some embodiments, the processing logic may perform a calibration procedure (e.g., cRLC) to determine the interval correlation of the block and increase the number of page samples associated with the calibration procedure. In some embodiments, the processing logic may determine the number of program-erase cycles associated with a block, and in response to determining that the number of program-erase cycles exceeds a predetermined threshold, adjust the order of error handling operations in the error handling stream or adjust the read voltage adjustment associated with one or more error handling operations. In some embodiments, the processing logic may update the order of error handling operations based on which error handling operation recovered data.

[0076] Figure 6 An example machine is described as a computer system 600, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1The memory subsystem 110) or can be used to perform controller operations (e.g., run an operating system to perform corresponding...). Figure 1 (Operation of the error handling flow management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0077] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0078] Example computer system 600 includes a processing device 602, main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 618, which communicate with each other via bus 630. Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 to perform the operations and steps discussed herein. The computer system 600 may additionally include a network interface device 608 for communication on the network 620.

[0079] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more instruction sets 626 or software embodying any or more of the methods or functions described herein are stored. Instructions 626 may also reside wholly or at least partially in main memory 604 and / or processing device 602 during execution by computer system 600, the main memory 604 and processing device 602 also constituting machine-readable storage medium. Machine-readable storage medium 624, data storage system 618 and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0080] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1 The error handling flow management component 113 provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0081] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0082] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0083] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0084] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0085] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0086] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory system comprising: Memory devices; and A processing device operatively coupled to the memory device to perform operations including: Detect read errors regarding data residing in a block of the memory device, wherein the block is associated with a voltage offset interval that defines a set of threshold voltage offsets applied to a base voltage read level during a read operation; Determine the order in which multiple error handling operations to be performed to recover data associated with the read error are performed, wherein the order is specified in a metadata table and is based on the voltage offset interval associated with the block; and At least one of the plurality of error handling operations is executed in the order specified in the metadata table.

2. The memory system of claim 1, wherein the processing device further performs operations including: Adjust the order of the multiple error handling operations.

3. The memory system of claim 1, wherein the processing device further performs operations including: Maintaining a record of the read error rate for the voltage offset range; and In response to detecting that the read error rate meets a threshold criterion, the read voltage offset associated with at least one error handling operation is adjusted.

4. The memory system of claim 1, wherein the processing device further performs operations including: The proximity of the post-programming time-of-application (TAP) value of the block to the TAP values ​​of adjacent voltage offset intervals is determined, and the read voltage offset is adjusted based on the error handling flow associated with the adjacent voltage offset intervals.

5. The memory system of claim 1, wherein the processing device further performs operations including: Perform a calibration procedure to determine the interval correlation of the block; and Increase the number of page samples associated with the calibration procedure.

6. The memory system of claim 1, wherein the processing means further performs operations including the following: Determine the number of programmable erase cycles associated with the block, and In response to determining that the number of program erase cycles exceeds a predetermined threshold, at least one of the order of the plurality of error handling operations or the read voltage adjustment associated with one of the error handling operations is adjusted.

7. The memory system of claim 1, wherein the processing means further performs operations including: The order of the plurality of error handling operations is updated based on which of the error handling operations recovered the data.

8. The memory system of claim 1, wherein the processing means further performs operations including: The order of the plurality of error handling operations is updated based on the latency data associated with each of the plurality of error handling operations.

9. A method of operating a memory device, comprising: Detect read errors regarding data residing in a block of the memory device, wherein the block is associated with a voltage offset interval that defines a set of threshold voltage offsets applied to a base voltage read level during a read operation; At least one of a plurality of error handling operations is performed in the order specified in the metadata table, wherein the order is based on the voltage offset range associated with the block; and Implement adjustments to the error handling flow.

10. The method of claim 9, wherein performing the adjustment to the error handling flow comprises: Adjust the order of the plurality of error handling operations in the error handling flow.

11. The method of claim 9, wherein performing the adjustment to the error handling flow comprises: Adjust the read voltage offset associated with the at least one error handling operation.

12. The method of claim 9, wherein performing the adjustment to the error handling flow comprises: The read voltage offset is adjusted based on another error handling stream associated with the adjacent voltage offset interval.

13. The method of claim 9, wherein performing the adjustment to the error handling flow comprises: Increase the number of page samples associated with the calibration procedure to determine the interval correlation of the block.

14. The method of claim 10, wherein the order of adjusting the plurality of error handling operations in the error handling stream is based on which of the plurality of error handling operations recovered the data.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means operatively coupled to a memory, perform operations including: Detect read errors regarding data residing in a block of memory device, wherein the block is associated with a voltage offset interval that defines a set of threshold voltage offsets applied to a base voltage read level during a read operation; Determine the order in which multiple error handling operations to be performed to recover data associated with the read error are performed, wherein the order is specified in a metadata table and is based on the voltage offset interval associated with the block; and At least one of the plurality of error handling operations is executed in the order specified in the metadata table.

16. The non-transitory computer-readable storage medium of claim 15, wherein the processing means further performs operations including: Adjust the order of the multiple error handling operations.

17. The non-transitory computer-readable storage medium of claim 15, wherein the processing means further performs operations including: Maintaining a record of the read error rate for the voltage offset range; and In response to detecting that the read error rate meets a threshold criterion, the read voltage offset associated with at least one error handling operation is adjusted.

18. The non-transitory computer-readable storage medium of claim 15, wherein the processing means further performs operations including: The proximity of the post-programming time-of-application (TAP) value of the block to the TAP values ​​of adjacent voltage offset intervals is determined, and the read voltage offset is adjusted based on the error handling flow associated with the adjacent voltage offset intervals.

19. The non-transitory computer-readable storage medium of claim 15, wherein the processing means further performs operations including: Perform a calibration procedure to determine the interval correlation of the block; and Increase the number of page samples associated with the calibration procedure.

20. The non-transitory computer-readable storage medium of claim 15, wherein the processing means further performs operations including: The order of the plurality of error handling operations is updated based on at least one of the following: which of the plurality of error handling operations recovered the data or the latency data associated with each of the plurality of error handling operations.

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