Fpga acceleration card power consumption test method, device and electronic equipment
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2022-06-23
- Publication Date
- 2026-05-29
AI Technical Summary
Existing FPGA accelerator card power consumption and heat dissipation testing methods cannot support adjusting the onboard voltage, resulting in incompatibility between tests on different servers and test scenarios.
By interacting with the CPLD and BMC, the onboard voltage value of the FPGA accelerator card is modified, and the firmware is upgraded after the modification takes effect to perform power consumption stress testing, ensuring the diversity and stability of the test scenarios.
We have implemented FPGA accelerator card power consumption testing under different servers and testing scenarios, ensuring the compatibility and stability of the tests.
Smart Images
Figure CN115114098B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer accelerator cards, and more specifically to a method, apparatus, and electronic device for testing the power consumption of FPGA accelerator cards. Background Technology
[0002] With the development of cloud computing, big data, and artificial intelligence technologies, CPUs (Central Processing Units) alone can no longer meet the computing power demands of various industries. Scenarios such as massive data analysis, machine learning, and edge computing require diverse computing architectures, necessitating collaboration between different processor architectures and heterogeneous computing technologies such as GPUs (Graphics Processing Units), NPUs (neural-network process units), and FPGAs (Field-Programmable Gate Arrays) to meet the algorithmic and specialized computing needs of specific fields. FPGA accelerator cards are increasingly favored by AI (Artificial Intelligence) users due to their customizability, low latency, and high performance-to-power ratio. The compatibility and stability of FPGA accelerator cards running on servers are particularly important.
[0003] FPGA accelerator card firmware typically comes in three types: static, dynamic, and full. A full version contains complete test logic and can be used to execute test programs. A static version contains only partial logic and cannot be used to execute test programs. A dynamic version needs to be used in conjunction with a static version to form complete logic, and the full version must be used during testing. In addition, there is a high-power version of firmware used for power consumption and thermal testing of FPGA accelerator cards. This version can provide FPGA core power consumption close to the maximum power consumption of the entire FPGA card. Besides the initial FPGA core power consumption, this version includes several power modules. The power consumption of each power module is not uniform, and the power modules can be enabled and the number of enabled power modules can be queried via commands.
[0004] Current FPGA accelerator card power consumption and heat dissipation tests involve flashing a high-power firmware version, enabling the high-power module under this version, and then performing stress tests. However, the onboard voltage of an FPGA accelerator card varies depending on the server it's paired with and the test scenario. Therefore, FPGA accelerator card manufacturers provide multiple versions of high-power firmware based on the onboard voltage. Performing stress tests requires adjusting the FPGA accelerator card's onboard voltage according to different test scenarios, then upgrading to the corresponding high-power firmware before conducting the stress test. Current testing methods do not support adjusting the FPGA accelerator card's onboard voltage. Summary of the Invention
[0005] The purpose of this invention is to provide a method, apparatus, and electronic device for testing the power consumption of FPGA accelerator cards that can be used with different servers and in different testing scenarios.
[0006] The technical solution of the present invention is as follows: Firstly, the present invention provides a method for testing the power consumption of an FPGA accelerator card, characterized in that the method includes:
[0007] Based on the CPLD receiving the first instruction sent by the BMC, the first instruction includes at least a modification instruction and a target voltage value;
[0008] Modify the onboard voltage value of the FPGA accelerator card according to the modification instructions and the target voltage value;
[0009] The CPLD receives a second instruction sent by the BMC, the second instruction including at least a save effective instruction;
[0010] Save the current onboard voltage value and make it effective according to the second instruction;
[0011] The firmware of the FPGA accelerator card is upgraded based on the current onboard voltage value, and a power consumption stress test is performed.
[0012] In a preferred embodiment, before the CPLD receives the first instruction sent by the BMC, wherein the first instruction includes at least a modification instruction and a target voltage value, the method further includes:
[0013] The CPLD receives a third instruction sent by the BMC, the third instruction including a version query instruction;
[0014] Query the CPLD version of the FPGA accelerator card according to the version query command;
[0015] Determine whether the CPLD version of the FPGA accelerator card supports modifying the onboard voltage;
[0016] If so, the CPLD receives the first instruction sent by the BMC.
[0017] In a preferred embodiment, after determining whether the CPLD version of the FPGA accelerator card supports modifying the onboard voltage and before receiving the first instruction sent by the BMC based on the CPLD, the method further includes:
[0018] The CPLD receives a fourth instruction, which includes a removal instruction and a target PCIe ID;
[0019] The FPGA accelerator card is removed from the operating system based on the fourth instruction.
[0020] The PCIe bridge port of the FPGA accelerator card is closed based on the target PCIe ID.
[0021] In a preferred embodiment, after closing the PCIe bridge port of the FPGA accelerator card based on the target PCIe ID and before receiving the first instruction sent by the BMC based on the CPLD, the method further includes:
[0022] The CPLD receives the fifth instruction sent by the BMC.
[0023] The fifth instruction pulls the program-b pin of the FPGA accelerator card low.
[0024] In a preferred embodiment, after the step of pulling down the program-b pin of the FPGA accelerator card based on the fifth instruction and before the step of receiving the first instruction sent by the BMC based on the CPLD, the method further includes:
[0025] The CPLD receives the sixth instruction sent by the BMC.
[0026] The voltage configuration switch of the FPGA accelerator card is turned on based on the sixth instruction.
[0027] In a preferred embodiment, after saving and activating the current onboard voltage value according to the second instruction, and before upgrading the firmware of the FPGA accelerator card based on the current onboard voltage value and performing a power consumption stress test, the method further includes:
[0028] The CPLD receives the seventh instruction sent by the BMC.
[0029] The program-b pin of the FPGA accelerator card is raised based on the seventh instruction.
[0030] In a preferred embodiment, after raising the program-b pin of the FPGA accelerator card based on the seventh instruction, and before upgrading the firmware of the FPGA accelerator card based on the current onboard voltage value and performing a power stress test, the method further includes:
[0031] The CPLD receives an eighth instruction, which includes a recovery instruction and the target PCIe ID;
[0032] Open the PCIe bridge port of the FPGA acceleration card based on the target PCIe ID;
[0033] The FPGA accelerator card is rescanned based on the recovery command.
[0034] In a preferred embodiment, after rescanning the FPGA accelerator card based on the recovery command and before upgrading the firmware of the FPGA accelerator card based on the current onboard voltage value and performing a power consumption stress test, the method further includes:
[0035] The CPLD receives the ninth instruction sent by the BMC, the ninth instruction including a verification instruction;
[0036] The current onboard voltage value of the FPGA accelerator card is verified based on the verification command.
[0037] Secondly, the present invention also provides an FPGA accelerator card power consumption testing device, the device comprising:
[0038] The first receiving module is used to receive a first instruction sent by the BMC based on the CPLD, the first instruction including at least a modification instruction and a target voltage value;
[0039] The modification module is used to modify the onboard voltage value of the FPGA acceleration card according to the modification instruction and the target voltage value;
[0040] The second receiving module is used to receive a second instruction sent by the BMC based on the CPLD, the second instruction including at least a save effective instruction;
[0041] The save and apply module is used to save the current onboard voltage value and apply it according to the second instruction.
[0042] The upgrade test module is used to upgrade the firmware of the FPGA accelerator card based on the current onboard voltage value and perform power consumption stress test.
[0043] Thirdly, the present invention also provides an electronic device, the device comprising: a processor, a memory, and a bus, wherein:
[0044] The processor and the memory communicate with each other via the bus;
[0045] The memory stores program instructions that can be executed by the processor, which can invoke the program instructions to perform the steps of the FPGA accelerator card power consumption test method as described in any one of the first aspects.
[0046] The advantages of this invention are: it provides an FPGA accelerator card power consumption testing method, apparatus, and electronic device. The method includes: receiving a first instruction sent by a BMC based on a CPLD, the first instruction including at least a modification instruction and a target voltage value; modifying the onboard voltage value of the FPGA accelerator card according to the modification instruction and the target voltage value; receiving a second instruction sent by a BMC based on a CPLD, the second instruction including at least a save and activate instruction; saving the current onboard voltage value according to the second instruction and activating it; upgrading the firmware of the FPGA accelerator card based on the current onboard voltage value and performing a power consumption stress test; modifying the onboard voltage value of the FPGA accelerator card through interaction between the BMC and the CPLD of the FPGA accelerator card, and then burning a high-power version of the firmware corresponding to the voltage value for high-power testing, thus enriching the testing scenarios of the FPGA accelerator card and ensuring the stability of the FPGA accelerator card. Attached Figure Description
[0047] The present invention will be further described below with reference to the accompanying drawings and embodiments:
[0048] Figure 1 This is a flowchart of the FPGA accelerator card power consumption test method provided in Embodiment 1 of the present invention;
[0049] Figure 2 This is a flowchart illustrating the FPGA accelerator card power consumption testing method provided in Embodiment 1 of the present invention;
[0050] Figure 3 This is a structural diagram of the FPGA accelerator card power consumption testing device provided in Embodiment 2 of the present invention;
[0051] Figure 4 This is an architectural diagram of the electronic device provided in Embodiment 3 of the present invention. Detailed Implementation
[0052] FPGAs will bring more advanced AI computing acceleration solutions to servers, helping users flexibly migrate workloads and algorithms. They will provide powerful computing acceleration for applications such as video transcoding, risk management, data analysis, security, and medicine, helping users improve work efficiency and reduce operating costs.
[0053] Example 1: This example provides a method for testing the power consumption of an FPGA accelerator card, referring to... Figure 1 and Figure 2As shown, the method includes:
[0054] S1A0-1: CPLD receives third instructions sent by BMC, including version query instructions.
[0055] Specifically, a CPLD chip is installed on the FPGA accelerator card, and the CPLD chip communicates with the BMC. The CPLD is mainly composed of programmable logic macrocells (MCs) surrounding a central programmable interconnect matrix. The MC structure is relatively complex and has a complex I / O unit interconnect structure. It can generate specific circuit structures as needed to complete certain functions. It is small in size, has simple application circuits, low power consumption, and its development environment programmable language is completely consistent with that of the FPGA accelerator card. The use of CPLD for related accelerator card data acquisition and processing applications does not interfere with the FPGA acceleration function.
[0056] BMC (Baseboard Management Controller) is a small operating system independent of the server system, which facilitates remote management, monitoring, installation, and restart of the server.
[0057] S1A0-2: Query the CPLD version of the FPGA acceleration card using the version query command.
[0058] S1A0-3. Determine whether the CPLD version of the FPGA accelerator card supports modifying the onboard voltage.
[0059] If so, proceed to S1B0.
[0060] S1B0-1 receives a fourth instruction based on the CPLD. The fourth instruction includes a removal instruction and a target PCIe ID.
[0061] S1B0-2, Remove the FPGA accelerator card under the operating system based on the fourth instruction.
[0062] Specifically, after confirming that the current FPGA accelerator card's CPLD version supports modifying the onboard voltage, the onboard voltage of the current FPGA accelerator card will be modified before power consumption testing. The FPGA accelerator card needs to be removed for subsequent onboard voltage modification and power consumption testing. Specifically, according to the fourth instruction, the FPGA accelerator card is removed in the OS using the command `echo 1 > / sys / bus / pci / devices / xxxx:xx:xx.xx / remove`, where `xxxx:xx:xx.xx` is the PCIe ID of the FPGA accelerator card.
[0063] S1B0-3, disable the PCIe bridge port of the FPGA acceleration card based on the target PCIe ID.
[0064] Specifically, the PCIe bridge port of the FPGA accelerator card is disabled using the setpci -s command.
[0065] S1C0-1, based on CPLD receiving the fifth instruction sent by BMC.
[0066] S1C0-2, pulls the program-b pin of the FPGA accelerator card low based on the fifth instruction.
[0067] S1D0-1, Receive the sixth instruction sent by the BMC based on the CPLD;
[0068] S1D0-2, based on the sixth instruction, turns on the voltage configuration switch of the FPGA accelerator card.
[0069] S110. Receive the first instruction sent by the BMC based on the CPLD. The first instruction includes at least a modification instruction and a target voltage value.
[0070] Specifically, the CPLD chip communicates with the BMC via PCIE SMBUS. After confirming that the current CPLD version of the FPGA accelerator card supports modifying the onboard voltage, the CPLD receives the onboard voltage modification instruction sent by the BMC, namely the first instruction. The first instruction includes at least the modification instruction and the target voltage value so that the CPLD can make specific modifications to the onboard voltage of the FPGA accelerator card.
[0071] S120. Modify the onboard voltage value of the FPGA accelerator card according to the modification instructions and target voltage value.
[0072] Specifically, the onboard voltage value of the FPGA accelerator card is modified to the target voltage value. The first instruction can be one or more; that is, the BMC may send one first instruction to the FPGA accelerator card's CPLD, or it may send two or more first instructions to the FPGA accelerator card's CPLD. As long as the FPGA accelerator card's CPLD receives the modification instruction and the target voltage value, the onboard voltage value of the FPGA accelerator card is modified accordingly.
[0073] S130. Receive a second instruction sent by the BMC based on the CPLD, the second instruction including at least a save effective instruction.
[0074] Specifically, the CPLD of the FPGA accelerator card will stop modifying the onboard voltage value of the FPGA accelerator card only after receiving the save and apply command sent by the BMC.
[0075] S140. Save the current onboard voltage value and make it effective according to the second instruction.
[0076] S1E0-1, Receive the seventh instruction sent by the BMC based on the CPLD.
[0077] S1E0-2, raising the program-b pin of the FPGA accelerator card based on the seventh instruction.
[0078] Specifically, after saving and enabling the current onboard voltage value of the FPGA accelerator card, the program-b pin of the FPGA accelerator card is pulled high to restore it.
[0079] S1F0-1 receives the eighth instruction based on the CPLD. The eighth instruction includes a recovery instruction and the target PCIe ID.
[0080] S1F0-2, Open the PCIe bridge port of the FPGA acceleration card based on the target PCIe ID.
[0081] Specifically, the PCIe bridge port of the FPGA accelerator card is opened using the setpci -s command.
[0082] S1F0-3, Rescan the FPGA accelerator card based on recovery instructions.
[0083] Specifically, the FPGA accelerator card is rescanned using the command `echo 1 > / sys / bus / pci / devices / xxxx:xx:xx.xx / rescan`, where xxxx:xx:xx.xx is the PCIe ID of the FPGA accelerator card.
[0084] S1G0-1: CPLD receives the ninth instruction sent by BMC, which includes a verification instruction.
[0085] S1G0-2 verifies the current onboard voltage value of the FPGA accelerator card based on the verification command.
[0086] S150: Upgrade the firmware of the FPGA accelerator card based on the current onboard voltage value and perform a power consumption stress test.
[0087] This embodiment provides a method, apparatus, and electronic device for testing the power consumption of an FPGA accelerator card. The method includes: receiving a first instruction sent by a BMC based on a CPLD, the first instruction including at least a modification instruction and a target voltage value; modifying the onboard voltage value of the FPGA accelerator card according to the modification instruction and the target voltage value; receiving a second instruction sent by the BMC based on a CPLD, the second instruction including at least a save effective instruction; saving the current onboard voltage value according to the second instruction and making it effective; upgrading the firmware of the FPGA accelerator card based on the current onboard voltage value and performing a power consumption stress test; modifying the onboard voltage value of the FPGA accelerator card through interaction between the BMC and the CPLD of the FPGA accelerator card, and verifying the current onboard voltage value of the FPGA accelerator card after the modification takes effect. After successful verification, a high-power version of the firmware corresponding to the voltage value is burned for high-power testing, and then another high-power version of the firmware corresponding to the voltage value is burned for high-power testing. This enriches the testing scenarios for the FPGA accelerator card and ensures the stability of the FPGA accelerator card.
[0088] Example 2: Corresponding to Example 1 above, this example provides an FPGA accelerator card power consumption testing device, referring to... Figure 3 As shown, the device includes:
[0089] The first receiving module 310 is used to receive a first instruction sent by the BMC based on the CPLD, the first instruction including at least a modification instruction and a target voltage value;
[0090] Modification module 320 is used to modify the onboard voltage value of the FPGA acceleration card according to the modification instruction and the target voltage value;
[0091] The second receiving module 330 is used to receive a second instruction sent by the BMC based on the CPLD, the second instruction including at least a save effective instruction;
[0092] The save and apply module 340 is used to save the current onboard voltage value and apply it according to the second instruction;
[0093] The upgrade test module 350 is used to upgrade the firmware of the FPGA accelerator card based on the current onboard voltage value and perform power consumption stress test.
[0094] In one embodiment, the device further includes:
[0095] The third receiving module 361 is used to receive a third instruction sent by the BMC based on the CPLD before the first receiving module 310 receives a first instruction sent by the BMC based on the CPLD, the first instruction including at least a modification instruction and a target voltage value. The third instruction includes a version query instruction.
[0096] Query module 362 is used to query the CPLD version of the FPGA accelerator card according to the version query instruction;
[0097] The judgment module 363 is used to determine whether the CPLD version of the FPGA acceleration card supports modifying the onboard voltage;
[0098] If so, the first receiving module 310 receives the first instruction sent by the BMC based on the CPLD.
[0099] Preferably, the device further includes:
[0100] The fourth receiving module 371 is used to receive a fourth instruction based on the CPLD after the judging module 363 judges whether the CPLD version of the FPGA acceleration card supports modifying the onboard voltage. The fourth instruction includes a removal instruction and a target PCIe ID.
[0101] The removal module 372 is used to remove the FPGA accelerator card under the operating system based on the fourth instruction;
[0102] Shutdown module 373 is used to shut down the PCIe bridge port of the FPGA accelerator card based on the target PCIe ID.
[0103] More preferably, the device further includes:
[0104] The fifth receiving module 381 is used to receive the fifth instruction sent by the BMC based on the CPLD after the closing module 373 closes the PCIe bridge port of the FPGA accelerator card based on the target PCIe ID and before the first receiving module 310 receives the first instruction sent by the BMC based on the CPLD.
[0105] The pull-low module 382 is used to pull the program-b pin of the FPGA accelerator card low based on the fifth instruction.
[0106] More preferably, the device further includes:
[0107] The sixth receiving module 391 is used to receive the sixth instruction sent by the BMC based on the CPLD after the pull-low module 382 pulls low the program-b pin of the FPGA accelerator card based on the fifth instruction and before the first receiving module 310 receives the first instruction sent by the BMC based on the CPLD.
[0108] Switch module 392 is used to turn on the voltage configuration switch of the FPGA accelerator card based on the sixth instruction.
[0109] More preferably, the device further includes:
[0110] The seventh receiving module 3A1 is used to receive the sixth instruction sent by the BMC based on the CPLD after the save and activate module 340 saves the current onboard voltage value according to the second instruction and activates it, and before the upgrade test module 350 upgrades the firmware of the FPGA accelerator card based on the current onboard voltage value and performs a power consumption stress test.
[0111] The elevation module 3A2 is used to elevate the program-b pin of the FPGA accelerator card based on the sixth instruction.
[0112] More preferably, the device further includes:
[0113] The eighth receiving module 3B1 is used to receive an eighth instruction based on the CPLD after the rise module 3A2 raises the program-b pin of the FPGA accelerator card based on the seventh instruction, and before the upgrade test module 350 upgrades the firmware of the FPGA accelerator card based on the current onboard voltage value and performs a power consumption stress test. The eighth instruction includes a recovery instruction and the target PCIe ID.
[0114] Enable module 3B2, used to open the PCIe bridge port of the FPGA acceleration card based on the target PCIe ID;
[0115] The scanning module 3B3 is used to rescan the FPGA accelerator card based on the recovery command.
[0116] More preferably, the device further includes:
[0117] The ninth receiving module 3C1 is used to receive a ninth instruction sent by the BMC based on the CPLD after the scanning module 3B3 rescans the FPGA accelerator card based on the recovery instruction and before the upgrade test module 350 upgrades the firmware of the FPGA accelerator card based on the current onboard voltage value and performs a power consumption stress test. The ninth instruction includes a verification instruction.
[0118] The verification module 3C2 is used to verify the current onboard voltage value of the FPGA accelerator card based on the verification command.
[0119] Example 3: Corresponding to Examples 1 and 2 above, the following will be combined with... Figure 4 This application provides a description of the electronic device, which includes: a processor 410, a memory 420, and a bus 430, wherein:
[0120] The processor 410 and the memory 420 communicate with each other through the bus 430;
[0121] The memory 420 stores program instructions that can be executed by the processor 410. The processor 410 can execute the following steps by calling the program instructions:
[0122] Based on the CPLD receiving the first instruction sent by the BMC, the first instruction includes at least a modification instruction and a target voltage value;
[0123] Modify the onboard voltage value of the FPGA accelerator card according to the modification instructions and the target voltage value;
[0124] The CPLD receives a second instruction sent by the BMC, the second instruction including at least a save effective instruction;
[0125] Save the current onboard voltage value and make it effective according to the second instruction;
[0126] The firmware of the FPGA accelerator card is upgraded based on the current onboard voltage value, and a power consumption stress test is performed.
[0127] In one embodiment, the processor 410 can also perform the following steps by calling the program instructions:
[0128] The CPLD receives a third instruction sent by the BMC, the third instruction including a version query instruction;
[0129] Query the CPLD version of the FPGA accelerator card according to the version query command;
[0130] Determine whether the CPLD version of the FPGA accelerator card supports modifying the onboard voltage;
[0131] If so, the CPLD receives the first instruction sent by the BMC.
[0132] Preferably, the processor 410, when invoking the program instructions, can also perform the following steps:
[0133] The CPLD receives a fourth instruction, which includes a removal instruction and a target PCIe ID;
[0134] The FPGA accelerator card is removed from the operating system based on the fourth instruction.
[0135] The PCIe bridge port of the FPGA accelerator card is closed based on the target PCIe ID.
[0136] Preferably, the processor 410, when invoking the program instructions, can also perform the following steps:
[0137] The CPLD receives the fifth instruction sent by the BMC.
[0138] The fifth instruction pulls the program-b pin of the FPGA accelerator card low.
[0139] Preferably, the processor 410, when invoking the program instructions, can also perform the following steps:
[0140] The CPLD receives the sixth instruction sent by the BMC.
[0141] The voltage configuration switch of the FPGA accelerator card is turned on based on the sixth instruction.
[0142] Preferably, the processor 410, when invoking the program instructions, can also perform the following steps:
[0143] The CPLD receives the seventh instruction sent by the BMC.
[0144] The program-b pin of the FPGA accelerator card is raised based on the seventh instruction.
[0145] Preferably, the processor 410, when invoking the program instructions, can also perform the following steps:
[0146] The CPLD receives an eighth instruction, which includes a recovery instruction and the target PCIe ID;
[0147] Open the PCIe bridge port of the FPGA acceleration card based on the target PCIe ID;
[0148] The FPGA accelerator card is rescanned based on the recovery command.
[0149] Preferably, the processor 410, when invoking the program instructions, can also perform the following steps:
[0150] The CPLD receives the ninth instruction sent by the BMC, the ninth instruction including a verification instruction;
[0151] The current onboard voltage value of the FPGA accelerator card is verified based on the verification command.
[0152] in, Figure 4 An exemplary architecture of an electronic device is shown, which may include a processor 410, a video display adapter 411, a disk drive 412, an input / output interface 413, a network interface 414, and a memory 420. The processor 410, video display adapter 411, disk drive 412, input / output interface 413, network interface 414, and memory 420 can communicate with each other via a communication bus 430.
[0153] The processor 410 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to achieve the technical solution provided in this application.
[0154] The memory 420 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 420 can store the operating system 421 for controlling the operation of the electronic device 400, and the basic input / output system (BIOS) 422 for controlling the low-level operations of the electronic device 400. Additionally, it can store a web browser 423, data storage management 424, and an icon font processing system 425, etc. The aforementioned icon font processing system 425 can be the application program that specifically implements the aforementioned steps in this embodiment. In summary, when the technical solution provided in this application is implemented through software or firmware, the relevant program code is stored in the memory 420 and is called and executed by the processor 410.
[0155] Input / output interface 413 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.
[0156] Network interface 414 is used to connect a communication module (not shown in the figure) to enable communication and interaction between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).
[0157] Bus 430 includes a pathway for transmitting information between various components of the device, such as processor 410, video display adapter 411, disk drive 412, input / output interface 413, network interface 414, and memory 420.
[0158] In addition, the electronic device 400 can also obtain information on specific acquisition conditions from the virtual resource object acquisition condition information database 441 for condition judgment, etc.
[0159] It should be noted that although the above-described electronic device 400 only shows a processor 410, a video display adapter 411, a disk drive 412, an input / output interface 413, a network interface 414, a memory 420, a bus 430, etc., in specific implementations, the electronic device may also include other components necessary for normal operation.
[0160] Furthermore, those skilled in the art will understand that the above-described device may contain only the components necessary to implement the solution of this application, and need not contain all the components shown in the figures.
[0161] Example 4: Corresponding to Examples 1 to 3 above, this example provides a computer-readable storage medium storing computer instructions that cause the computer to perform the following steps:
[0162] Based on the CPLD receiving the first instruction sent by the BMC, the first instruction includes at least a modification instruction and a target voltage value;
[0163] Modify the onboard voltage value of the FPGA accelerator card according to the modification instructions and the target voltage value;
[0164] The CPLD receives a second instruction sent by the BMC, the second instruction including at least a save effective instruction;
[0165] Save the current onboard voltage value and make it effective according to the second instruction;
[0166] The firmware of the FPGA accelerator card is upgraded based on the current onboard voltage value, and a power consumption stress test is performed.
[0167] In one implementation, the computer further instructs itself to perform the following steps:
[0168] The CPLD receives a third instruction sent by the BMC, the third instruction including a version query instruction;
[0169] Query the CPLD version of the FPGA accelerator card according to the version query command;
[0170] Determine whether the CPLD version of the FPGA accelerator card supports modifying the onboard voltage;
[0171] If so, the CPLD receives the first instruction sent by the BMC.
[0172] In one implementation, the computer further instructs itself to perform the following steps:
[0173] The CPLD receives a fourth instruction, which includes a removal instruction and a target PCIe ID;
[0174] The FPGA accelerator card is removed from the operating system based on the fourth instruction.
[0175] The PCIe bridge port of the FPGA accelerator card is closed based on the target PCIe ID.
[0176] In one implementation, the computer further instructs itself to perform the following steps:
[0177] The CPLD receives the fifth instruction sent by the BMC.
[0178] The fifth instruction pulls the program-b pin of the FPGA accelerator card low.
[0179] In one implementation, the computer further instructs itself to perform the following steps:
[0180] The CPLD receives the sixth instruction sent by the BMC.
[0181] The voltage configuration switch of the FPGA accelerator card is turned on based on the sixth instruction.
[0182] In one implementation, the computer further instructs itself to perform the following steps:
[0183] The CPLD receives the seventh instruction sent by the BMC.
[0184] The program-b pin of the FPGA accelerator card is raised based on the seventh instruction.
[0185] In one implementation, the computer further instructs itself to perform the following steps:
[0186] The CPLD receives an eighth instruction, which includes a recovery instruction and the target PCIe ID;
[0187] Open the PCIe bridge port of the FPGA acceleration card based on the target PCIe ID;
[0188] The FPGA accelerator card is rescanned based on the recovery command.
[0189] In one implementation, the computer further instructs itself to perform the following steps:
[0190] The CPLD receives the ninth instruction sent by the BMC, the ninth instruction including a verification instruction;
[0191] The current onboard voltage value of the FPGA accelerator card is verified based on the verification command.
[0192] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, cloud server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.
[0193] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.
[0194] It should also be noted that the terms "first," "second," ... "eighth," "ninth" in this invention are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," ... "eighth," "ninth" may explicitly or implicitly include one or more of that feature.
[0195] Of course, the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the scope of protection of the present invention. All modifications made according to the spirit and essence of the main technical solution of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A method for testing the power consumption of an FPGA accelerator card, characterized in that, The method includes: Based on the CPLD receiving the first instruction sent by the BMC, the first instruction includes at least a modification instruction and a target voltage value; Modify the onboard voltage value of the FPGA accelerator card according to the modification instructions and the target voltage value; The CPLD receives a second instruction sent by the BMC, the second instruction including at least a save effective instruction; Save the current onboard voltage value and make it effective according to the second instruction; The method further includes upgrading the firmware of the FPGA accelerator card based on the current onboard voltage value and performing a power consumption stress test; before the CPLD receives the first instruction sent by the BMC, wherein the first instruction includes at least a modification instruction and a target voltage value, the method also includes: The CPLD receives a third instruction sent by the BMC, the third instruction including a version query instruction; Query the CPLD version of the FPGA accelerator card according to the version query command; Determine whether the CPLD version of the FPGA accelerator card supports modifying the onboard voltage; If so, the CPLD receives the first instruction sent by the BMC.
2. The FPGA accelerator card power consumption testing method according to claim 1, characterized in that, After determining whether the CPLD version of the FPGA acceleration card supports modifying the onboard voltage, and before receiving the first instruction sent by the BMC based on the CPLD, the method further includes: The CPLD receives a fourth instruction, which includes a removal instruction and a target PCIe ID; The FPGA accelerator card is removed from the operating system based on the fourth instruction. The PCIe bridge port of the FPGA accelerator card is closed based on the target PCIe ID.
3. The FPGA accelerator card power consumption testing method according to claim 2, characterized in that, After closing the PCIe bridge port of the FPGA acceleration card based on the target PCIe ID, and before receiving the first instruction sent by the BMC based on the CPLD, the method further includes: The CPLD receives the fifth instruction sent by the BMC. The fifth instruction pulls the program-b pin of the FPGA accelerator card low.
4. The FPGA accelerator card power consumption testing method according to claim 3, characterized in that, After the fifth instruction pulls the program-b pin of the FPGA accelerator card low, and before the CPLD receives the first instruction sent by the BMC, the method further includes: The CPLD receives the sixth instruction sent by the BMC. The voltage configuration switch of the FPGA accelerator card is turned on based on the sixth instruction.
5. The FPGA accelerator card power consumption testing method according to claim 4, characterized in that, After saving and activating the current onboard voltage value according to the second instruction, and before upgrading the firmware of the FPGA accelerator card based on the current onboard voltage value and performing a power consumption stress test, the method further includes: The CPLD receives the seventh instruction sent by the BMC. The program-b pin of the FPGA accelerator card is raised based on the seventh instruction.
6. The FPGA accelerator card power consumption testing method according to claim 5, characterized in that, After raising the program-b pin of the FPGA accelerator card based on the seventh instruction, and before upgrading the firmware of the FPGA accelerator card based on the current onboard voltage value and performing a power consumption stress test, the method further includes: The CPLD receives an eighth instruction, which includes a recovery instruction and the target PCIe ID; Open the PCIe bridge port of the FPGA acceleration card based on the target PCIe ID; The FPGA accelerator card is rescanned based on the recovery command.
7. The FPGA accelerator card power consumption testing method according to claim 6, characterized in that, After rescanning the FPGA accelerator card based on the recovery command, and before upgrading the firmware of the FPGA accelerator card based on the current onboard voltage value and performing a power consumption stress test, the method further includes: The CPLD receives the ninth instruction sent by the BMC, the ninth instruction including a verification instruction; The current onboard voltage value of the FPGA accelerator card is verified based on the verification command.
8. An FPGA accelerator card power consumption testing device for implementing the FPGA accelerator card power consumption testing method as described in claim 1, characterized in that, The device includes: The first receiving module is used to receive a first instruction sent by the BMC based on the CPLD, the first instruction including at least a modification instruction and a target voltage value; The modification module is used to modify the onboard voltage value of the FPGA acceleration card according to the modification instruction and the target voltage value; The second receiving module is used to receive a second instruction sent by the BMC based on the CPLD, the second instruction including at least a save effective instruction; The save and apply module is used to save the current onboard voltage value and apply it according to the second instruction. The upgrade test module is used to upgrade the firmware of the FPGA accelerator card based on the current onboard voltage value and perform power consumption stress test.
9. An electronic device, characterized in that, The device includes: a processor, a memory, and a bus, wherein: The processor and the memory communicate with each other via the bus; The memory stores program instructions that can be executed by the processor, and the processor can call the program instructions to perform the steps of the FPGA accelerator card power consumption test method as described in any one of claims 1 to 7.