A duty cycle regulator

Abstract

The present invention relates to a duty cycle regulator, comprising: N number of duty cycle pre-regulation PRE_DCA circuits, each PRE_DCA circuit being arranged in parallel in a delay-locked loop (DLL) circuit and configured to widen the high-level portion of the corresponding phase of the N-phase input signal; and M number of duty cycle adjustment DCA circuits, each DCA circuit being arranged in parallel in the DLL circuit and coupled to the corresponding PRE_DCA circuit, and each DCA circuit being configured to: receive a signal from the corresponding PRE_DCA circuit, and further adjust the duty cycle of the signal output from the corresponding PRE_DCA circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and more particularly, to a duty cycle regulator. Background Art

[0002] For some semiconductor devices, there may be a need to adjust the duty cycle. In some cases, it may be desirable to adjust only the rising edge while keeping the falling edge unchanged.

[0003] For example, for DDR5, the duty cycle of the bidirectional data control pin (DQS) internal clock can be adjusted according to Section 4.41 of the JEDEC (Solid State Electronics Association) JESD79-5A specification standard. However, the duty cycle adjustment may affect the tDQSCK timing, which is not expected. Summary of the Invention

[0004] The present invention relates to a duty cycle regulator, comprising: N number of duty cycle pre-regulation PRE_DCA circuits, each PRE_DCA circuit being arranged in parallel in a delay locked loop (DLL) circuit and configured to widen the high level portion of the corresponding phase of the N-phase input signal; and M number of duty cycle adjustment DCA circuits, each DCA circuit being arranged in parallel in the DLL circuit and coupled to the corresponding PRE_DCA circuit, and each

[0005] The DCA circuit is configured to receive a signal from a corresponding PRE_DCA circuit and further adjust a duty cycle of the signal output from the corresponding PRE_DCA circuit.

[0006] As described above, the duty cycle regulator, the input signal is a pulse signal, wherein each PRE_DCA circuit is configured to widen the high-level portion of the corresponding phase of the N-phase input signal, including: delaying the falling edge of the corresponding phase of the N-phase pulse signal by a first amount as a default state; wherein each DCA circuit is configured to adjust the duty cycle of the signal output from the corresponding PRE_DCA circuit, including: delaying the rising edge of the signal output from the corresponding PRE_DCA circuit by a second amount to shorten the high-level portion of the signal, wherein the default setting of each DCA circuit is to make the second amount equal to the first amount to compensate for the widening of the signal by the PRE_DCA circuit.

[0007] In the duty cycle regulator as described above, the DCA circuit includes a first DCA circuit for a first phase of an N-phase input signal, wherein the DLL circuit realigns a rising edge of a first signal output from the first DCA circuit with a rising edge of a clock signal of the DLL circuit after locking, and at this time, a falling edge of the signal output from the first DCA circuit is also realigned with a falling edge of the clock signal of the DLL circuit; and respective phases of signals output from the second DCA circuit to the Mth DCA circuit are respectively shifted by the same amount as the first signal based on a fixed phase relationship with the first phase.

[0008] As described above, each of the second to Mth DCA circuits is further configured to: after the DLL is locked, further change the duty cycle of the signal received from the corresponding PRE_DCA according to the received control signal.

[0009] As described above, each DCA in the second DCA to Mth DCA circuits can be configured to change the duty cycle of the signal by adjusting the rising edge of the signal received from the corresponding PRE_DCA, wherein adjusting the rising edge includes one or more of delaying the rising edge, advancing the rising edge, or not changing the rising edge.

[0010] As described above, each DCA circuit can independently adjust the duty cycle of the signal received from the corresponding PRE_DCA according to the control signal received by the DCA circuit.

[0011] As described above for the duty cycle regulator, N is equal to M.

[0012] As described above, the duty cycle regulator, each PRE_DCA circuit includes an inverter, a delay component, and an NOR gate, wherein in each PRE_DCA circuit: the first input of the NOR gate is the corresponding phase of the original input pulse, and the second input is the corresponding phase of the original input pulse passing through the delay component of the PRE_DCA circuit; and wherein each DCA circuit includes an inverter, a delay component, and an NAND gate, wherein in each DCA circuit: the first input of the NAND gate is the input pulse from the corresponding PRE_DCA circuit, and the second input is the input pulse from the corresponding PRE_DCA circuit and passing through the delay component of the DCA circuit.

[0013] The duty cycle regulator as described above includes a duty cycle regulator for the internal clock of the DDR5 four-phase bidirectional data control pin DQS, and N and M are 4.

[0014] As described above, the delay component of each PRE_DCA circuit of the duty cycle regulator includes 14 delay units, and each PRE_DCA circuit is configured to: widen the high-level part of the input signal by a fixed 7 steps at the falling edge by enabling 7 delay units among the 14 delay units as a default setting.

[0015] As described above, the duty cycle regulator is configured to use the corresponding mode register to specify the duty cycle adjustment of the corresponding DCA circuit, wherein: the mode register MR43 OP[2:0] is used to specify the step of the second DCA to adjust the duty cycle of the second phase, and MR43 OP[3] is used to specify the positive or negative sign of the step, and the step includes -7 to +7, a total of 14 steps; the mode register MR43 OP[6:4] is used to specify the step of the third DCA to adjust the duty cycle of the third phase, and MR43 OP[7] is used to specify the positive or negative sign of the step, and the step includes -7 to +7, a total of 14 steps; the mode register MR44 OP[2:0] is used to specify the step of the fourth DCA to adjust the duty cycle of the fourth phase, and MR44 is used to specify the positive or negative sign of the step. OP[3] is used to specify the positive or negative sign of the step, and the steps include 14 steps from -7 to +7, and the delay components of each PRE_DCA circuit and each DCA circuit include 14 delay units connected in parallel and whose states can be adjusted independently. The 14 steps are realized by utilizing different state combinations of the 14 delay units connected in parallel, wherein the state of each delay unit includes "1" or "0", and the state "1" of each delay unit indicates a valid state in which a delay is generated, and the state "0" indicates an invalid state in which no delay is generated.

[0016] As described above, the duty cycle regulator, each DCA circuit is configured to adjust the high-level portion of the corresponding phase of the signal output from the PRE_DCA circuit, including: performing 7 steps for shortening the high level of the corresponding phase output from the corresponding PRE_DCA circuit as a default setting to compensate for the 7 steps for widening in the PRE_DCA circuit, wherein the default setting includes setting 7 delay components among the 14 DCA circuits to state 1, so that the rising edge of the corresponding phase output from the corresponding DCA circuit is delayed by 7 steps.

[0017] As described above, the default setting of each of the second DCA, the third DCA and the fourth DCA corresponds to the state of "step = 0", and each of the second DCA, the third DCA and the fourth DCA can be configured to: change the duty cycle of the signal by adjusting the rising edge of the signal received from the corresponding PRE_DCA by -7 to +7 steps, wherein steps +1 to +7 respectively correspond to 8 to 14 of the 14 delay units being set to state 1, and steps -1 to -7 respectively correspond to 6 to 0 of the 14 delay units being set to state 1.

[0018] In the duty cycle regulator as described above, the delay unit is a capacitor, and the capacitor is a NAND gate or a NOR gate, including two PMOSs and two NMOSs.

[0019] As described above, the duty cycle regulator has an adjustment range of 2ps-4ps for each step, and a total adjustment range of 28ps-56ps for 14 steps.

[0020] As described above, the DLL circuit includes a frequency divider configured to divide a four-phase input signal into a first phase, a second phase, a third phase, and a fourth phase, wherein adjacent phases thereof differ by π / 2.

[0021] The present invention also relates to a delay phase-locked loop (DLL) circuit, which includes the duty cycle regulator as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to further illustrate various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It should be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope of protection claimed in the present invention.

[0023] In addition, it should be understood that the drawings illustrate the main connection relationships of the various components, rather than all connection relationships. Moreover, for the purpose of explaining the technical solutions of the present invention, the drawings show exemplary components. More or fewer components may be included in actual applications.

[0024] Figure 1 It is a schematic diagram of the duty cycle adjustment of the four-phase signal;

[0025] Figure 2 is a schematic diagram showing the range and steps of duty cycle adjustment;

[0026] Figure 3a It is a duty cycle adjustment circuit and its timing diagram for increasing the duty cycle of a signal;

[0027] Figure 3bIt is a duty cycle adjustment circuit and its timing diagram for reducing the duty cycle of a signal;

[0028] Figure 4a It is the duty cycle pre-adjustment (PRE_DCA) circuit and its timing diagram;

[0029] Figure 4b It is the duty cycle adjustment (DCA) circuit and its timing diagram;

[0030] Figures 5a-5c is a non-limiting example of a delay component for duty cycle adjustment;

[0031] Figure 6a-6b A schematic diagram of a DLL (delay locked loop) circuit including a PRE_DCA circuit and a DCA circuit, and a timing diagram of output signals of the PRE_DCA circuit and the DCA circuit; and

[0032] Figure 7 Schematic diagram of a DCA circuit and the corresponding relationship between the mode register bits of each phase of a multiphase signal and the states of the step and delay components used for duty cycle adjustment. DETAILED DESCRIPTION

[0033] The following detailed description refers to the accompanying drawings. The accompanying drawings illustrate, by way of example, specific embodiments in which the claimed subject matter may be practiced. It should be understood that the following specific embodiments are intended to provide specific descriptions of typical examples for illustrative purposes and should not be construed as limiting the present invention. Persons skilled in the art, provided they fully understand the spirit and purpose of the present invention, may make appropriate modifications and adjustments to the disclosed embodiments without departing from the spirit and scope of the claimed subject matter.

[0034] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of each described embodiment. However, it will be apparent to one of ordinary skill in the art that the various described embodiments can be practiced without these specific details. Unless otherwise defined, technical and scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0035] The terms "first", "second", etc. in the specification and claims of this application do not imply any order, quantity or importance, but are merely used to distinguish different components or features. An embodiment is an exemplary implementation or example. References in the specification to "an embodiment", "one embodiment", "some embodiments", "various embodiments" or "other embodiments" mean that the specific features, configurations or characteristics described in conjunction with the embodiment are included in at least some embodiments of the present technology, but not necessarily all embodiments. The various appearances of "an embodiment", "one embodiment", or "some embodiments" do not necessarily refer to the same embodiment. Elements or aspects from one embodiment may be combined with elements or aspects of another embodiment.

[0036] The present invention relates to a duty cycle adjuster, comprising: N duty cycle pre-adjustment (PRE_DCA) circuits, each of which can be arranged in parallel within a delay-locked loop (DLL) circuit and configured to widen the high-level portion of a corresponding phase of an N-phase input signal; and M duty cycle adjustment (DCA) circuits, each of which can be arranged in parallel within the DLL circuit and coupled to a corresponding PRE_DCA circuit. Each DCA circuit can be configured to receive a signal from a corresponding PRE_DCA circuit and further adjust the duty cycle of the signal output from the corresponding PRE_DCA circuit. The present invention implements duty cycle adjustment after the DLL is locked without changing or affecting tDQSCK timing, as described in more detail below.

[0037] In the following description, for ease of understanding, the detailed description of the technical solution of the present invention is primarily focused on DDR5. However, it should be understood that the duty cycle adjustment technology of the present invention is not limited to DDR5. The technical solution of the present invention can be used in any use case requiring duty cycle adjustment. In particular, the technology of the present application is more beneficial when it is desired to adjust the rising edge while keeping the falling edge unchanged.

[0038] For DDR5, the DDR5 duty cycle regulator can be applied to the bidirectional data control pin (DQS) clock tree according to Section 4.41 of the JEDEC (Solid State Electronics Association) JESD79-5A specification standard. Different mode register definitions can be used for single-phase and multi-phase DQS internal clocks. For example, the mode register MR43 OP[3:0] can be used for a single-phase DQS internal clock, while MR43OP[7:0] or MR44 OP[3:0] can be used for a multi-phase DQS internal clock. When using DDR5, the present invention is mainly directed to duty cycle adjustment for a four-phase DQS internal clock. The four phases of the DQS internal clock may include: ICLK (0°), QCLK (90°), IBCLK (180°) and QBCLK (270°), as described in the DDR5 specification. The duty cycle adjustment for QCLK, IBCLK and QBCLK can be as follows: Figure 1 As shown in the figure, since the rising edge is adjusted, an increase in the DCA code corresponds to a delay in the rising edge (correspondingly, a decrease in the duty cycle), while a decrease in the DCA code corresponds to an advance in the rising edge (correspondingly, an increase in the duty cycle). Furthermore, for some applications, the duty cycles of QCLK (90°), IBCLK (180°), and QBCLK (270°) are generally adjusted, while ICLK (0°) can remain unchanged.

[0039] If combined Figure 2 As shown, the duty cycle adjustment steps -7 to +7 can be specified by mode registers MR43 and MR44, respectively. For example, for QCLK duty cycle adjustment, MR43 OP[2:0] can be used to specify the duty cycle adjustment step, and OP[3] can be used to specify the positive or negative sign of the step. For IBCLK duty cycle adjustment, MR43 OP[6:4] can be used to specify the duty cycle adjustment step, and MR43 OP[7] can be used to specify the positive or negative sign of the step. For QBCLK duty cycle adjustment, MR44 OP[2:0] can be used to specify the duty cycle adjustment step, and MR44 OP[3] can be used to specify the positive or negative sign of the step. Generally speaking, the circuit design follows the JEDEC specification requirements.

[0040] DQS duty cycle adjustment can be located before the DQS clock tree or equivalent. Duty cycle adjustment requires a locked DLL state and will affect the DQS and DQ duty cycle in the following operations:

[0041] a) read;

[0042] b) Read the preamble training;

[0043] c) Read the training pattern;

[0044] d) Mode register read.

[0045] In the scenario where the DQS clock tree uses a four-phase clock, the odd and even duty cycles of all DQS of each device can be adjusted accordingly because the internal four-phase clocks can be independently controlled by the DCA code.

[0046] Reference again Figure 2 , for DDR5's four-phase DQS, adjust the rising edge of the pulse signal. In the duty cycle adjustment of QCLK, IBCLK, and QBCLK, there can be 7 steps for positive and negative adjustment respectively. Therefore, a total of 14 steps can be included. In the present invention, the delay of each step can be approximately 2ps-4ps. Therefore, the total duty cycle adjustment range of the 14 steps can be approximately 28ps-56ps.

[0047] Figure 3a This circuit design uses a duty cycle adjustment circuit and its timing diagram to increase the duty cycle of a signal. This circuit design uses a NOR gate (NOR) 312 to widen the high-level portion of a pulse signal. The first input pin of NOR gate 312 can receive an input pulse, while the second input pin can be a specific pulse with a greater delay than the input pulse received at the first input pin. The difference between the input pulse and the output pulse of this circuit can be equal to the delay.

[0048] In a further embodiment, in addition to NOR gate 312, Figure 3a The circuit may further include a delay component 310 for widening the high level of the pulse. The delay component 310 may use any delay component available in the art. In a non-limiting embodiment, the present invention may use a capacitor as the delay component 310. Figure 3a The circuit may further include several inverters 302-308. The number of inverters may be Figure 3a The four in the figure can also be used in other numbers according to the specific situation. The present invention does not limit this. However, generally, an even number of inverters is required on each input line of the logic gate. Figure 3a As shown, an inverter 314 is generally required after the NOR gate 312 and before the output to make the input and output in phase.

[0049] Figure 3b This is a duty cycle adjustment circuit and its timing diagram for reducing the duty cycle of a signal. This circuit design uses a NAND gate (NAND) 342 to shorten the high-level portion of a pulse signal. Similarly, the first input pin of NAND gate 342 can be used to receive an input pulse, and the second input pin can be a specific pulse with a narrower high-level portion than the input pulse received by the first input pin. The shortened high-level portion of the output pulse signal represents the delay caused by the specific pulse.

[0050] Similarly, in addition to the NAND gate 342, Figure 3b The circuit may further include a delay component 340 for shortening the high level portion of the pulse. The delay component 340 may use any delay component available in the art. In a non-limiting embodiment, the present invention may use a capacitor as the delay component 340. Figure 3b The circuit may further include several inverters 332-338. The number of inverters may be Figure 3b The four in the figure can also be used in other numbers according to the specific situation. The present invention does not limit this. However, generally, an even number of inverters is required on each input line of the logic gate. Figure 3b As shown, an inverter 344 is generally required after the NAND gate 342 and before the output to make the input and output in phase.

[0051] Figure 4a The present invention is a circuit for pre-adjusting the duty cycle (PRE_DCA) and its timing diagram. The present invention is configured to widen the circuit of the high level portion of the input signal (for example, Figure 3a The circuit is used as a duty cycle pre-adjustment (PRE_DCA) circuit and is set in the DLL circuit. Figure 4a Zhongyu Figure 3a The same parts will not be repeated here.

[0052] The high level part of the pulse signal can be widened by Figure 3a As shown, the timing of the falling edge of the pulse signal is delayed. As described above, the present invention can use an NOR gate to achieve the widening of the high-level part of the pulse signal. A delay component can be added to one of the inputs of the NOR gate (for example, between the two inverters 406 and 408). In a preferred embodiment, the delay component can be 14 parallel delay units that can be used to implement the 14 steps described above. Each delay unit can be in one of two states (for example, state "1" or state "0") under the control of a control signal, so that 14 steps of duty cycle adjustment can be achieved by combining different states of 14 delay units, as shown below in combination Figure 7 More detailed description. The first state of each delay unit (e.g., state "1") can indicate that a delay is generated, and the second state (e.g., state "0") can indicate that no delay is generated. As an example and not a limitation, an equal number of delay components can be added to another input (e.g., between the two inverters 402 and 404), but these delay components can all be set to state "0" so that no delay is applied to the signal on the line. As shown below in combination Figures 5a-5c As mentioned above, in one embodiment of the present invention, each delay unit can utilize a capacitor as a delay unit.

[0053] In a further preferred embodiment of the present invention, the PRE_DCA circuit of the present invention can be configured to use 7 steps for widening the high level portion of the pulse as a default setting. Figure 4a As shown, 7 delay units are set to the "1" state to widen the high-level portion of the pulse signal, while the remaining 7 delay units are set to the "0" state. Since this is the default setting, the state of each delay unit can be fixed separately without further adjustment. The above default setting is a preferred embodiment of the present invention. The present invention can also set another number of delay units to the "1" state and the remaining ones to the "0" state.

[0054] Figure 4b The duty cycle regulator of the present invention may further include: Figure 4b The DCA circuit shown. The DCA circuit can be coupled to the above-mentioned PRE_DCA circuit. The DCA circuit can be configured to receive a signal from the PRE_DCA circuit. The DCA circuit can be configured to further adjust the duty cycle of the signal output from the PRE_DCA circuit. Specifically, the DCA circuit can be configured to adjust the rising edge of the signal output from the PRE_DCA circuit. Adjusting the rising edge can include at least one of advancing the falling edge (negative delay), delaying it (positive delay), or keeping it unchanged. The DCA circuit can be configured to perform corresponding duty cycle adjustment operations after the DLL circuit is locked. Similarly, Figure 4b Zhongyu Figure 3b The same parts will not be repeated here.

[0055] As described above, the present invention can shorten the high level portion of the pulse signal with the help of a NAND gate. A delay component can be added to one of the inputs of the NAND gate (for example, between the two inverters 436 and 438). In a preferred embodiment, the delay component can be 14 parallel delay units that can be used to implement the 14 steps described above. Each delay unit can be in one of two states (for example, state "1" or state "0") under the control of a control signal, so that 14 steps can be implemented by combining different states of the 14 delay units, as shown below. Figure 7 The first state of each delay unit (e.g., state "1") may indicate that a delay is generated, and the second state (e.g., state "0") may indicate that no delay is generated. Similarly, as an example and not a limitation, an equal number of delay units may be added to another input (e.g., between the two inverters 432 and 434), but these delay units may all be set to state "0" so that no delay is applied to the signal on the line. As shown below in combination with Figures 5a-5cAs mentioned above, in one embodiment of the present invention, each delay unit can utilize a capacitor as a delay unit.

[0056] like Figure 4b The DCA circuit is shown in FIG. Figure 4b The illustrated DCA circuit can be a first DCA circuit for the first phase ICLK of the four-phase DQS internal clock signal. The default state of the first DCA circuit can be set to shorten the high-level portion of the signal output from the corresponding first PRE_DCA circuit. More specifically, the default state of the DCA circuit can be set to shorten the high-level portion of the signal output from the first PRE_DCA circuit by seven steps (i.e., seven of the 14 delay cells are set to the "1" state) to compensate for the seven steps used for widening in the PRE_DCA circuit. The seven steps used for shortening include setting seven of the 14 delay cells to the "1" state. The above default setting is a preferred embodiment of the present invention. The present invention can also set another number of delay elements to the "1" state, while the remaining delay elements are in the "0" state. This setting corresponds to the setting of the delay elements of the PRE_DCA circuit, so that the first DCA circuit can compensate for duty cycle adjustment.

[0057] like Figure 4b The DCA circuits shown may be second, third, and fourth DCA circuits for the second, third, and fourth phases of the DQS internal clock four-phase signal, respectively. As a preferred embodiment, the default setting of each of the second, third, and fourth DCA circuits may be a shortened 7-step ( Figure 4b The 7 steps for shortening include setting 7 of the 14 delay cells to state "1". This default setting can then be used as the starting point for adjustment, and the maximum forward step (7 steps) can be further achieved by setting the delay. Figure 4b = +7) and a maximum of 7 steps in the negative direction ( Figure 4b Step = -7), such as Figure 4b As shown in . Positive adjustment can further shorten the high level, and negative adjustment can widen the high level (for example, relative to CLK, as Figure 4b The corresponding relationship between the steps used for duty cycle adjustment and the combination states of the 14 delay units can be found in Figure 7 Note that the states of the 14 delay units here are independently controllable, for example, by adjusting them to be in state "1" or state "0" through the switches shown.

[0058] In other words, if Figure 4bThe DCA circuit shown can be a first DCA circuit for the first phase ICLK of a four-phase signal, or a second, third, or fourth DCA circuit for the second, third, and fourth phases QCLK, IBCLK, and QBCLK of a four-phase signal. The difference is that the steps of the first DCA circuit can be fixed, for example, fixedly set to shorten the high-level portion of the signal output from the PRE_DCA circuit by 7 steps (i.e., 7 of the 14 delay cells are set to state "1") without further adjustment. Therefore, for the first DCA circuit, the state of each delay cell can be fixed separately without adjustment. For the second to fourth DCA circuits, as described above, further adjustment may be required for the second, third, and fourth phase signals, so the respective 14 delay cells can be adjusted separately to further adjust the duty cycle.

[0059] Since the present invention sets the PRE_DCA circuit and the DCA circuit in the loop of the DLL circuit, Figure 4b As shown in the timing diagram, after the falling edge of each signal is delayed by the corresponding PRE_DCA circuit and the rising edge is delayed by the corresponding first DCA circuit, the rising edge of ICLK can be realigned to the rising edge of the clock signal CLK in the DLL circuit after the DLL is locked. In addition, if the falling edge of ICLK is delayed by the first PRE_DCA circuit and the rising edge is delayed by the same amount by the first DCA circuit, ICLK remains unchanged compared to the initial state (consistent with CLK, that is, both the rising edge and the falling edge are aligned with CLK). ICLK will not affect the tDQSCK timing. If the PRE_DCA circuit and the DCA circuit are not set in the DLL circuit, although the duty cycle of ICLK is the same as that of CLK, the overall delay will be, for example, 7 steps (such as Figure 4b This can affect the tDQSCK timing.

[0060] Due to the fixed phase relationship between ICLK and QCLK, IBCLK and QBCLK, after ICLK is aligned with CLK, the rising edges of QCLK, IBCLK and QBCLK are shifted by the same amount as ICLK.

[0061] After the DLL is locked, the second, third, and fourth DCAs can further change the duty cycle of the signal received from the corresponding PRE_DCA according to the received control signal. Specifically, the second, third, and fourth DCAs can change the duty cycle of the signal by adjusting the rising edge of the signal received from the corresponding PRE_DCA, where adjusting the rising edge can include one or more of delaying the rising edge, advancing the rising edge, or not changing the rising edge, as shown in the following combination: Figure 6a-6bDescribed in more detail.

[0062] Figures 5a-5c is an example of a delay component for duty cycle adjustment. As an example and not limitation, the delay component may include, for example, a plurality of capacitors disposed between the two inverters 502 and 504 as delay components, each capacitor being a delay unit. As an example, each delay unit may be a NOR (not-or gate), and each NOR may be specifically implemented as Figure 5b or Figure 5c It should be understood that this document describes the NOR gate as an example, however, the delay component may also include a NAND gate or other devices.

[0063] exist Figure 5b or Figure 5c Each capacitor may include, for example, 2 PMOS and 2 NMOS. The gate capacitance of the capacitor may be changed by the control signal of the control bit, thereby realizing the function of controlling the enabling or disabling of each delay unit. The load terminal is connected to Figure 5a When the control bit gives a high level (H) or low level (L) signal (e.g., corresponding to states "1" and "0", respectively), the source voltage will change (e.g., generate Figure 5b and Figure 5c The voltages "H" and "L" indicated in the figure will cause the load capacitance to change, and according to the formula τ = RC, the delay time will change accordingly. This capacitance change is small enough to achieve an adjustment step size as small as about 2ps. However, it should be understood that the same Figures 5a-5c Different delay components are used to delay the signal. Figures 5a-5c The embodiment is only one way to implement delaying a signal.

[0064] Figure 6a-6b 1 is a schematic diagram of a DLL (delay locked loop) circuit including each PRE_DCA circuit and each DCA circuit, and a timing diagram of the output signals of the PRE_DCA circuit and the DCA circuit. Figure 6aAs shown, in addition to the aforementioned PRE_DCA circuit and DCA circuit, the DLL circuit may further include other circuits, such as one or more of the following: a phase detector 602, configured to detect whether the phase of the clock signal CLK is consistent with the phase of the DLL output signal; a DLL control 604, configured to output a control signal to control voltage regulation (U voltage is increased, D voltage is decreased) based on a comparison result of the phase detector; a charge pump 606, configured to output a voltage control signal (VCTRL) based on the control signal output by the DLL control; a voltage-controlled delay line (VCDL) 608, configured to perform voltage control based on the voltage control signal; a MIMIC circuit 610, configured to simulate circuit components between CLK and DCA_OUT to simulate the effects of various factors in the DLL circuit on the input CLK clock signal, particularly the effect of the duty cycle; and a frequency divider 612, configured to divide the signal from the MIMIC 610 into four phase signals, such as ICLK (0°), QCLK (90°), IBCLK (180°), and QBCLK (270°). The frequency divider 612 can be coupled to each PRE_DCA circuit 614-1, 614-2, 614-3, and 614-4. For example, each PRE_DCA circuit can be arranged after the frequency divider 612 to receive the signal from the frequency divider 612. Each PRE_DCA circuit 614-1, 614-2, 614-3, and 614-4 can be further coupled to a corresponding DCA circuit 616-1, 616-2, 616-3, and 616-4, respectively. The working principles of the PRE_DCA circuit and the DCA circuit are as described above and will not be repeated here. Figure 6a The circuit diagram shown not only allows the signal output by ICLK to be consistent with CLK, but also allows the duty cycles of QCLK, IBCLK, and QBCLK to be independently adjusted according to circumstances or needs.

[0065] By setting the PRE_DCA and DCA circuits in the DLL circuit, the DLL circuit can be locked after ( Figure 6b The dotted box part) aligns the rising edge of ICLK with the rising edge of the clock signal (CLK), and if the widening and shortening adjustment widths of ICLK in PRE_DCA and DCA are consistent, the aligned ICLK and CLK are completely consistent (the rising and falling edges of the two are aligned). In addition, the duty cycle adjustment of QCLK, IBCLK and QBCLK can also be done after the DLL circuit is locked ( Figure 6b Based on DDR5, the adjustment can be made on the rising edge. For example, Figure 6bThe default state for the rising edge shown in FIG (step = 0, 7 units in 14 adjustment units are valid), and the default setting is used as the adjustment starting point, and the maximum positive step ( Figure 6b = +7 steps in the negative direction, the high level part is shortened) and a maximum of 7 steps in the negative direction ( Figure 6b = -7 in the step, the high level part is widened). Figure 6b As shown in , positive regulation can achieve further shortening, and negative regulation can achieve widening (for example, relative to CLK, as shown in Figure 6b The corresponding relationship between the steps used for duty cycle adjustment and the combination states of the 14 delay units can be found in Figure 7 Note that the states of the 14 delay units are independently controlled, for example, by adjusting them to be in state "1" or state "0" through the switches shown.

[0066] Figure 7 1 is a DCA circuit and timing diagram thereof according to an embodiment of the present disclosure. One input line of a NAND gate has 14 delay cells (e.g., loading capacitors) S1-S14, which are used for duty cycle adjustment steps -7 to +7. Each of these 14 delay cells has a switch that can be switched between states "1" and "0" under the control of a control signal. Thus, the combination of the states of the 14 delay cells can delay the input signal within a range of steps -7 to +7. As described above, the default setting of the DCA circuit (step = 0, as shown in the dashed box) is that 7 delay cells are active (state "1") to compensate for the widened 7 steps implemented in the PRE_DCA circuit. Steps +1 to +7 correspond to 8 to 14 of the 14 delay cells being set to state "1," and steps -1 to -7 correspond to 6 to 0 of the 14 delay cells being set to state "1." Step -7 means that all 14 delay units are invalid, which can be used to widen the step by 7 steps relative to the high level part of the CLK signal; while step +7 means that all 14 delay units are valid, which can be used to shorten the step by 7 steps relative to the high level part of the CLK signal.

[0067] As described herein, for ease of understanding, this specification is mainly described with reference to DDR5 as an example. However, the present invention is not limited to application in DDR5, but can be used in any use scenario where duty cycle adjustment is required. In particular, the technology of the present application is more beneficial when the falling edge needs to be adjusted while the rising edge remains unchanged. In other application scenarios, the corresponding parameters may change, for example, the step may be a number of steps other than 14 steps from -7 to +7, and the number of phases may not be limited to four phases. Other parameters may also change and are not limited to the specific forms described in this article, and are not listed here one by one.

[0068] The basic concepts of the present invention have been described above. It will be apparent to those skilled in the art that the above disclosure is merely illustrative and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are suggested in the present application, and such modifications, improvements, and amendments remain within the spirit and scope of the embodiments of the present application.

Claims

1. A duty cycle regulator, comprising: N number of duty cycle pre-adjustment PRE_DCA circuits, each PRE_DCA circuit is provided in parallel in the delay locked loop (DLL) circuit and is configured to widen a high level portion of a corresponding phase of the N-phase input signal; as well as A number M of duty cycle adjustment DCA circuits are provided, each DCA circuit is arranged in parallel in the DLL circuit and coupled to a corresponding PRE_DCA circuit, and each DCA circuit is configured to: receiving a signal from a corresponding PRE_DCA circuit, and further adjusting the duty cycle of the signal output from the corresponding PRE_DCA circuit; Wherein, each PRE_DCA circuit includes an inverter, a delay component, and an NOR gate, wherein in each PRE_DCA circuit: the first input of the NOR gate is the corresponding phase of the original input pulse, and the second input is the corresponding phase of the original input pulse passing through the delay component of the PRE_DCA circuit; and wherein each DCA circuit includes an inverter, a delay component, and an NAND gate, wherein in each DCA circuit: the first input of the NAND gate is the input pulse from the corresponding PRE_DCA circuit, and the second input is the input pulse from the corresponding PRE_DCA circuit and passing through the delay component of the DCA circuit.

2. The duty cycle regulator according to claim 1, wherein: The input signal is a pulse signal, wherein each PRE_DCA circuit is configured to widen the high level portion of the corresponding phase of the N-phase input signal including: delaying the falling edge of the corresponding phase of the N-phase pulse signal by a first amount as a default state; Each DCA circuit is configured to adjust the duty cycle of the signal output from the corresponding PRE_DCA circuit, including: delaying the rising edge of the signal output from the corresponding PRE_DCA circuit by a second amount to shorten the high level portion of the signal; The default setting of each DCA circuit is to make the second amount equal to the first amount, so as to compensate for the widening of the signal by the PRE_DCA circuit.

3. The duty cycle regulator according to claim 2, wherein: The DCA circuit includes a first DCA circuit for a first phase of an N-phase input signal, wherein After locking, the DLL circuit realigns the rising edge of the first signal output from the first DCA circuit with the rising edge of the clock signal of the DLL circuit, and at this time, the falling edge of the signal output from the first DCA circuit is also realigned with the falling edge of the clock signal of the DLL circuit; and Respective phases of the signals output from the second to Mth DCA circuits are respectively shifted by the same amount as the first signal based on a fixed phase relationship with the first phase.

4. The duty cycle regulator according to claim 3, wherein: Each of the second to Mth DCA circuits is further configured to, after the DLL is locked, further change a duty cycle of a signal received from a corresponding PRE_DCA according to a received control signal.

5. The duty cycle regulator according to claim 4, wherein: Each DCA in the second to Mth DCA circuits can be configured to change a duty cycle of a signal by adjusting a rising edge of a signal received from a corresponding PRE_DCA, wherein adjusting the rising edge includes one or more of delaying the rising edge, advancing the rising edge, or not changing the rising edge.

6. The duty cycle regulator according to claim 4, wherein: Each DCA circuit can independently adjust the duty cycle of the signal received from the corresponding PRE_DCA circuit according to the respective received control signal.

7. The duty cycle regulator according to claim 1, wherein: N equals M.

8. The duty cycle regulator according to claim 1, wherein: The duty cycle regulator includes a duty cycle regulator for the DDR5 four-phase bidirectional data control pin DQS internal clock, and N and M are 4.

9. The duty cycle regulator according to claim 8, wherein: The delay component of each PRE_DCA circuit includes 14 delay units. Each PRE_DCA circuit is configured to widen the high-level portion of the input signal by a fixed 7 steps at the falling edge by enabling 7 delay units among the 14 delay units as a default setting.

10. The duty cycle regulator according to claim 9, wherein: The duty cycle adjuster is configured to specify duty cycle adjustment of a corresponding DCA circuit using a corresponding mode register, wherein: Use the mode register MR43 OP[2:0] to specify the step of the second DCA to adjust the duty cycle of the second phase, and use MR43 OP[3] to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7; Use the mode register MR43 OP[6:4] to specify the step of the third DCA to adjust the duty cycle of the third phase, and use MR43 OP[7] to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7; Use the mode register MR44 OP[2:0] to specify the step of the fourth DCA to adjust the duty cycle of the fourth phase, and use MR44 OP[3] to specify the positive or negative sign of the step, and the step includes 14 steps from -7 to +7, and The delay components of each PRE_DCA circuit and each DCA circuit include 14 delay units connected in parallel and whose states are independently adjustable. The 14 steps are realized by utilizing different state combinations of the 14 delay units connected in parallel, wherein The state of each delay unit includes "1" or "0". The state "1" of each delay unit indicates a valid state in which delay is generated, and the state "0" indicates an invalid state in which no delay is generated.

11. The duty cycle regulator according to claim 10, wherein: Each DCA circuit is configured to adjust the high-level portion of the corresponding phase of the signal output from the PRE_DCA circuit, including: performing 7 steps for shortening the high level of the corresponding phase output from the corresponding PRE_DCA circuit as a default setting to compensate for the 7 steps for widening in the PRE_DCA circuit, wherein the default setting includes setting 7 delay elements among the 14 DCA circuits to state 1, so that the rising edge of the corresponding phase output from the corresponding DCA circuit is delayed by 7 steps.

12. The duty cycle regulator according to claim 11, wherein: The default setting of each of the second DCA, the third DCA, and the fourth DCA corresponds to a state of "step=0", and Each of the second DCA, the third DCA and the fourth DCA can be configured to change the duty cycle of the signal by adjusting the rising edge of the signal received from the corresponding PRE_DCA by -7 to +7 steps, wherein steps +1 to +7 correspond to 8 to 14 of the 14 delay cells being set to state 1, and steps -1 to -7 correspond to 6 to 0 of the 14 delay cells being set to state 1, respectively.

13. The duty cycle regulator according to claim 11, wherein: The delay unit is a capacitor, and the capacitor is a NAND gate or a NOR gate, including two PMOS and two NMOS.

14. The duty cycle regulator according to claim 13, wherein: The adjustment range of each step is 2ps-4ps, and the total adjustment range of 14 steps is 28ps-56ps.

15. The duty cycle regulator according to claim 1, wherein: The DLL circuit includes a frequency divider configured to divide a four-phase input signal into a first phase, a second phase, a third phase, and a fourth phase having a phase difference of π / 2 between adjacent phases.

16. A delay phase-locked loop (DLL) circuit, comprising the duty cycle regulator according to any one of claims 1 to 15.

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