Method for Measuring Static Noise Margin of Static Random Access Memory

Abstract

The present invention provides a method for measuring the static noise margin of a static random access memory. A static random access memory circuit is provided and the first and second measurement points therein are selected. Using the voltage values of the first and second measurement points as the abscissa and ordinate respectively, within the first measurement interval, the voltage values of the first and second measurement points are changed respectively, and the voltage values of the corresponding other measurement point are measured respectively, obtaining the symmetric first and second voltage curves. The coordinates at the fastest change rate of the slopes of the first and second voltage curves are obtained, and according to the coordinates, a second measurement interval smaller than the first measurement interval is set. Then, within the second measurement interval, the voltage values of the first and second measurement points are changed respectively, and the voltage values of the corresponding other measurement point are measured respectively, obtaining the symmetric third and fourth voltage curves. The measurement method of the present invention can shorten the measurement time and improve the measurement accuracy at the same time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for measuring the static noise margin of a static random access memory. Background Art

[0002] In the development process of semiconductor manufacturing technology, static random access memories have become an indispensable and important part due to their wide applications. The main process technologies for fabricating CMOS static random access memories can be directly extended to the production of other types of circuits. Therefore, static random access memories are frequently used as important indicators for process verification in the integrated circuit manufacturing process.

[0003] For static random access memories, their static noise margin is one of the most important performance indicators. The static noise margin is the minimum DC noise voltage that causes the state of the storage cell to flip, which determines the stability of the storage cell and the reliability of the static random access memory.

[0004] For existing static noise margin measurement methods, if high measurement accuracy is to be obtained, a large amount of test time is required.

[0005] Taking a 6T static random access memory as an example, the existing static noise margin measurement method is through:

[0006] 1. Vary the voltage at the Q point (such as Figure 1 ), and measure the voltage at the Q(—) point (such as Figure 1 );

[0007] 2. Vary the voltage at the Q(—) point (such as Figure 1 ), and measure the voltage at the Q point (such as Figure 1 );

[0008] 3. Place the two voltage-varying curves in the same coordinate system to obtain a set of butterfly curves (such as Figure 2 );

[0009] 4. Rotate the butterfly curve by 45 degrees to obtain the distance of the extreme point of the butterfly curve in the Y direction. Taking this distance as the diagonal of a square, the side length of the square is the static noise margin of the basic unit of this static random access memory (such as Figure 3 ).

[0010] For the existing test method, if high measurement accuracy is to be achieved, when measuring the voltages in steps 1 and 2, if the change amount of the input voltage is reduced and the measurement point density is increased, the measurement time will be too long. We can only make a trade-off and balance between accuracy and speed.

[0011] To solve the above problems, a new method for measuring the static noise margin of a static random access memory is needed. Summary of the Invention

[0012] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for measuring the static noise margin of a static random access memory, which is used to solve the problem in the prior art that if a higher measurement accuracy is to be obtained, when reducing the change amount of the input voltage and increasing the measurement point density, the measurement time will be too long.

[0013] To achieve the above purpose and other related purposes, the present invention provides a method for measuring the static noise margin of a static random access memory, including:

[0014] Step 1: Provide a static random access memory circuit and select the first and second measurement points therein;

[0015] Step 2: Respectively use the voltage values of the first and second measurement points as the abscissa and ordinate, change the voltage values of the first and second measurement points respectively within the first measurement interval, measure the voltage values of the corresponding other measurement points respectively, obtain multiple sets of first and second measurement data corresponding to the first and second measurement points, and then obtain symmetric first and second voltage curves according to the first and second measurement data;

[0016] Step 3: Obtain the coordinates of the point where the slope change rate of the first and second voltage curves is the fastest, set a second measurement interval smaller than the first measurement interval according to the coordinates, then change the voltage values of the first and second measurement points respectively within the second measurement interval, measure the voltage values of the corresponding other measurement points respectively, obtain multiple sets of third and fourth measurement data corresponding to the first and second measurement points, and then obtain symmetric third and fourth voltage curves according to the first to fourth measurement data;

[0017] Step 4: Rotate the third and fourth voltage curves counterclockwise by 45 degrees around the coordinate origin, and define the distance of the maximum value point in the Y-axis direction of the third and fourth voltage curves after rotation relative to the other voltage curve as the static noise margin.

[0018] Preferably, the static memory circuit in Step 1 is a 6-transistor static random access memory circuit.

[0019] Preferably, the static memory circuit in step one includes: the static memory circuit in step one includes: a first NMOS, a first PMOS, a second NMOS, a second PMOS, a third NMOS, and a fourth NMOS; wherein, the drain of the first PMOS is connected to the drain of the first NMOS, the gates of the first NMOS and the first PMOS are connected, the drain of the second NMOS is connected to the drain of the second PMOS, the gates of the second NMOS and the second PMOS are connected, the sources of the first PMOS and the second PMOS are both connected to the power supply voltage, the sources of the first NMOS and the second NMOS are both grounded, the gate of the third NMOS is connected to the word line, one end of the third NMOS is connected to the second bit line, and the other end of the third NMOS is respectively connected to the drains of the first NMOS and the first PMOS and the gates of the second NMOS and the second PMOS, the gate of the fourth NMOS is connected to the word line, one end of the fourth NMOS is connected to the first bit line, and the other end of the fourth NMOS is respectively connected to the drains of the second NMOS and the second PMOS and the gates of the first NMOS and the first PMOS.

[0020] Preferably, the second bit line in step one is at a high potential, and the first bit line is at a high potential.

[0021] Preferably, the source of the third NMOS in step one is connected to the second bit line, the drain of the third NMOS is respectively connected to the drains of the first NMOS and the first PMOS and the gates of the second NMOS and the second PMOS, the source of the fourth NMOS is connected to the first bit line, and the drain of the fourth NMOS is respectively connected to the drains of the second NMOS and the second PMOS and the gates of the first NMOS and the first PMOS.

[0022] Preferably, the position of the second measurement point in step one is the connection point of the drain of the third NMOS and the drains of the first NMOS and the first PMOS; the position of the first measurement point is the connection point of the drain of the fourth NMOS and the drains of the second NMOS and the second PMOS.

[0023] Preferably, the first measurement interval in step two is from 0V to the operating voltage of the device.

[0024] Preferably, the first measurement interval in step two is from 0V to 0.9V.

[0025] Preferably, the measurement accuracy of the first measurement interval in step two is 0.1V.

[0026] Preferably, the range of the second measurement interval in step three is from (X1 - 0.1V) to (X1 - 0.05V), (X1 + 0.05V) to (X1 + 0.1V), where X1 is the voltage value of the first measurement point corresponding to the abscissa.

[0027] Preferably, in step three, the measurement accuracy in the second measurement interval is 0.05V.

[0028] In step three, the range of the second measurement interval is from (X1 - 0.1V) to (X1 - 0.05V), (X1 + 0.05V) to (X1 + 0.1V), where X1 is the voltage value of the first measurement point corresponding to the abscissa.

[0029] Preferably, in step three, the measurement accuracy in the second measurement interval is 0.01V.

[0030] Preferably, in step three, the measurement accuracy in the second measurement interval is 0.1V.

[0031] As described above, the method for measuring the static noise margin of a static random access memory of the present invention has the following beneficial effects: The present invention first roughly measures a voltage change curve in the butterfly curve to obtain the range of extreme points, then estimates the range of extreme points of the other voltage change curve using the symmetry of the butterfly curve, and then performs refined measurement on the determined range. Such a measurement method can shorten the measurement time and improve the measurement accuracy at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of a 6-transistor static random access memory circuit shown as prior art;

[0033] Figure 2 Schematic diagram of the measured butterfly curve of a static random access memory shown as prior art;

[0034] Figure 3 Schematic diagram of the measured butterfly curve of a static random access memory rotated by -45 degrees shown as prior art;

[0035] Figure 4 Schematic diagram of the butterfly curve of a static random access memory obtained by rough measurement of the present invention;

[0036] Figure 5 Schematic diagram of the butterfly curve of a static random access memory obtained by refined measurement of the present invention;

[0037] Figure 6 Schematic diagram of the butterfly curve of a static random access memory obtained by refined measurement of the present invention rotated by -45 degrees;

[0038] Figure 7 Schematic diagram of the measurement method of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please refer to Figure 7 , the present invention provides a method for measuring the static noise margin of a static random access memory, including:

[0041] Step 1, please refer to Figure 1 , provide a static random access memory circuit and select the first measurement point Q point and the second measurement point Q(—) point therein;

[0042] In an embodiment of the present invention, the static memory circuit in Step 1 is a 6-transistor static random access memory circuit.

[0043] In an embodiment of the present invention, the static memory circuit in Step 1 includes: a first NMOS M1, a first PMOS M2, a second NMOS M3, a second PMOS M4, a third NMOS M5, and a fourth NMOS M6; wherein, the drain of the first PMOS M2 is connected to the drain of the first NMOS M1, the gates of the first NMOS M1 and the first PMOS M2 are connected, the drain of the second NMOS M3 is connected to the drain of the second PMOS M4, the gates of the second NMOS M3 and the second PMOS M4 are connected, the sources of the first PMOS M2 and the second PMOS M4 are both connected to the power supply voltage, the sources of the first NMOS M1 and the second NMOS M3 are both grounded, the gate of the third NMOS M5 is connected to the word line, one end of the third NMOS M5 is connected to the second bit line BLB, and the other end of the third NMOS M5 is respectively connected to the drains of the first NMOS M1, the first PMOS M2, and the gates of the second NMOS M3 and the second PMOS M4, the gate of the fourth NMOS M6 is connected to the word line, one end of the fourth NMOS M6 is connected to the first bit line BL, and the other end of the fourth NMOS M6 is respectively connected to the drains of the second NMOS M3, the second PMOS M4, and the gates of the first NMOS M1 and the first PMOS M2, wherein the first NMOS M1 and the second NMOS M3 are pull-down transistors, the first PMOS M2 and the second PMOS M4 are pull-up transistors, and the third NMOS M5 and the fourth NMOS M6 are transfer transistors.

[0044] In an embodiment of the present invention, the second bit line BLB is at a high potential and the first bit line BL is at a high potential in Step 1.

[0045] In an embodiment of the present invention, in step one, the source of the third NMOS M5 is connected to the second bit line BLB, and the drain of the third NMOS M5 is connected to the drains of the first NMOS M1 and the first PMOS M2, and the gates of the second NMOS M3 and the second PMOS M4. The source of the fourth NMOS M6 is connected to the first bit line BL, and the drain of the fourth NMOS M6 is connected to the drains of the second NMOS M3 and the second PMOS M4, and the gates of the first NMOS M1 and the first PMOS M2, where the first and second ends are the source or the drain, determined by the potentials of the first bit line BL and the second bit line BLB.

[0046] In an embodiment of the present invention, the position of the first measurement point is the connection point of the drain of the third NMOS M5 and the drains of the first NMOS M1 and the first PMOS M2; the position of the second measurement point is the connection point of the drain of the fourth NMOS M6 and the drains of the second NMOS M3 and the second PMOS M4.

[0047] It should be understood that the static random access memory circuit here may also be more complex, and this measurement method can also be applied to static random access memory circuits with more transistors.

[0048] Step two, please refer to Figure 4 , taking the voltage values of the first and second measurement points as the abscissa and ordinate respectively, changing the voltage values of the first and second measurement points within the first measurement interval, and respectively measuring the voltage values of the other measurement points corresponding to the first and second measurement points, obtaining multiple groups of first and second measurement data corresponding to the first and second measurement points, that is, changing the voltage of the first measurement point Q, measuring the voltage of the second measurement point Q(—), and then obtaining the first measurement data; changing the voltage of the second measurement point Q(—), measuring the voltage of the first measurement point Q, and then obtaining the second measurement data, and then obtaining the first and second symmetric voltage curves according to the first and second measurement data. In this step, it is used to roughly measure the butterfly curve of the static random access memory. In an embodiment of the present invention, the first measurement interval in step two is from 0V to the operating voltage of the device.

[0049] In an embodiment of the present invention, the first measurement interval in step two is from 0V to 0.9V.

[0050] In an embodiment of the present invention, the measurement accuracy of the first measurement interval in step two is 0.1V.

[0051] Specifically, according to the existing measurement method, the operating voltage of the device is 0.9V. Starting from 0V, measurements are taken every 0.01V, with a total of 91 measurement points. For the two curves, there are a total of 182 measurement points. According to the measurement method of the embodiment of the present invention, a rough measurement is first performed: the operating voltage of the device is 0.9V, and starting from 0V, measurements are taken every 0.1V for one curve, with a total of 10 measurement points. Coordinate transformation is performed on the measurement data to obtain the data of the other curve.

[0052] Step three, please refer to Figure 5 , obtain the coordinates at the points where the slope change rates of the first and second voltage curves are the fastest. Set a second measurement interval smaller than the first measurement interval according to the coordinates. Then, within the second measurement interval, change the voltage values of the first and second measurement points respectively, and measure the voltage values corresponding to another measurement point for the first and second measurement points respectively, to obtain a plurality of third and fourth measurement data corresponding to the first and second measurement points, that is, change the voltage of the first measurement point Q, measure the voltage of the second measurement point Q(—), and thus obtain the third measurement data; change the voltage of the second measurement point Q(—), measure the voltage of the first measurement point Q, and thus obtain the fourth measurement data. Then, obtain the relatively symmetric third and fourth voltage curves according to the first to fourth measurement data. In this step, by taking the coordinates at the points where the slope change rate of the butterfly curve is the fastest, slightly change the input voltage near these coordinates, and re-measure the voltage change curve to obtain a set of more refined and accurate butterfly curves;

[0053] In the embodiment of the present invention, the range of the second measurement interval in step three is from (X1 - 0.1V) to (X1 - 0.05V), (X1 + 0.05V) to (X1 + 0.1V), where X1 is the voltage value of the first measurement point corresponding to the abscissa.

[0054] In the embodiment of the present invention, the measurement accuracy in the second measurement interval in step three is 0.05V.

[0055] The range of the second measurement interval in step three is from (X1 - 0.1V) to (X1 - 0.05V), (X1 + 0.05V) to (X1 + 0.1V), where X1 is the voltage value of the first measurement point corresponding to the abscissa.

[0056] In the embodiment of the present invention, the measurement accuracy in the second measurement interval in step three is 0.01V.

[0057] In the embodiment of the present invention, the measurement accuracy in the second measurement interval in step three is 0.1V.

[0058] Specifically, measurements are taken at intervals of 0.005V within the range of (X1 - 0.1V) to (X1 - 0.05V), for a total of 42 measurement points. Measurements are taken at intervals of 0.01V within the ranges of (X1 - 0.1V) to (X1 - 0.05V) and (X1 + 0.05V) to (X1 + 0.1V), for a total of 20 measurement points. In other regions, measurements are taken at intervals of 0.1V, for a total of 5 measurement points. There are a total of 67 measurement points, and a total of 134 measurement points for the two curves;

[0059] The total number of measurements for the rough measurement and the fine measurement is 144 measurement points;

[0060] The number of measurement points is reduced from 182 to 144, shortening the measurement time;

[0061] The measurement accuracy of the key area is increased from 0.01V to 0.005V, improving the measurement accuracy.

[0062] Step four, please refer to Figure 6 , rotate the third and fourth voltage curves counterclockwise by 45 degrees around the origin of coordinates, and define the distance of the maximum point in the Y-axis direction of the rotated third and fourth voltage curves relative to the other voltage curve as the static noise margin.

[0063] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, numbers, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0064] In summary, the present invention first performs a rough measurement on one of the voltage change curves in the butterfly curve to obtain the range of the extreme points, then estimates the range of the extreme points of the other voltage change curve using the symmetry of the butterfly curve, and then performs a refined measurement on the determined range. Such a measurement method can shorten the measurement time and improve the measurement accuracy at the same time. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0065] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for measuring the static noise margin of a static random access memory, characterized in that, At least including: Step 1: Provide a static random access memory (SRAM) circuit and select the first and second measurement points therein; Step 2: Respectively use the voltage values of the first and second measurement points as the abscissa and ordinate, change the voltage values of the first and second measurement points within the first measurement interval, respectively measure the voltage values of the corresponding other measurement point, obtain multiple sets of first and second measurement data corresponding to the first and second measurement points, and then obtain symmetric first and second voltage curves according to the first and second measurement data; Step 3: Obtain the coordinates of the points where the slopes of the first and second voltage curves change most rapidly, set a second measurement interval smaller than the first measurement interval according to the coordinates, then change the voltage values of the first and second measurement points within the second measurement interval, respectively measure the voltage values of the corresponding other measurement point, obtain multiple sets of third and fourth measurement data corresponding to the first and second measurement points, and then obtain symmetric third and fourth voltage curves according to the first to fourth measurement data; Step 4: Rotate the third and fourth voltage curves counterclockwise by 45 degrees around the origin of coordinates, and define the distance of the maximum value point in the Y-axis direction of the rotated third and fourth voltage curves relative to the other voltage curve as the static noise margin.

2. The method for measuring the static noise margin of a static random access memory according to claim 1, wherein: The static memory circuit in Step 1 is a 6-transistor static random access memory circuit.

3. The method for measuring the static noise margin of a static random access memory according to claim 2, wherein: The static memory circuit in Step 1 includes: a first NMOS, a first PMOS, a second NMOS, a second PMOS, a third NMOS, and a fourth NMOS; wherein, the drain of the first PMOS is connected to the drain of the first NMOS, the gates of the first NMOS and the first PMOS are connected, the drain of the second NMOS is connected to the drain of the second PMOS, the gates of the second NMOS and the second PMOS are connected, the sources of the first PMOS and the second PMOS are both connected to the power supply voltage, the sources of the first NMOS and the second NMOS are both grounded, the gate of the third NMOS is connected to the word line, one end of the third NMOS is connected to the second bit line, and the other end of the third NMOS is respectively connected to the drains of the first NMOS and the first PMOS and the gates of the second NMOS and the second PMOS, the gate of the fourth NMOS is connected to the word line, one end of the fourth NMOS is connected to the first bit line, and the other end of the fourth NMOS is respectively connected to the drains of the second NMOS and the second PMOS and the gates of the first NMOS and the first PMOS.

4. The method for measuring the static noise margin of a static random access memory according to claim 3, wherein: In Step 1, the second bit line is at a high potential, and the first bit line is at a high potential.

5. The method for measuring the static noise margin of a static random access memory according to claim 4, wherein: In Step 1, the source of the third NMOS is connected to the second bit line, the drain of the third NMOS is respectively connected to the drains of the first NMOS and the first PMOS and the gates of the second NMOS and the second PMOS, the source of the fourth NMOS is connected to the first bit line, and the drain of the fourth NMOS is respectively connected to the drains of the second NMOS and the second PMOS and the gates of the first NMOS and the first PMOS.

6. The method for measuring the static noise margin of a static random access memory according to claim 3 or 5, characterized in that: The position of the second measurement point in Step 1 is the connection point of the drain of the third NMOS and the drains of the first NMOS and the first PMOS; the position of the first measurement point is the connection point of the drain of the fourth NMOS and the drains of the second NMOS and the second PMOS.

7. The method for measuring the static noise margin of a static random access memory according to claim 1, wherein: The first measurement interval in Step 2 is from 0V to the operating voltage of the device.

8. The method for measuring the static noise margin of a static random access memory according to claim 7, characterized in that: The first measurement interval in Step 2 is from 0V to 0.9V.

9. The method for measuring the static noise margin of a static random access memory according to claim 8, wherein: The measurement accuracy of the first measurement interval in Step 2 is 0.1V.

10. The method for measuring the static noise margin of a static random access memory according to claim 1, wherein: The range of the second measurement interval in Step 3 is from (X1 - 0.05V) to (X1 + 0.05V), where X1 is the voltage value of the first measurement point corresponding to the abscissa.

11. The method for measuring the static noise margin of a static random access memory according to claim 10, wherein: The measurement accuracy in the second measurement interval in Step 3 is 0.05V.

12. The method for measuring the static noise margin of a static random access memory according to claim 1, wherein: The range of the second measurement interval in Step 3 is from (X1 - 0.1V) to (X1 - 0.05V), (X1 + 0.05V) to (X1 + 0.1V), where X1 is the voltage value of the first measurement point corresponding to the abscissa.

13. The method for measuring the static noise margin of a static random access memory according to claim 12, characterized in that: The measurement accuracy in the second measurement interval in Step 3 is 0.01V.

14. The method for measuring the static noise margin of a static random access memory according to claim 10 or 12, characterized in that: The measurement accuracy in the second measurement interval in Step 3 is 0.01V.

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