A method for manufacturing a memory

Abstract

The application provides a preparation method of a memory, comprising the following steps: providing a substrate, wherein a first oxide layer, a word line material layer, a second oxide layer and a hard mask layer are sequentially stacked on the substrate; etching partial thicknesses of the hard mask layer, the second oxide layer, the word line material layer, the first oxide layer and the substrate to form a trench; forming a metal floating gate material layer in the trench, wherein the metal floating gate material layer covers the inner wall of the trench and extends to cover the hard mask layer; and performing a nitriding treatment on the metal floating gate material layer to repair ion vacancies in the metal floating gate material layer, form a stable metal compound crystal structure, prevent free metal ions from diffusing to affect the continuity of the metal floating gate material layer, and further ensure the continuity of a subsequently formed metal floating gate layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating a memory. Background Technology

[0002] With the development of microelectronics, memory needs to provide higher speeds, lower power consumption, and higher integration. For traditional polysilicon floating gate memories, the thickness of the polysilicon floating gate decreases as the device feature size shrinks. When the number of high-energy incident electrons increases, a large number of high-energy incident electrons will pass through the polysilicon floating gate, causing damage to the substrate, generating more defects, and affecting the reliability of the device. To overcome this problem, a scheme using metal instead of polysilicon as the floating gate has been proposed. However, due to the poor stability of the metal material used in the metal floating gate layer under high temperature and other conditions, the metal floating gate layer is prone to film discontinuity problems during the fabrication and use of the memory, affecting the reliability of the metal floating gate memory. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a memory to solve the problem of poor continuity of existing metal floating gates.

[0004] To achieve the above objectives, the present invention provides a method for fabricating a memory, comprising:

[0005] A substrate is provided on which a first oxide layer, a word line material layer, a second oxide layer and a hard mask layer are formed in sequence.

[0006] Etch a portion of the thickness of the hard mask layer, the second oxide layer, the word line material layer, the first oxide layer, and the substrate to form a trench;

[0007] A metal floating grid material layer is formed in the trench, the metal floating grid material layer covering the inner wall of the trench and extending to cover the hard mask layer;

[0008] The metal floating grid material layer is subjected to nitriding treatment.

[0009] Optionally, after forming the trench and before forming the metal floating grid material layer, the method further includes:

[0010] A barrier material layer is formed within the trench, the barrier material layer covering the inner wall of the trench and extending to cover the hard mask layer;

[0011] The barrier material layer is subjected to an annealing process.

[0012] Optionally, after nitriding the metal floating gate material layer, the process further includes:

[0013] A barrier oxide layer is formed on the metal floating grid material layer, the barrier oxide layer covering the inner wall of the trench and extending to cover the metal floating grid material layer on the hard mask layer;

[0014] Using the barrier oxide layer as a mask, the metal floating gate material layer and the barrier material layer on the hard mask and at the bottom of the trench are removed, and the remaining metal floating gate material layer and the barrier material layer respectively constitute the metal floating gate layer and the barrier layer.

[0015] Remove the remaining barrier oxide layer;

[0016] A source line layer is formed within the trench, and the source line layer at least partially fills the trench.

[0017] After removing the hard mask layer, the second oxide layer, a portion of the word line material layer, and a portion of the first oxide layer, the remaining word line material layer and the first oxide layer constitute the word line layer and the tunnel oxide layer, respectively.

[0018] Optionally, the annealing process includes a spike annealing process or a laser annealing process.

[0019] Optionally, oxygen may be introduced during the annealing process of the barrier material layer.

[0020] Optionally, the oxygen flow rate is less than 5 slm.

[0021] Optionally, the nitriding treatment is a decoupled plasma nitrogen doping process.

[0022] Optionally, the effective power of the decoupled plasma nitrogen-doped process is less than 500W.

[0023] Optionally, the nitriding treatment includes ammonia annealing of the metal floating grid material layer.

[0024] Optionally, the ammonia annealing temperature is 500℃~1100℃.

[0025] This invention provides a method for fabricating a memory, comprising: providing a substrate on which a first oxide layer, a word line material layer, a second oxide layer, and a hard mask layer are formed in sequence; etching a portion of the thickness of the hard mask layer, the second oxide layer, the word line material layer, the first oxide layer, and the substrate to form a trench; forming a metal floating gate material layer in the trench, the metal floating gate material layer covering the inner wall of the trench and extending to cover the hard mask layer; and performing a nitriding treatment on the metal floating gate material layer to repair ion vacancies in the metal floating gate material layer, forming a stable metal compound crystal structure, preventing the diffusion of free metal ions from affecting the continuity of the metal floating gate material layer, thereby ensuring the continuity of the subsequently formed metal floating gate layer.

[0026] Furthermore, in the method for fabricating the memory described in this invention, a barrier material layer is formed between the metal floating gate material layer and the inner wall of the trench. The barrier material layer can prevent free metal ions in the metal floating gate material layer from diffusing to other film layers, thereby improving the continuity of the metal floating gate material layer. Moreover, annealing the barrier material layer can repair oxygen vacancies in the barrier material layer and prevent oxygen vacancies from capturing free metal ions in the metal floating gate material layer. Attached Figure Description

[0027] Figure 1 A flowchart of the fabrication method of the memory is provided for embodiments of the present invention;

[0028] Figures 2-14 A schematic diagram of the structure corresponding to the corresponding steps of the method for fabricating a memory provided in an embodiment of the present invention;

[0029] The attached figures are labeled as follows:

[0030] 100 - Substrate; 101 - First oxide layer; 102 - Word line material layer; 103 - Second oxide layer; 104 - Hard mask layer; 105 - Tunnel oxide layer; 106 - Barrier material layer; 107 - Metal floating gate material layer; 108 - Barrier oxide layer; 111 - Source line layer; 112 - Source region; 113 - Drain region;

[0031] 20-Trench; 21-First sidewall; 22-Second sidewall; 24-Barrier layer; 25-Metallic floating gate layer; 26-Word line layer; 27-Gate dielectric layer; 28-Dielectric layer; 29-Erase gate. Detailed Implementation

[0032] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0033] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the steps presented herein are not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described in the text may be added to the method.

[0034] This embodiment provides a method for fabricating a memory. Figure 1This is a flowchart of the fabrication method for the memory. Figure 1 As shown, the fabrication method of the memory includes:

[0035] Step S1: Provide a substrate on which a first oxide layer, a word line material layer, a second oxide layer and a hard mask layer are formed in sequence.

[0036] Step S2: Etch a portion of the thickness of the hard mask layer, the second oxide layer, the word line material layer, the first oxide layer, and the substrate to form trenches;

[0037] Step S3: A metal floating grid material layer is formed in the trench, the metal floating grid material layer covering the inner wall of the trench and extending to cover the hard mask layer;

[0038] Step S4: Nitride the metal floating grid material layer.

[0039] Figures 2-14 This is a schematic diagram illustrating the corresponding steps of the fabrication method for the memory provided in this embodiment. Next, we will discuss... Figures 2-14 The fabrication method of the memory is described in detail.

[0040] like Figure 2 As shown, a substrate 100 is provided, on which a first oxide layer 101, a word line material layer 102, a second oxide layer 103 and a hard mask layer 104 are sequentially formed.

[0041] like Figure 3 As shown, the hard mask layer 104 and the second oxide layer 103 are etched until the word line material layer 102 is exposed to form an opening; a first sidewall 21 is formed in the opening, and the first sidewall 21 covers the sidewall of the opening.

[0042] like Figure 4 As shown, using the first sidewall 21 as a mask, the word line material layer 102 and the first oxide layer 101 are etched downwards, deepening the opening until the substrate 100 is exposed; a second sidewall 22 is formed within the opening, covering the sidewalls of the word line material layer 102 and the first oxide layer 101, and extending to cover part of the sidewall of the first sidewall 21; then, using the first sidewall 21 and the second sidewall 22 as a mask, a portion of the substrate 100 is etched further, so that the opening extends into the substrate 100, forming a trench 20, wherein the depth of the trench 20 within the substrate 100 is [insert depth here].

[0043] Furthermore, such as Figure 5As shown, with the trench 20 as the alignment window, a first ion implantation process is performed on the substrate 100 at the bottom of the trench 20 to form a source region 112 in the substrate 100 at the bottom of the trench 20; then a tunneling oxide layer 105 is formed in the trench 20, and the tunneling oxide layer 105 covers the inner wall of the portion of the trench 20 located in the substrate 100.

[0044] like Figure 6 As shown, a barrier material layer 106 is formed in the trench 20, the barrier material layer 106 covers the inner wall of the trench 20 and extends to cover the first sidewall 21 and the top surface of the hard mask layer 104.

[0045] The barrier material layer 106 is made of metal oxides such as hafnium oxide, titanium oxide, and zirconium oxide, and the thickness of the barrier material layer 106 is [missing information]. Because the barrier material layer 106 is relatively thin, it is typically formed using atomic layer deposition. Since oxygen vacancies exist in the barrier material layer 106, these vacancies can negatively impact the performance of semiconductor devices.

[0046] Next, the barrier material layer 106 undergoes an annealing process. This annealing is performed under low-pressure conditions, and oxygen is introduced into the annealing chamber during the process to repair oxygen vacancies in the barrier material layer 106. Specifically, the low-pressure condition is less than 20 torr, and the oxygen flow rate is less than 5 slm. This provides sufficient oxygen ions to repair oxygen vacancies while preventing further reaction between oxygen and the barrier material layer 106, thus avoiding adverse effects on the memory caused by thickening or changes in the properties of the barrier material layer 106. In this embodiment, the annealing process includes a peak annealing process or a laser annealing process. The annealing temperature is less than 900℃, achieving oxygen vacancy repair at a lower temperature and avoiding the creation of more oxygen vacancies due to high temperatures during the annealing process.

[0047] like Figure 7 As shown, a metal floating gate material layer 107 is formed on the barrier material layer 106, and the metal floating gate material layer 107 covers the barrier material layer 106. The metal floating gate material layer 107 is subjected to nitriding treatment.

[0048] The thickness of the metal grating material layer 107 is

[0049] Since the material of the metal floating gate material layer 107 is generally titanium nitride (titanium tetranitride, Ti3N4), the nitrogen-titanium bonds in the titanium nitride unit cell will break at high temperatures, forming free titanium ions and nitrogen vacancies. These free titanium ions will diffuse towards the first sidewall 21, the second sidewall 22, and the barrier oxide layer 108, causing discontinuity or even breakage of the metal floating gate material layer 107. In this embodiment, a barrier material layer 106 is formed between the first sidewall 21, the second sidewall, and the metal floating gate material layer 107 to prevent the free titanium ions in the metal floating gate material layer 107 from diffusing towards the first sidewall 21 and the second sidewall 22. Simultaneously, this embodiment also uses an annealing process to repair the oxygen vacancies in the barrier material layer 106, further preventing the oxygen vacancies in the barrier material layer 106 from capturing free titanium ions, thereby ensuring the continuity of the metal floating gate material layer 107.

[0050] In this embodiment, the nitriding process is a decoupled plasma nitrogen doping process, and the effective power of the decoupled plasma nitrogen doping process is less than 500W, where the effective power is the product of the radio frequency power and the duty cycle. By using the decoupled plasma nitrogen doping process, nitrogen ions are doped into the metal floating gate material layer 107 to repair nitrogen vacancies within the metal floating gate material layer 107. This allows free titanium ions and nitrogen ions to recombine into a stable lattice structure, preventing the remaining titanium ions from diffusing to other film layers and better ensuring the continuity of the metal floating gate material layer 107. Furthermore, controlling the effective power of the decoupled plasma nitrogen doping process can also avoid damage to the lattice structure caused by high-energy ion implantation.

[0051] The decoupled plasma nitrogen doping process can be further followed by a nitriding and annealing process to further promote the polymerization of free titanium ions and nitrogen ions, while repairing the lattice damage caused during the decoupled plasma nitrogen doping process.

[0052] In other alternative embodiments, the nitriding process can be an ammonia annealing process. The metal floating gate layer 107 is annealed with ammonia, utilizing the energy provided during annealing to repolymerize nitrogen ions with free titanium ions, repairing nitrogen vacancies in the metal floating gate material layer and improving the continuity of the metal floating gate material layer 107. The ammonia annealing temperature is 500℃~1100℃, controlling the temperature to prevent the breakage of nitrogen-titanium bonds caused by high process temperatures.

[0053] like Figure 8 As shown, a barrier oxide layer 108 is formed on the barrier material layer 106, and the barrier oxide layer 108 covers the barrier material layer 106. The thickness of the barrier oxide layer 108 is... Since the barrier material layer 106, the metal floating grid layer 107 and the barrier oxide layer 108 all have a small thickness, the stack formed by the barrier material layer 106, the metal floating grid layer 107 and the barrier oxide layer 108 only covers the inner wall of the trench 20 and does not fill the trench 20.

[0054] like Figure 9 As shown, the first sidewall 21, the hard mask layer 104 and the barrier oxide layer 108 on the bottom of the trench 20 are removed by anisotropic etching. The remaining barrier oxide layer 108 covers the metal floating grid material layer 107 on the sidewall of the trench 20.

[0055] like Figure 10 As shown, the first sidewall 21, the hard mask layer 104, and the metal floating grid material layer 107 and the barrier material layer 106 on the bottom of the trench 20 are removed using the barrier oxide layer 108 as a mask. The remaining barrier material layer 106 and the metal floating grid material layer 107 sequentially cover the sidewall of the trench 20 to form a barrier layer 24 and a metal floating grid layer 25.

[0056] like Figure 11 As shown, the remaining barrier oxide layer 108 is removed.

[0057] like Figure 12 As shown, a gate dielectric layer 27 is formed in the trench 20, and the gate dielectric layer 27 covers the sidewall of the metal floating gate layer 25. Since the barrier oxide layer will be corroded by the etchant during the etching process, affecting the properties of the film layer, regenerating the gate dielectric layer 27 is beneficial to ensuring the reliability of the memory. Finally, a source line layer 111 is formed in the trench 20, and the source line layer 111 at least fills part of the trench 20.

[0058] like Figure 13 As shown, after removing the hard mask layer 104 and the second oxide layer 103, and using the first sidewall 21 as a mask, the word line material layer 102 and the first oxide layer 101 are etched, and the remaining word line material layer 102 constitutes the word line layer 26.

[0059] Furthermore, such as Figure 14 As shown, a second ion implantation process is performed on the substrate 100 outside the word line layer 26 to form a drain region 113 in the substrate 100 outside each word line layer 26; then a dielectric layer 28 and an erase gate 29 are formed on the substrate 100, the dielectric layer 28 covering the word line layer 26 and the source line layer 111, and the erase gate 29 being located on the dielectric layer 28 and corresponding to the metal floating gate layer 25.

[0060] In summary, the present invention provides a method for fabricating a memory, comprising: providing a substrate 100, wherein a stacked first oxide layer 101, a word line material layer 102, a second oxide layer 103, and a hard mask layer 104 are formed on the substrate 100; etching a portion of the thickness of the hard mask layer 104, the second oxide layer 103, the word line material layer 102, the first oxide layer 101, and the substrate 100 to form a trench 20; forming a metal floating gate material layer 107 in the trench 20, wherein the metal floating gate material layer 107 covers the inner wall of the trench 20 and extends to cover the hard mask layer 104; and performing a nitriding treatment on the metal floating gate material layer 107 to repair ion vacancies in the metal floating gate layer 107, forming a stable metal compound crystal structure, preventing the diffusion of free metal ions from affecting the continuity of the metal floating gate material layer 107, thereby ensuring the continuity of the subsequent metal floating gate layer 25 formed by the metal floating gate material layer 107.

[0061] Furthermore, in the method for fabricating the memory described in this invention, a barrier material layer 108 is formed between the metal floating gate material layer 107 and the trench 20. The barrier material layer 108 can prevent free metal ions in the metal floating gate material layer 107 from diffusing to other film layers, thereby improving the continuity of the metal floating gate material layer 107. Moreover, annealing the barrier material layer 108 can repair oxygen vacancies in the barrier material layer 108 and prevent oxygen vacancies from capturing free metal ions in the metal floating gate material layer 107.

[0062] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for producing a memory, characterized by, The method comprises: providing a substrate, wherein a first oxide layer, a word line material layer, a second oxide layer and a hard mask layer are sequentially stacked on the substrate; etching a partial thickness of the hard mask layer, the second oxide layer, the word line material layer, the first oxide layer and the substrate to form a trench; forming a metal floating gate material layer in the trench, wherein the metal floating gate material layer covers inner walls of the trench and extends to cover the hard mask layer; nitriding the metal floating gate material layer; after forming the trench and before forming the metal floating gate material layer, the method further comprises: forming a barrier material layer in the trench, wherein the barrier material layer covers the inner walls of the trench and extends to cover the hard mask layer; performing an annealing process on the barrier material layer; after the nitriding process on the metal floating gate material layer, the method further comprises: forming a barrier oxide layer on the metal floating gate material layer, wherein the barrier oxide layer covers the inner walls of the trench and extends to cover the metal floating gate material layer on the hard mask layer; removing the metal floating gate material layer and the barrier material layer on the hard mask layer and at the bottom of the trench with the barrier oxide layer as a mask, wherein the remaining metal floating gate material layer and the remaining barrier material layer respectively form a metal floating gate layer and a barrier layer, and the material of the metal floating gate material layer is titanium nitride; removing the remaining barrier oxide layer; forming a source line layer in the trench, wherein the source line layer at least fills part of the trench; removing the hard mask layer, the second oxide layer, part of the word line material layer and part of the first oxide layer, wherein the remaining word line material layer and the remaining first oxide layer respectively form a word line layer and a tunnel oxide layer.

2. The method of claim 1, wherein the step of depositing the memory material is performed by atomic layer deposition. The annealing process comprises a spike annealing process or a laser annealing process.

3. The method for fabricating the memory as described in claim 1, characterized in that, Oxygen is introduced when the annealing process is performed on the barrier material layer.

4. The method of producing a memory according to claim 3, wherein The flow rate of the introduced oxygen is less than 5 slm.

5. The method of producing a memory according to claim 1, wherein The nitriding process comprises a decoupled plasma nitriding process on the metal floating gate material layer.

6. The method of producing a memory according to claim 5, wherein The effective power of the decoupled plasma nitriding process is less than 500 W.

7. The method of producing a memory according to claim 1, wherein The nitriding process comprises an ammonia annealing process on the metal floating gate material layer.

8. The method of producing a memory according to claim 7, wherein The temperature of the ammonia annealing process is 500°C-1100°C.

Images