A method for manufacturing a semiconductor structure and a semiconductor structure

By using a method of fabricating isolation structures in different regions, the problem of word line deposition in fully enclosed gate transistors was solved, achieving high-yield semiconductor structure fabrication, simplifying the process flow, and improving word line deposition quality.

CN115116952BActive Publication Date: 2026-07-24CHANGXIN MEMORY TECH INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
CHANGXIN MEMORY TECH INC
Filing Date
2022-06-24
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

In existing processes for fabricating fully enclosed gate transistors, the space available for word lines is small, making it difficult to deposit and form word lines. This results in empty areas in the semiconductor structure, affecting product yield.

Method used

The method of preparing the isolation structure by region first forms an isolation layer containing a first sub-isolation layer and a second sub-isolation layer. After etching, word lines are formed on the side wall of the pillar, and a dielectric layer is covered on the word lines to form an isolation structure. This simplifies the word line preparation process and avoids depositing void areas.

Benefits of technology

It improves the yield of semiconductor structure fabrication, simplifies the process flow, increases the opening for word line fabrication, reduces the trench aspect ratio, and improves word line deposition quality.

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Abstract

The application relates to the technical field of semiconductor manufacturing processes, and discloses a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises the following steps: providing a substrate, forming array-arranged column bodies on the surface of the substrate, and forming bit lines extending along a first direction at the bottom of the column bodies; forming first grooves extending along a second direction between adjacent column bodies; forming an isolation layer on the substrate, and the isolation layer is filled between the first grooves and the adjacent bit lines; etching the isolation layer to expose the surface of the column body, and a first sub-isolation layer located in the first groove is lower than a second sub-isolation layer; forming a word line surrounding the sidewall of the column body on the first sub-isolation layer, and the surface of the word line does not exceed the surface of the second sub-isolation layer; forming a dielectric layer on the word line, the dielectric layer covers the second sub-isolation layer and the word line, and the dielectric layer and the isolation layer form an isolation structure of the word line. The preparation method can simplify the preparation process of the word line, and improve the product yield of the prepared semiconductor structure.
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