Dynamic random access memory and manufacturing method thereof

Abstract

The present invention provides a dynamic random access memory and a manufacturing method thereof, comprising: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on the side wall of the opening; forming a first part of a buried word line at the bottom of the opening; forming a barrier layer on the top surface of the hard mask layer, the barrier layer having an overhang and covering the top corner of the hard mask layer; depositing a first barrier layer on the substrate through the obstruction of the overhang, the first barrier layer covering the barrier layer and the top surface of the first part and exposing the dielectric layer on the side wall of the opening; and forming a first conductor layer in the opening, the side wall of the first conductor layer being in contact with the dielectric layer.

Description

Technical Field

[0001] The present invention relates to an integrated circuit and a manufacturing method thereof, and in particular to a dynamic random access memory and a manufacturing method thereof. Background Art

[0002] With the rapid development of technology, in order to meet the needs of consumers for miniaturized electronic devices, the size of dynamic random access memory design continues to shrink and develop towards high integration. In recent years, buried word line dynamic random access memory (buried word line DRAM) has been developed. In the process of buried word line dynamic random access memory, as the size of components continues to shrink, the process margin also becomes smaller. When forming a buried word line, if there is metal or barrier layer remaining on the dielectric layer of the buried word line trench sidewall, it will cause component reliability problems. Summary of the invention

[0003] The invention is directed to a dynamic random access memory and a manufacturing method thereof, which can prevent metal or barrier layer from remaining on the dielectric layer of the side wall of the buried word line trench and improve the reliability of the component.

[0004] According to an embodiment of the present invention, a method for manufacturing a dynamic random access memory is provided, comprising: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on the sidewall of the opening; forming a first portion of a buried word line at the bottom of the opening; forming a barrier layer on the substrate, the barrier layer covering the top surface of the hard mask layer and having an overhang, covering the top corner of the hard mask layer; depositing a first barrier layer on the substrate through the obstruction of the overhang, the first barrier layer covering the barrier layer and the top surface of the first portion, exposing the dielectric layer on the sidewall of the opening; and forming a first conductor layer in the opening, the first conductor layer covering the top surface of the first barrier layer, and the sidewall of the first conductor layer contacting the dielectric layer.

[0005] According to an embodiment of the present invention, a dynamic random access memory is provided, comprising: a substrate having an opening; a dielectric layer formed on the sidewall of the opening; a first portion of a buried word line located at a lower portion of the opening; a second portion of the buried word line located on the first portion, comprising: a first barrier layer located in the opening and covering a top surface of the first portion; and a first conductor layer located in the opening, the first conductor layer covering a top surface of the first barrier layer, and the sidewall of the first conductor layer in contact with the dielectric layer.

[0006] Based on the above, the overhang formed at the opening end of the embodiment of the present invention can hinder the deposition of the barrier layer, making it difficult for the barrier layer to be deposited on the sidewall of the buried word line trench. Thereby, after the barrier layer is deposited, the deposition process of doped polysilicon can be directly performed. Since there is no need to go through the etching process, the process steps can be saved, and the formed component has high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1H It is a cross-sectional schematic diagram of a method for manufacturing a dynamic random access memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0008] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0009] Please refer to Figure 1A , provide a substrate 10, such as a silicon substrate. Then, form a hard mask layer 12 having an opening pattern on the substrate 10. The method for forming the hard mask layer 12 is, for example, to first form a hard mask layer material layer. Then, the hard mask layer material layer is patterned by photolithography and etching processes. The material of the hard mask layer material layer is, for example, silicon oxide, and the method of formation is, for example, thermal oxidation or chemical vapor deposition. Thereafter, an etching process is performed using the hard mask layer 12 as a mask to partially remove the substrate 10 to form an opening 14. The opening 14 is, for example, a trench. In the present embodiment, the buried word line trench 14 is used as an example of the opening 14 for illustration, but the present invention is not limited thereto. The depth H1 of the buried word line trench 14 is, for example, 110nm to 130nm. The aspect ratio of the buried word line trench 14 is, for example, 3 to 10.

[0010] Please refer to Figure 1A , a dielectric layer 16, a barrier layer 18 and a conductor layer 20 are formed on the hard mask layer 12 and in the buried word line trench 14. The dielectric layer 16 is conformally formed on the inner surface of the buried word line trench 14. The dielectric layer 16 can be an oxide layer, such as silicon oxide, and the method of forming it is, for example, in-situ steam generation technology (ISSG). The barrier layer 18 can also be called an adhesion layer. The barrier layer 18 can be a single layer or a multi-layer, and its material includes metal or metal alloy, such as titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof. The material of the conductor layer 20 includes metal or metal alloy, such as tungsten.

[0011] Please refer to Figure 1B , an etching process or a chemical mechanical polishing process is performed to remove the barrier layer 18 and the conductive layer 20 on the hard mask layer 12 , leaving the barrier layer 18 a and the conductive layer 20 a in the buried word line trench 14 .

[0012] Please refer to Figure 1C , an etch-back process is performed to partially remove the barrier layer 18a and the conductor layer 20a, so that the remaining barrier layer 18b and the conductor layer 20b are located at the lower sidewall LSW and the bottom of the buried word line trench 14. The height H2 of the remaining conductor layer 20b is, for example, about 1 / 4 to 1 / 3 of the depth H1 of the buried word line trench 14. In some embodiments, the height H2 of the remaining conductor layer 20b is, for example, between 50nm and 60nm. The conductor layer 20b and the barrier layer 18b are located at the lower part of the buried word line trench 14 as the first part P1 of the buried word line.

[0013] Please refer to Figure 1D , a barrier layer 22 is formed on the substrate 10. The barrier layer 22 has poor step coverage and has an overhang 23 at the top corner of the buried word line trench 14. The barrier layer 22 covers the top surface of the hard mask layer 12 and covers the sidewalls of the hard mask layer 12, the sidewalls of the buried word line trench 14, and the upper surfaces of the barrier layer 18b and the conductor layer 20b. The material of the barrier layer 22 includes a dielectric material, such as silicon oxide. The barrier layer 22 is formed by, for example, enhanced chemical vapor deposition.

[0014] Please refer to Figure 1E , the barrier layer 22 covering the upper sidewall USW of the buried word line trench 14 and the barrier layer 18b and the conductor layer 20b is removed to expose the sidewall of the hard mask layer 12, the upper sidewall USW of the buried word line trench 14, and the top surface of the barrier layer 18b and the conductor layer 20b. The remaining barrier layer 22a covers the top surface of the hard mask layer 12. The barrier layer 22a also has an overhang 23 covering the top corner of the hard mask layer 12. The width W2 of the opening 24 between the overhangs 23 is smaller than the width W1 of the buried word line trench 14.

[0015] Please refer to Figure 1F, a barrier layer 26 is formed on the substrate 10. The barrier layer 26 may be a single layer or a multilayer, and its material includes a metal or a metal alloy, such as titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof. The barrier layer 26 may be formed by a physical vapor deposition method, such as a sputtering method. The barrier layer 26 includes a barrier layer 26a and a barrier layer 26b. The barrier layer 26a covers the top surface and sidewall of the barrier layer 22a or further covers the sidewall of the hard mask layer 12. The barrier layer 26b is filled in the buried word line trench 14 and covers the upper surface of the barrier layer 18b and the conductor layer 20b. Since the overhang 23 of the barrier layer 22a hinders the deposition direction of the barrier layer 26, it is difficult for the barrier layer 26 to be formed on the upper sidewall USW of the buried word line trench 14 close to the barrier layer 26b. There is only a little or no barrier layer 26 deposited on the sidewall of the dielectric layer 16 away from the barrier layer 26b on the upper sidewall USW of the buried word line trench 14. No barrier layer 26 is deposited on the sidewall of the dielectric layer 16 near the barrier layer 26b, so the barrier layer 26a is separated from the barrier layer 26b. The thickness of the barrier layer 26b is, for example, 2nm to 3nm.

[0016] Please refer to Figure 1G Since the barrier layer 26a and the barrier layer 26b are separated from each other, there is no need to perform an etching process to remove the barrier layer 26 on the upper sidewall USW of the buried word line trench 14, and the subsequent deposition process can be directly performed. Next, a conductor layer 28 is formed in the buried word line trench 14. The material of the conductor layer 28 is different from that of the conductor layer 20. In some embodiments, the conductor layer 20 is a metal or a metal alloy; the conductor layer 28 is doped polysilicon. The bottom surface of the conductor layer 28 covers and contacts the barrier layer 26b, and the sidewall of the conductor layer 28 contacts the dielectric layer 16. The conductor layer 28 can be formed by depositing and etching back the doped polysilicon layer. The conductor layer 28 is, for example, 10nm to 20nm. The conductor layer 28 and the barrier layer 26a, the barrier layer 18b and the conductor layer 20b form a buried word line 30. The barrier layer 18b and the conductor layer 20b together serve as the first portion P1 of the buried word line 30; the conductor layer 28 and the barrier layer 26a together serve as the second portion P2 of the buried word line 30. The conductor layer 20b of the first portion P1 has a lower resistance than the conductor layer 28, and the conductor layer 20b is separated from the dielectric layer 16 by the barrier layer 18b. The conductor layer 28 of the second portion P2 contacts the dielectric layer 16 and is separated from the conductor layer 20b by the barrier layer 26a.

[0017] Please refer to Figure 1G , an insulating layer 32 is formed in the buried word line trench 14. The material of the insulating layer 32 is, for example, silicon nitride. The insulating layer 32 is formed by, for example, depositing and etching back an insulating material layer.

[0018] Please refer to Figure 1H, a planarization process is performed to remove the barrier layer 22 a , the barrier layer 26 a and the insulating layer 32 above the hard barrier layer 12 .

[0019] In summary, the present invention forms a barrier layer with an overhang on the substrate before depositing the barrier layer. The barrier of the overhang makes it difficult for the barrier layer to be deposited on the sidewall of the buried word line trench. Therefore, after the barrier layer is deposited, the deposition process of doped polysilicon can be directly performed. Since there is no need to go through the etching process, the process steps can be saved, and the formed component has high reliability.

[0020] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a dynamic random access memory, characterized in that include: forming a hard mask layer on the substrate; forming openings in the hard mask layer and the substrate; forming a dielectric layer on the sidewalls of the opening; forming a first portion of a buried word line at a lower portion of the opening; forming a barrier layer on the substrate, wherein the barrier layer covers the top surface of the hard mask layer and has an overhang covering the top corner of the hard mask layer; Depositing a first barrier layer on the substrate by blocking the overhang, wherein the first barrier layer covers the barrier layer and the top surface of the first portion, exposing the dielectric layer on the sidewall of the opening; as well as forming a first conductor layer in the opening, wherein the first conductor layer covers a top surface of the first barrier layer, and a sidewall of the first conductor layer contacts the dielectric layer, The first portion of the buried word line formed at the lower portion of the opening includes: forming a second barrier layer in the opening; as well as A second conductive layer is formed in the opening, wherein a material of the second conductive layer is different from a material of the first conductive layer. 2 . The method for manufacturing a dynamic random access memory according to claim 1 , wherein after depositing the first barrier layer on the substrate, the first conductive layer is formed in the opening. 3 . 3 . The method for manufacturing a dynamic random access memory according to claim 1 , wherein between the steps of depositing the first barrier layer on the substrate and forming the first conductor layer in the opening, there is no need to perform a step of etching the first barrier layer. 4 . The method for manufacturing a dynamic random access memory according to claim 1 , wherein a method of depositing the first barrier layer on the substrate comprises a physical vapor deposition method. 5 . The method for manufacturing a dynamic random access memory according to claim 1 , wherein a method of forming the barrier layer on the substrate comprises a plasma enhanced chemical vapor deposition method. 6 . The method for manufacturing a dynamic random access memory according to claim 1 , further comprising filling an insulating layer in the opening to cover the first conductive layer. 7 . The method for manufacturing a dynamic random access memory according to claim 1 , further comprising removing the hard mask layer and the barrier layer and the first barrier layer thereon.

8. A dynamic random access memory, characterized in that include: a substrate having an opening therein; forming a dielectric layer on the sidewalls of the opening; a first portion of the buried word line located at a lower portion of the opening; as well as A second portion of the buried word line, located on the first portion, comprises: a first barrier layer, located in the opening and covering a top surface of the first portion; and a first conductor layer, located in the opening, the first conductor layer covers the top surface of the first barrier layer, and the sidewall of the first conductor layer contacts the dielectric layer, The first part includes: A second conductor layer is located in the opening; and The second barrier layer is located between the second conductor layer and the dielectric layer, wherein the material of the second conductor layer is different from that of the first conductor layer. 9 . The dynamic random access memory according to claim 8 , wherein the first conductor layer comprises metal or metal alloy, and the second conductor layer comprises doped polysilicon.

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