Semiconductor devices

Abstract

The embodiment provides a semiconductor device with high reliability. The semiconductor device of the embodiment comprises: a mounting substrate provided with a first electrode pad and a second electrode pad; a semiconductor element provided on the mounting substrate, having a supporting substrate, a third electrode pad provided on a surface of the supporting substrate facing the mounting substrate, and a fourth electrode pad provided on a surface of the supporting substrate facing the mounting substrate, a first slit provided on the supporting substrate and the third electrode pad, and a second slit provided on the supporting substrate and the fourth electrode pad; a first conductive adhesive connecting the first electrode pad and the third electrode pad; and a second conductive adhesive connecting the second electrode pad and the fourth electrode pad.

Description

[0001] [Related applications]

[0002] This application claims priority based on Japanese Patent Application No. 2021-47800 (filing date: March 22, 2021). This application includes all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] A photorelay including a photocoupler type insulation circuit can convert an input electrical signal into an optical signal using a light emitting element, and output the electrical signal after the light receiving element receives the signal. Therefore, the photorelay can transmit electrical signals while isolating the input and output.

[0005] Photorelays for AC loads are often used in semiconductor testers that inspect semiconductor integrated circuits, etc. With the demand for wider bandwidths for DRAM (Dynamic Random Access Memory), semiconductor devices with photorelays that can pass high-frequency signals with frequencies higher than several GHz with low loss are required. Summary of the invention

[0006] Embodiments provide a semiconductor device with high reliability.

[0007] A semiconductor device in an embodiment comprises: a mounting substrate provided with a first electrode pad and a second electrode pad; a semiconductor element provided on the mounting substrate, having a supporting substrate, a third electrode pad provided on a surface of the supporting substrate facing the mounting substrate, and a fourth electrode pad provided on a surface of the supporting substrate facing the mounting substrate, a first slit provided on the supporting substrate and the third electrode pad, and a second slit provided on the supporting substrate and the fourth electrode pad; a first conductive adhesive connecting the first electrode pad and the third electrode pad; and a second conductive adhesive connecting the second electrode pad and the fourth electrode pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment.

[0009] Figure 2 It is a schematic top view of a semiconductor device according to an embodiment.

[0010] Figure 3 This is a schematic perspective view of a wiring substrate according to an embodiment.

[0011] Figure 4 It is a schematic diagram of the process of an implementation method.

[0012] Figure 5 It is a schematic diagram of a wiring substrate according to an embodiment.

[0013] Figure 6 It is a schematic top view of a semiconductor device according to an embodiment.

[0014] Figure 7 It is a schematic diagram of a wiring substrate according to an embodiment.

[0015] Figure 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment.

[0016] Fig. 9 It is a schematic perspective view of a photorelay according to an embodiment.

[0017] Fig.10 It is a structural diagram of a photorelay according to an embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same or similar components are sometimes denoted by the same reference numerals, and the description of components that have been described once is omitted.

[0019] In this specification, in order to indicate the positional relationship of components, the upper direction of the drawings is described as "up", and the lower direction of the drawings is described as "down". In this specification, the concepts of "up" and "down" are not necessarily terms indicating the relationship with the direction of gravity.

[0020] The physical properties in the specification are values ​​in an air atmosphere at 25°C.

[0021] (First Embodiment)

[0022] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment. Figure 2 It is a schematic top view of a semiconductor device according to an embodiment.

[0023] The semiconductor device 100 includes a mounting substrate 10 , a semiconductor element 20 , a first conductive adhesive 13 , and a second conductive adhesive 14 .

[0024] The mounting substrate 10 is a substrate connected to the semiconductor element 20. The mounting substrate 10 is, for example, a printed circuit board. A first electrode pad 11 and a second electrode pad 12 are provided on the surface of the mounting substrate 10 facing the semiconductor element 20. The two-part first electrode pad 11 and the two-part second electrode pad 12 are provided on the surface of the mounting substrate 10.

[0025] The semiconductor element 20 is provided on the mounting substrate 10. The semiconductor element 20 has a supporting substrate 21, a third electrode pad 22, and a fourth electrode pad 23. The semiconductor element 20 is placed on the mounting substrate 10 via the first conductive adhesive 13 and the second conductive adhesive 14. The semiconductor element 20 is, for example, a photorelay. The semiconductor element 20 has a supporting substrate 21 on the surface facing the mounting substrate 10. Two portions of the third electrode pad 22 and two portions of the fourth electrode pad 23 are provided on the surface of the supporting substrate 21 facing the mounting substrate 10.

[0026] The first electrode pad 11 of the mounting substrate 10 is opposed to the third electrode pad 22 of the semiconductor element 20. The first electrode pad 11 and the third electrode pad 22 overlap in the vertical direction of the surface of the mounting substrate 10 facing the semiconductor element 20. From the viewpoint of confirming the bonding portion between the mounting substrate 10 and the semiconductor element 20 by visual observation, it is preferred that when the first electrode pad 11 and the semiconductor element 20 are overlapped in the direction vertical to the surface of the mounting substrate 10 facing the semiconductor element 20 (when viewed from the semiconductor element 20 side toward the mounting substrate 10), a portion of the first electrode pad 11 protrudes outward from the outer periphery of the semiconductor element 20 in the surface direction of the mounting substrate 10.

[0027] The second electrode pad 12 of the mounting substrate 10 is opposed to the fourth electrode pad 23 of the semiconductor element 20. The second electrode pad 12 and the fourth electrode pad 23 overlap in the vertical direction of the surface of the mounting substrate 10 facing the semiconductor element 20. From the viewpoint of confirming the bonding portion between the mounting substrate 10 and the semiconductor element 20 by visual observation, it is preferred that when the second electrode pad 12 and the semiconductor element 20 are overlapped in the vertical direction from the surface of the mounting substrate 10 facing the semiconductor element 20 (when viewed from the semiconductor element 20 side toward the mounting substrate 10), a portion of the second electrode pad 12 protrudes outward from the outer periphery of the semiconductor element 20 in the surface direction of the mounting substrate 10.

[0028] It is preferable that the third electrode pad 22 and the fourth electrode pad 23 are not provided at the corners of the support substrate 21 .

[0029] The first conductive adhesive 13 is provided between the mounting substrate 10 and the semiconductor element 20 to electrically connect the semiconductor element 20 to the mounting substrate 10. The first electrode pad 11 of the mounting substrate 10 and the third electrode pad 22 of the semiconductor element 20 are connected by the first conductive adhesive 13. The first conductive adhesive 13 is, for example, solder. From the viewpoint of improving the reliability of the connection between the mounting substrate 10 and the semiconductor element 20, the first conductive adhesive 13 is preferably also provided in the first slit 24.

[0030] The second conductive adhesive 14 is provided between the mounting substrate 10 and the semiconductor element 20 to electrically connect the semiconductor element 20 to the mounting substrate 10. The second electrode pad 12 of the mounting substrate 10 and the fourth electrode pad 23 of the semiconductor element 20 are connected by the second conductive adhesive 14. The second conductive adhesive 14 is, for example, solder. From the viewpoint of improving the reliability of the connection between the mounting substrate 10 and the semiconductor element 20, the second conductive adhesive 14 is preferably also provided in the second slit 25.

[0031] The first slit 24 is provided on the third electrode pad 22 of the semiconductor element 20 and the support substrate 21. The side surface of the third electrode pad 22 and the side surface of the support substrate 21 are part of the side surface of the semiconductor element 20. The side surface of the third electrode pad 22 is connected to the side surface of the support substrate 21. The third electrode pad 22 and the support substrate 21 are stacked. The surface of the third electrode pad 22 facing the support substrate 21 is in direct contact with the surface of the support substrate 21 facing the third electrode pad 22. The entire surface of the surface of the third electrode pad 22 facing the support substrate 21 is in direct contact with the surface of the support substrate 21 facing the third electrode pad 22.

[0032] like Figure 3 As shown in the schematic diagram of the support substrate 21 of FIG. 1 , the first slit 24 is preferably provided from the outer periphery of the semiconductor element 20 toward the center of the support substrate 21. That is, the opening of the first slit 24 is located on the outer periphery side of the semiconductor element 20. Due to the surface tension during bonding, the first conductive adhesive 13 easily penetrates the first slit 24. In addition, since the opening of the first slit 24 is located on the outer periphery side of the semiconductor element 20, the first conductive adhesive 13 easily spreads from the opening side to the outside, and the bonding portion between the semiconductor element 20 and the mounting substrate 10 is easily confirmed. If the first slit 24 opens in the center direction of the support substrate 21, the first conductive adhesive 13 may spread in the center direction, which may easily cause an unintended short circuit, and may also cause a decrease in the frequency characteristics of the semiconductor device 100. In addition, in the present embodiment, for example, the first slit 24a provided in the support substrate 21 and the first slit 24b provided in the third electrode pad 22 are provided as the first slit 24.

[0033] In consideration of frequency characteristics and processability, it is preferred that the shape of the first slit 24 provided in the support substrate 21 is the same (substantially the same) as the shape of the first slit 24 provided in the third electrode pad 22. The first slit 24 penetrates the third electrode pad 22 and the support substrate 21 in the thickness direction, and the components in the semiconductor element 20 are electrically connected to the mounting substrate 10 via the first slit 24.

[0034] From the perspective of confirming the bonding portion between the mounting substrate 10 and the semiconductor element 20 by visual observation, when the first conductive adhesive 13 and the semiconductor element 20 are overlapped in a direction perpendicular to the surface of the mounting substrate 10 facing the semiconductor element 20 (when viewed from the semiconductor element 20 side toward the mounting substrate 10), a portion of the first conductive adhesive 13 preferably extends outwardly in the surface direction of the mounting substrate 10 by a length (L1) of not less than 0.05 mm and not more than 0.2 mm, and more preferably extends outward by a length (L1) of not less than 0.1 mm and not more than 0.15 mm, more preferably.

[0035] The first conductive adhesive 13 preferably has a surface inclined from the third electrode pad 22 toward the outer periphery of the first electrode pad 11. More specifically, the first conductive adhesive 13 preferably has a surface inclined from the opening of the first slit 24 toward the outer periphery of the first electrode pad 11. By confirming the inclined surface, it is possible to evaluate the connection between the semiconductor element 20 and the mounting substrate 10. The shape of the inclined surface of the first conductive adhesive 13 may partially include a curved surface.

[0036] The inside of the first slit 24 is preferably plated with a metal such as Cu. The plating inside the first slit 24 is formed on the inner side surface of the support substrate 21 formed with the first slit 24, the inner side surface of the third electrode pad 22 formed with the first slit 24, or both the inner side surface of the support substrate 21 formed with the first slit 24 and the inner side surface of the third electrode pad 22 formed with the first slit 24.

[0037] The height of the first slit 24 is preferably the sum of the thickness of the supporting substrate 21 and the thickness of the third electrode pad 22. The height of the first slit 24 is, for example, greater than 10 μm and less than 100 μm, for example, preferably greater than 25 μm and less than 75 μm. The width of the first slit 24 (the width of the opening) is preferably less than half the width of the side of the third electrode pad 22 having the opening of the first slit 24. Since the first slit 24 has a length, if the width of the first slit 24 is too wide, the strength of the supporting substrate 21 is reduced. In addition, if the width of the first slit 24 is too narrow, the effect of providing the first slit 24 cannot be obtained. Therefore, specifically, the width of the first slit 24 is, for example, greater than 5 μm and less than 100 μm, for example, preferably greater than 50 μm and less than 75 μm.

[0038] Unlike the cylindrical through hole, the first slit 24 extends in the surface direction of the support substrate 21. The mounting substrate 10 and the semiconductor element 20 are connected via the first conductive adhesive 13 in contact with the first slit 24 having a larger surface than the through hole, so that the reliability of the connection can be improved. The length of the first slit 24 is longer than the height of the first slit 24 and longer than the width of the first slit 24. The length of the first slit 24 is preferably 4 times or more of the height of the first slit 24 and 4 times or more of the width of the first slit 24.

[0039] The second slit 25 is provided on the fourth electrode pad 23 of the semiconductor element 20 and the support substrate 21. The side surface of the fourth electrode pad 23 and the side surface of the support substrate 21 are part of the side surface of the semiconductor element 20. The side surface of the fourth electrode pad 23 is connected to the side surface of the support substrate 21. The fourth electrode pad 23 and the support substrate 21 are stacked. The surface of the fourth electrode pad 23 facing the support substrate 21 is in direct contact with the surface of the support substrate 21 facing the fourth electrode pad 23. The entire surface of the surface of the fourth electrode pad 23 facing the support substrate 21 is in direct contact with the surface of the support substrate 21 facing the fourth electrode pad 23.

[0040] like Figure 3 As shown in the schematic diagram of the support substrate 21 of FIG. 1 , the second slit 25 is preferably provided from the outer periphery of the semiconductor element 20 toward the center of the support substrate 21. That is, the opening of the second slit 25 is located on the outer periphery side of the semiconductor element 20. Due to the surface tension during bonding, the second conductive adhesive 14 easily penetrates the second slit 25. In addition, since the opening of the second slit 25 is provided on the outer periphery side of the semiconductor element 20, the second conductive adhesive 14 easily spreads from the opening side to the outside, and the bonding portion between the semiconductor element 20 and the mounting substrate 10 is easily confirmed. If the second slit 25 opens in the center direction of the support substrate 21, the second conductive adhesive 14 may spread in the center direction, which may easily cause an unintended short circuit, and may also cause a decrease in the frequency characteristics of the semiconductor device 100. In addition, in the present embodiment, for example, the second slit 25a provided in the support substrate 21 and the second slit 25b provided in the third electrode pad 22 are provided as the second slit 25.

[0041] In consideration of frequency characteristics and processability, it is preferred that the shape of the second slit 25 provided in the support substrate 21 is the same (substantially the same) as the shape of the second slit 25 provided in the fourth electrode pad 23. The second slit 25 penetrates the fourth electrode pad 23 and the support substrate 21 in the thickness direction, and the components in the semiconductor element 20 are electrically connected to the mounting substrate 10 via the second slit 25.

[0042] From the perspective of confirming the bonding portion between the mounting substrate 10 and the semiconductor element 20 by visual observation, when the second conductive adhesive 14 and the semiconductor element 20 are overlapped in a direction perpendicular to the surface of the mounting substrate 10 facing the semiconductor element 20 (when viewed from the semiconductor element 20 side toward the mounting substrate 10), a portion of the second conductive adhesive 14 preferably extends outwardly in the surface direction of the mounting substrate 10 by a length (L2) of not less than 0.05 mm and not more than 0.1 mm, and more preferably extends outward by a length (L2) of not less than 0.1 mm and not more than 0.15 mm, more preferably.

[0043] The second conductive adhesive 14 preferably has a surface inclined from the fourth electrode pad 23 toward the outer periphery of the second electrode pad 12. More specifically, the second conductive adhesive 14 preferably has a surface inclined from the opening of the second slit 25 toward the outer periphery of the second electrode pad 12. By confirming the inclined surface, it is possible to evaluate the connection between the semiconductor element 20 and the mounting substrate 10. The shape of the inclined surface of the second conductive adhesive 14 may partially include a curved surface.

[0044] The inside of the second slit 25 is preferably plated with a metal such as Cu. The plating inside the second slit 25 is formed on the inner side surface of the support substrate 21 formed with the second slit 25, the inner side surface of the fourth electrode pad 23 formed with the second slit 25, or both the inner side surface of the support substrate 21 formed with the second slit 25 and the inner side surface of the fourth electrode pad 23 formed with the second slit 25.

[0045] The height of the second slit 25 is preferably the sum of the thickness of the supporting substrate 21 and the thickness of the fourth electrode pad 23. The height of the second slit 25 is, for example, greater than 10 μm and less than 100 μm, for example, preferably greater than 25 μm and less than 75 μm. The width of the first slit 24 (the width of the opening) is preferably less than half the width of the side of the fourth electrode pad 23 having the opening of the second slit 25. Since the second slit 25 has a length, if the width of the second slit 25 is too wide, the strength of the supporting substrate 21 is reduced. In addition, if the width of the second slit 25 is too narrow, the effect of providing the second slit 25 cannot be obtained. Therefore, specifically, the width of the second slit 25 is, for example, greater than 25 μm and less than 100 μm, for example, preferably greater than 50 μm and less than 100 μm.

[0046] Unlike the cylindrical through hole, the second slit 25 extends in the surface direction of the support substrate 21. The mounting substrate 10 and the semiconductor element 20 are connected via the second conductive adhesive 14 in contact with the second slit 25 having a larger surface than the through hole, so that the reliability of the connection can be improved. The length of the second slit 25 is longer than the height of the second slit 25 and longer than the width of the second slit 25. The length of the second slit 25 is preferably 4 times or more of the height of the second slit 25 and 4 times or more of the width of the second slit 25.

[0047] The support substrate 21 having the slits of the embodiment can be, for example, Figure 4 The component shown in the process diagram of is obtained by processing. A component having a long electrode pad 22 (23) provided on a support substrate 21 is prepared, a slit is formed, and an electrode pad is also provided on the surface of the support substrate 21 on the opposite side of the long electrode pad 22 (23), and then cut, thereby obtaining the support substrate 21 of the semiconductor element 20. By using a laser, a slit that penetrates the support substrate 21 and the electrode pad 22 (23) is formed.

[0048] Two or more slits may be provided for one electrode pad. In addition, the slit may be provided in the form of two openings bent in the electrode pad. Specifically, Figure 5 As shown in the schematic diagram of the support substrate 21 of FIG. 1 , the first slit 24 is bent at a right angle in the third electrode pad 22, and has a second opening in the lateral direction of the semiconductor element 20. In addition, the second slit 25 is bent at a right angle in the fourth electrode pad 23, and has a second opening in the lateral direction of the semiconductor element 20. If the semiconductor element 20 having the support substrate 21 of this type is used in the semiconductor device 100, as shown in FIG. Figure 6 As shown in the top view of the schematic diagram, the first conductive adhesive 13, the second conductive adhesive 14, or both the first conductive adhesive 13 and the second conductive adhesive 14 are connected from any one of the four side surfaces of the semiconductor element 20 toward the mounting substrate 10. In the case where the slit is bent, the length to the portion where the slit is bent is the length of the slit.

[0049] The first slit 24 and the second slit 25 may pass through the center of the third electrode pad 22 and the fourth electrode pad 23, respectively, or may be staggered (offset) in the vertical direction. Figure 5 In the case of the first slit 24 and the second slit 25 as shown in the schematic diagram of FIG, they may be staggered not only vertically but also horizontally.

[0050] In addition, the support substrate 21 may be provided with not only the first slit 24 and the second slit 25 but also a through hole 26 .

[0051] (Second Embodiment)

[0052] The second embodiment is a modification of the semiconductor device 100 of the first embodiment. Figure 8 2 is a cross-sectional view of a semiconductor device 200 according to the second embodiment. The semiconductor element 20 according to the second embodiment is a photorelay. Fig. 9 A schematic perspective view of the semiconductor element 20 is shown.

[0053] The photorelay 20 includes a light receiving element 31 having a light receiving surface on its upper surface, a light emitting element 32 for irradiating light onto the light receiving surface, and a MOSFET 33 ( 34 ) as a switching element.

[0054] The photorelay 20 includes: a MOSFET 33 (34) bonded to the output terminal portions 41 and 42; a light receiving element 31 bonded to the die pad portion 35 and having a light receiving surface on the upper surface; a light emitting element 32 irradiating light to the light receiving surface; an adhesive layer 36 having light transmittance and insulation properties and bonding the light emitting element 32 to the upper surface of the light receiving element 31; and a first sealing resin 90. The light emitting element 32 can use, for example, an LED (Light Emitting Diode). In addition, the light receiving element 31 can use a photodiode, a phototransistor, a light receiving IC, or the like.

[0055] In this figure, MOSFET 33 (34) is assumed to include two elements with a source and a common connection. However, the present invention is not limited to this, and it can also be a single MOSFET. If the back side of the chip of each MOSFET 33 (34) is used as a drain, the output terminals 41 and 42 are connected to the drain of each MOSFET 33 (34).

[0056] The first sealing resin 90 covers the light receiving element 31 , the light emitting element 32 , the MOSFET 33 ( 34 ), and the first surface 10 a of the polyimide substrate 21 to protect the inside. The light emitting element 32 may be further sealed by the second sealing resin 91 .

[0057] A polyimide substrate is preferably used as the support substrate 21. The polyimide substrate 21 is provided with a MOSFET 33 (34), a light receiving element 31, a light emitting element 32, etc. on the first surface side of the rectangle, and a third electrode pad 22 and a fourth electrode pad 23 are provided on the second surface side opposite to the first surface. The third electrode pad 22 is provided with a first slit 24. The fourth electrode pad 23 is provided with a second slit 25.

[0058] The thickness of the polyimide substrate 21 is preferably set to be greater than 10 μm and less than 120 μm. In this way, by using an extremely thin polyimide substrate 21, the pass characteristics in a high-frequency band such as 15 GHz to 30 GHz can be improved. From the viewpoint of improving the pass characteristics in the high-frequency band, the thickness of the polyimide substrate 21 is more preferably greater than 10 μm and less than 100 μm. From the viewpoint of improving the pass characteristics in a further high-frequency band above 20 GHz, the thickness of the polyimide substrate 21 is preferably greater than 10 μm and less than 60 μm, and more preferably greater than 10 μm and less than 30 μm. By thinning the thickness of the polyimide substrate 21, for example, to less than 60 μm, it is preferred that the pass characteristics of a higher-frequency high-frequency band are further improved. Since the polyimide substrate 21 is thin, the high-frequency pass characteristics can be improved.

[0059] The semiconductor element 20 has two output terminal portions 41 and 42 as output terminals, for example. The thickness of the output terminal portions 41 and 42 is preferably 5 μm or more and 50 μm or less. The output terminal portions 41 and 42 are electrode pads and are electrically connected to the third electrode pad 22 provided on the second surface side of the support substrate 21. The first slit 24 is not provided in the output terminal portions 41 and 42.

[0060] The semiconductor element 20 has, for example, two input terminal portions 43 and 44 as input terminals. The input terminal portions 43 and 44 are electrode pads and are electrically connected to the fourth electrode pad 23 provided on the second surface side of the support substrate 21. The thickness of the input terminal portions 43 and 44 is preferably 5 μm or more and 50 μm or less. The second slit 25 is not provided in the input terminal portions 43 and 44.

[0061] The input terminal portions 43, 44, the output terminal portions 41, 42, and the die pad portion 35 can be configured by Cu foil provided on the surface of the polyimide substrate 21 and a plating layer such as Ni or Au stacked thereon. In addition, when viewed from above, the input terminal portions 43, 44, the output terminal portions 41, 42, and the die pad portion 35 are separated and insulated from each other on the polyimide substrate 21.

[0062] The input terminal portion 43 is electrically connected to a pad 81 f of a cathode of the light emitting element 32 via a bonding wire BW1 .

[0063] The input terminal portion 44 is electrically connected to the pad 81 e of the anode of the light emitting element 32 via the bonding wire BW2 .

[0064] The gates and sources of the light receiving element 31 and the MOSFETs 33 and 34 are electrically connected via bonding wires BW3, BW4, BW6, and BW7. The pads 81a, 81b, 81c, and 81d of the light receiving element are electrically connected to the pads 81g, 81h, 81k, and 81l of the MOSFETs 33 and 34 via bonding wires BW3, BW4, BW6, and BW7.

[0065] The MOSFET 33 (source) and the MOSFET 34 (source) are electrically connected via a bonding wire BW5 that connects the pad 81 i and the pad 81 j .

[0066] From the perspective of obtaining a semiconductor device 200 with high-frequency pass characteristics, it is preferred that the first conductive adhesive 13 and the light receiving element 31 do not overlap in a direction perpendicular to the surface of the mounting substrate 10 facing the semiconductor element 20, and the second conductive adhesive 14 and the light receiving element 31 do not overlap in a direction perpendicular to the surface of the mounting substrate 10 facing the semiconductor element 20.

[0067] Preferably, the length of the first slit 24 is shorter than the distance from the side surface of the semiconductor element 20 where the opening of the first slit 24 of the MOSFET 33, 34 is located to the side surface opposite to the side surface of the semiconductor element 20 where the opening of the first slit 24 of the MOSFET 33, 34 is located. If the first slit 24 is too long, the first conductive adhesive 13 is also likely to be located under the light emitting element 32 and the light receiving element 31, which may adversely affect the high frequency pass characteristics.

[0068] Preferably, the first slit 24 overlaps with the pads 81g, 81h, 81k, 81l of the MOSFETs 33 and 34 in a direction perpendicular to the surface of the mounting substrate 10 facing the semiconductor element 20, and the first slit 24 overlaps with the pads 81g, 81h, 81k, 81l of the MOSFETs 33 and 34, thereby shortening the wiring distance between the pads 81g, 81h, 81k, 81l of the MOSFETs 33 and 34 and the first electrode pad 11 of the mounting substrate 10. From the above viewpoint, it is preferred that the length of the first slit 24 is greater than or equal to the distance from the side of the photo relay 20 to the pads 81i, 81j on the opening side of the first slit 24 of the MOSFETs 33 and 34, and less than or equal to the distance from the side of the photo relay 20 to the pads 81g, 81h, 81k, 81l on the opposite side of the opening side of the first slit 24 of the MOSFETs 33 and 34.

[0069] Preferably, the second slit 25 overlaps with the connection surface of the bonding wires BW1 and BW2 of the input terminal portions 43 and 44 in a direction perpendicular to the surface of the mounting substrate 10 facing the semiconductor element 20, and the second slit 25 overlaps with the connection surface of the bonding wires BW1 and BW2 of the input terminal portions 43 and 44, thereby shortening the wiring distance between the input terminal portions 43 and 44 and the second electrode pad 12 of the mounting substrate 10.

[0070] Fig.10 It is a structural diagram of a photorelay according to a second embodiment.

[0071] The light receiving element 31 may further include a control circuit 31a. The control circuit 31a is connected to the first electrode and the second electrode of the photodiode array 31b, respectively. If such a structure is adopted, a voltage can be supplied to the gate of each of the source-commonly connected MOSFETs 33. In addition, the control circuit 31a includes a resistor, etc., and when the MOSFET 33 is turned from on to off, it can be discharged to shorten the fall time.

[0072] MOSFETs 33 and 34 can be, for example, n-channel enhancement type. Fig.10 In the embodiment, the gate G of the MOSFET 33 is connected to the anode of the photodiode 31 b , the source S is connected to the cathode of the photodiode 31 b , and the drain D is connected to the output terminal 41 , 42 .

[0073] When the optical signal is on, both MOSFETs 33 and 34 are turned on and connected to an external circuit including a power supply and a load via output terminals 41 and 42. On the other hand, when the optical signal is off, both MOSFETs 33 and 34 are turned off and disconnected from the external circuit. If the source is connected in common, linear output can be achieved, and switching of high-frequency signals becomes easy.

[0074] The two MOSFETs 33 and 34 are connected to the source and common, and when turned on, a high-frequency signal is supplied to the load. For example, if the number of bonding wires connected between the two source electrodes S is increased to two or more, the source inductance can be reduced. In addition, if the two or more bonding wires are not parallel, the source inductance can be further reduced. Furthermore, if the diameter of the bonding wire on the MOSFET 33 and 34 side is larger than the diameter of the bonding wire on the light emitting element 32 side, the wiring inductance can be reduced. As a result, the transmission loss can be reduced.

[0075] The semiconductor device using the photorelay 20 of the embodiment can reduce the transmission loss of high-frequency signals above 20 GHz and has high reliability. Therefore, the high-frequency characteristics of semiconductor devices including ultra-high-speed DRAM of the next-generation standard can be measured with high accuracy and high speed.

[0076] These photorelays can be widely used in semiconductor devices such as industrial equipment including semiconductor testers for inspecting ICs and the like.

[0077] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: A mounting substrate is provided with a first electrode pad and a second electrode pad; A semiconductor element is provided on the mounting substrate, comprising: a supporting substrate; a third electrode pad provided on a surface of the supporting substrate facing the mounting substrate; and a fourth electrode pad provided on a surface of the supporting substrate facing the mounting substrate, wherein a first slit is provided on the supporting substrate and the third electrode pad, and a second slit is provided on the supporting substrate and the fourth electrode pad; a first conductive adhesive connecting the first electrode pad and the third electrode pad; and A second conductive adhesive connects the second electrode pad and the fourth electrode pad, The shape of the first slit provided in the support substrate is the same as the shape of the first slit provided in the third electrode pad. The shape of the second slit provided in the support substrate is the same as the shape of the second slit provided in the fourth electrode pad.

2. The semiconductor device according to claim 1, wherein The first slit is provided from the outer periphery of the semiconductor element toward the center of the support substrate. The second slit is provided from the outer periphery of the semiconductor element toward the center of the support substrate.

3. The semiconductor device according to claim 1 or 2, wherein: When the first electrode pad and the semiconductor element are overlapped in a direction perpendicular to the surface of the mounting substrate facing the semiconductor element, a portion of the first electrode pad protrudes outward from an outer periphery of the semiconductor element in the surface direction of the mounting substrate, The first conductive adhesive has a surface inclined from the third electrode pad toward the outer periphery of the first electrode pad, When the second electrode pad and the semiconductor element are overlapped in a direction perpendicular to the surface of the mounting substrate facing the semiconductor element, a portion of the second electrode pad protrudes outward from the outer periphery of the semiconductor element in the surface direction of the mounting substrate, The second conductive adhesive has a surface inclined from the fourth electrode pad toward an outer periphery of the second electrode pad.

4. The semiconductor device according to claim 1 or 2, wherein: The length of the first slit is at least 4 times the height of the first slit, The length of the first slit is at least 4 times the width of the first slit, The length of the second slit is at least 4 times the height of the second slit, The length of the second slit is greater than or equal to four times the width of the second slit.

5. The semiconductor device according to claim 1 or 2, wherein: The first slit and the second slit are not open in the center direction of the support substrate.

6. The semiconductor device according to claim 1 or 2, wherein: The semiconductor element is a photorelay including a light emitting element, a light receiving element, a switch element, and a first bonding wire connecting the switch element and the light receiving element. The third electrode pad is connected to the drain electrode of the switching element, The first slit is provided directly below a connection portion of the first bonding wire connected to the switching element.

7. The semiconductor device according to claim 6, wherein: The length of the first slit is shorter than a distance from a side surface of the semiconductor element where the opening of the first slit of the switching element is located to a side surface of the semiconductor element opposite to the side surface where the opening of the first slit of the switching element is located.

8. The semiconductor device according to claim 6, wherein: The first conductive adhesive and the light receiving element do not overlap in a direction perpendicular to a surface of the mounting substrate facing the semiconductor element. The second conductive adhesive and the light receiving element do not overlap in a direction perpendicular to a surface of the mounting substrate facing the semiconductor element.

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