Integrated circuit, chip and electronic device

Abstract

Embodiments of the present application provide an integrated circuit, chip, and electronic device, relating to the field of microelectronic circuit technology, and capable of improving integrated circuit failures caused by electrostatic discharge. The integrated circuit includes a substrate and a transistor disposed on the substrate; the gate of the transistor is coupled to a first terminal of a switching device, and the second terminal of the switching device is coupled to a ground terminal; the switching device is configured to be in an on state or an off state under the control of a control signal received at a control terminal; in the on state, the switching device transmits the electrostatic voltage of the gate of the transistor to the ground terminal; or, in the off state, the switching device disconnects the gate of the transistor from the ground terminal.

Description

Technical Field

[0001] The present application relates to the field of microelectronic circuit technology, and in particular to an integrated circuit, a chip, and an electronic device. Background Art

[0002] Currently, electrostatic discharge (ESD) is often generated during the assembly and processing of integrated circuits (for example, during the process of attaching the chip to the packaging substrate). ESD is generally harmful and cannot be eliminated, and ESD may damage the integrated circuit. For example, the signal electrodes (electrode pads, pins, etc.) of the integrated circuit generate static electricity during the assembly and processing. The ESD current may be discharged from the transistors coupled to the signal electrodes in the integrated circuit, causing damage to the transistors coupled to the signal electrodes in the integrated circuit, and further causing the integrated circuit to fail. In particular, for high electron mobility transistors (HEMTs), which use heteroepitaxial growth to form the channel layer on a substrate using a Group III nitride material different from the substrate material, the gate leakage current of such transistors is relatively large during operation. When an ESD event occurs on the gate, the physical structure of the gate that withstands the ESD pulse is almost entirely the gate dielectric layer and the barrier layer. When the current passing through exceeds a certain value, the gate dielectric layer will be broken down, causing device failure. Summary of the Invention

[0003] Embodiments of the present application provide an integrated circuit, a chip, and an electronic device that can improve integrated circuit failure caused by electrostatic discharge.

[0004] To achieve the above objectives, this application adopts the following technical solutions:

[0005] In the first aspect, an integrated circuit is provided. The integrated circuit may be in the form of a bare core, a bare chip or a die. The integrated circuit is characterized in that it comprises: a substrate and a transistor arranged on the substrate; the gate of the transistor is coupled to the first end of the switching device, and the second end of the switching device is coupled to the ground end; wherein the switching device is configured to be in an on state or an off state under the control of a control signal received at the control end; the switching device transmits the electrostatic voltage of the gate of the transistor to the ground end in the on state; or, the switching device disconnects the gate of the transistor from the ground end in the off state. In this way, in the process of attaching the integrated circuit to the packaging substrate, by configuring the switching device on the integrated circuit to be in the on state, the electrostatic voltage V ESDTransmitted to the ground terminal GND; can effectively prevent electrostatic discharge from breaking down the transistor and causing failure of the integrated circuit. In addition, after the integrated circuit is mounted on the packaging substrate, by configuring the switching device on the integrated circuit to the off state, it is ensured that the gate G of the transistor and the ground terminal GND are disconnected, thereby ensuring the normal function of the transistor during operation. In addition, during the on-wafer screening stage before the integrated circuit is mounted on the package substrate, a control signal is applied to the control electrode Pm to put the switching device in the off state, so that the gate G of the transistor and the ground terminal GND are in an open circuit state, and a test signal can be applied to the gate electrode connected to the gate G of the transistor, and the on-wafer screening of the transistor is achieved by detecting the output signal of the drain D; during the mounting process of the integrated circuit on the package substrate, a control signal is applied to the control electrode to put the switching device in the on state (or the other state of the switching device is the normally on state. It can be understood that when one state of the switching device, such as HEMT, is the normally on state, applying a control signal to its gate can change the state of the HEMT to the off state. Then, when the switching device is in the normally on state, no control signal can be applied to its gate, or the control signal is 0), so that the gate G of the transistor and the ground terminal GND are short-circuited through the switching device, and the electrostatic voltage V of the gate G of the transistor is reduced through the switching device. ESD Transmitted to the ground terminal GND; after the integrated circuit is mounted on the packaging substrate, in order to ensure the normal operation of the transistor, the gate G of the transistor and the ground terminal GND need to be disconnected, so the switching device is disconnected by the control signal to achieve the disconnection of the gate G of the transistor and the ground terminal GND.

[0006] In a possible implementation manner, the control terminal of the switching device is coupled to a control electrode, and the control electrode is configured to receive the control signal.

[0007] In one possible implementation, the gate of the transistor is further coupled to a gate electrode, and the gate of the transistor is electrically connected to the gate electrode via a via. Since the gate of the transistor is usually covered inside the protective layer, in order to connect the gate of the transistor to other components such as a package substrate, it is usually necessary to make an electrode (gate electrode) outside the protective layer to connect to the gate of the transistor. When the integrated circuit is connected to other components such as a package substrate via a patch method, the electrode (gate electrode) outside the protective layer is connected to the electrode on the package substrate, thereby enabling the PCB to provide signals to the integrated circuit or transmit signals output by the integrated circuit to the PCB.

[0008] In one possible implementation, the switching device includes a depletion-mode HEMT, wherein a first active electrode of the depletion-mode HEMT is coupled to the ground terminal, a second active electrode of the depletion-mode HEMT is coupled to the gate of the transistor, and the gate of the depletion-mode HEMT is coupled to a control electrode, wherein the control electrode and the gate of the depletion-mode HEMT are electrically connected through a via. The depletion-mode HEMT is in an on state, or the gate of the depletion-mode HEMT receives a first control voltage transmitted by the control electrode, and the depletion-mode HEMT is in an off state under the control of the first control voltage. The source S of the depletion-mode HEMT can be understood as the first active electrode, and the drain D of the depletion-mode HEMT can be understood as the second active electrode. In one embodiment, the source S of the depletion-mode HEMT is coupled to the first end of an electrostatic discharge wire, and the drain D of the depletion-mode HEMT is coupled to the gate of the transistor. In another embodiment, the drain D of the depletion-mode HEMT can be coupled to the first end of the electrostatic discharge wire, and the source S of the depletion-mode HEMT is coupled to the gate of the transistor. In addition, during the bonding process of the integrated circuit to the packaging substrate, since the above-mentioned electrodes (gate electrode and control electrode) are encapsulated, it is impossible to apply a control signal to the control electrode through a probe during this process. In addition, if a control signal can be applied to the control electrode through a probe, ESD will also be directly released through the probe, and there will be no electrostatic discharge problem. Therefore, the switching device can be a depletion-type HEMT. Since the depletion-type HEMT is in a normally-on state when no signal is applied to the gate (or the control signal is 0), for the depletion-type HEMT, there is sufficient two-dimensional electron gas concentration when no voltage is applied to the gate, so The source S and drain D of this depletion-mode HEMT are in a normally-on state. To turn off the depletion-mode HEMT, a negative voltage must be applied to the gate G of the depletion-mode HEMT. When the negative voltage provided by the gate G of the depletion-mode HEMT is less than the threshold voltage, the depletion-mode HEMT is turned off. The negative voltage on the gate G of the depletion-mode HEMT generates an electric field opposite to the built-in electric field, which reduces the band bending at the heterojunction interface of the barrier layer / channel layer, reduces the depth of the triangular potential well, and thus reduces the concentration of the two-dimensional electron gas. Therefore, during the bonding process of the integrated circuit to the package substrate, the electrostatic voltage V on the gate G of the transistor can be reduced by the normally-on depletion-mode HEMT. ESD Transmitted to the ground terminal GND.

[0009] In a possible implementation, the transistor and / or the switching device includes a fin-gate transistor.

[0010] In a possible implementation, the channel layer of the transistor includes Group III nitride.

[0011] In a possible implementation manner, a channel layer of the transistor includes a material different from that of the substrate, and the channel layer is located on the substrate.

[0012] In a possible implementation, the channel layer and the barrier layer of the depletion-mode HEMT include group III nitride.

[0013] In one possible implementation, the thickness of the gate dielectric layer of the depletion-mode HEMT is greater than the thickness of the gate dielectric layer of the transistor. During the bonding process of the integrated circuit to the packaging substrate, the control electrode Pm also accumulates electrostatic charge, so the gate of the depletion-mode HEMT also faces ESD issues. To reduce the risk of breakdown of the gate dielectric layer and barrier layer of the depletion-mode HEMT, the gate dielectric layer of the depletion-mode HEMT is set to be sufficiently thick. For example, to withstand 100V ESD, the gate dielectric layer thickness is approximately 200nm. When the gate dielectric layer of the depletion-mode HEMT and the gate dielectric layer of the transistor are made of the same material, the thickness of the gate dielectric layer of the depletion-mode HEMT is greater than the thickness of the gate dielectric layer of the transistor.

[0014] In one possible implementation, the thickness of the barrier layer of the depletion-mode HEMT is less than that of the barrier layer of the transistor. When the gate dielectric layer is thickened, the gate capacitance decreases, weakening the ability to deplete electrons. Therefore, a more negative voltage is required to completely deplete the electrons beneath the channel layer, which is clearly unacceptable. To reduce the voltage required to deplete electrons, another approach is to reduce the total number of electrons, thereby reducing the voltage required to deplete electrons. The most effective way to reduce the number of electrons is to reduce the thickness of the barrier layer. Therefore, when the barrier layer of the depletion-mode HEMT and the barrier layer of the transistor are made of the same material, the thickness of the barrier layer of the depletion-mode HEMT is less than that of the barrier layer of the transistor.

[0015] In a possible implementation, the thickness of the barrier layer of the depletion-mode HEMT is 0.1 nm-100 nm.

[0016] In a possible implementation, the thickness of the gate dielectric layer of the depletion-mode HEMT is 0.1 nm-200 nm.

[0017] In a possible implementation, the threshold voltage of the depletion-mode HEMT is -60V to -0.1V.

[0018] In a possible implementation, the integrated circuit is a monolithic microwave integrated circuit (MMIC).

[0019] In a second aspect, a chip is provided, comprising the above-mentioned integrated circuit and a packaging substrate, wherein the integrated circuit is coupled to the packaging substrate.

[0020] According to a third aspect, an electronic device is provided, comprising a printed circuit board and the chip as described above; the chip is coupled to the printed circuit board.

[0021] In a fourth aspect, an electrostatic protection method is provided, which is applied to the integrated circuit provided in the first aspect; comprising: in the process of attaching the integrated circuit to the packaging substrate, controlling the switching device to be in the on state, and conducting the electrostatic voltage of the gate of the transistor to the ground terminal.

[0022] In a possible implementation, before attaching the integrated circuit to a packaging substrate, the method further includes: controlling the switch device to be in an off state, and outputting a test signal to the gate of the transistor.

[0023] In a possible implementation, after the integrated circuit is mounted on a packaging substrate, the method includes: controlling the switch device to be in an off state.

[0024] Among them, the technical effects brought about by any possible implementation method of the second aspect, the third aspect, and the fourth aspect can refer to the technical effects brought about by the different implementation methods of the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A A schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0026] Figure 1B A schematic structural diagram of an electronic device provided in another embodiment of the present application;

[0027] Figure 1C A schematic structural diagram of an electronic device provided in yet another embodiment of the present application;

[0028] Figure 2 A schematic structural diagram of a base station provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application;

[0031] Figure 5 A schematic structural diagram of an integrated circuit provided in another embodiment of the present application;

[0032] Figure 6 A schematic structural diagram of an integrated circuit provided in yet another embodiment of the present application;

[0033] Figure 7 A schematic diagram of the principle of ESD problem of a HEMT provided in an embodiment of the present application;

[0034] Figure 8A schematic structural diagram of an integrated circuit provided in yet another embodiment of the present application;

[0035] Figure 9 A schematic structural diagram of an integrated circuit provided in another embodiment of the present application;

[0036] Figure 10 A schematic structural diagram of an integrated circuit provided in yet another embodiment of the present application;

[0037] Figure 11 A schematic structural diagram of an integrated circuit provided in yet another embodiment of the present application;

[0038] Figure 12 A schematic diagram of a process flow of an integrated circuit provided in an embodiment of the present application;

[0039] Figure 13 A schematic structural diagram of an integrated circuit provided in another embodiment of the present application;

[0040] Figure 14 A schematic structural diagram of an integrated circuit provided in yet another embodiment of the present application;

[0041] Figure 15 A schematic structural diagram of an integrated circuit provided in yet another embodiment of the present application;

[0042] Figure 16 A schematic structural diagram of an integrated circuit provided in another embodiment of the present application;

[0043] Figure 17 A schematic structural diagram of an integrated circuit provided in yet another embodiment of the present application;

[0044] Figure 18 A schematic structural diagram of an integrated circuit provided in yet another embodiment of the present application;

[0045] Figure 19 A schematic structural diagram of a HEMT provided in an embodiment of the present application;

[0046] Figure 20 A schematic structural diagram of a HEMT provided in an embodiment of the present application;

[0047] Figure 21 A schematic structural diagram of a HEMT provided in another embodiment of the present application;

[0048] Figure 22 A schematic structural diagram of a HEMT provided in another embodiment of the present application;

[0049] Figure 23A schematic diagram of a relationship curve between barrier layer thickness, gate dielectric thickness, gate capacitance, and gate voltage of a HEMT provided in an embodiment of the present application;

[0050] Figure 24 A schematic structural diagram of an integrated circuit provided in accordance with another embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0052] Unless otherwise defined, all scientific and technological terms used herein have the same meaning as those known to those of ordinary skill in the art. In this application, "at least one" refers to one or more, and "a plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, wherein A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following items" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit quantity and order.

[0053] In addition, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0054] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0055] The integrated circuits and chips provided in the embodiments of the present application can be applied to electronic devices, which are different types of terminals such as mobile phones, tablet computers, personal computers (PCs), personal digital assistants (PDAs), smart watches, netbooks, wearable electronic devices, augmented reality (AR) devices, virtual reality (VR) devices, vehicle-mounted devices, smart cars, smart speakers, robots, smart glasses, etc.; the electronic devices can also be network devices such as base stations. The electronic devices can also be devices such as chips used in the above-mentioned electronic devices. The electronic devices can also include a printed circuit board, and the above-mentioned chip is arranged on the printed circuit board. The chip is encapsulated with an integrated circuit arranged on a packaging substrate, and the integrated circuit can be connected to the packaging substrate in a patch manner. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic devices.

[0056] Take mobile phones as an example. Figures 1A to 1C 1 shows a schematic structural diagram of an electronic device 100, wherein: Figure 1A A top view of electronic device 100 is shown in accordance with the described embodiment. Figure 1B A bottom view of electronic device 100 is shown for the described embodiment. Figure 1C FIG. 1 shows a top view of the electronic device 100 with its back cover opened, illustrating a specific configuration of various internal components according to the described embodiment. Figure 1C The dotted arrow in the figure indicates the direction in which the rear cover is opened. It is understood that the structure shown in this embodiment does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently.

[0057] like Figure 1A and Figure 1BAs shown, the electronic device 100 may include a housing 100A, which may include a front cover 101, a back cover 103, and a frame 102. The front cover 101 and the back cover 103 are arranged opposite each other, and the frame 102 surrounds the front cover 101 and the back cover 103 and connects the front cover 101 and the back cover 103 together. The front cover 101 may be a glass cover plate, and the display 194 is arranged below the front cover 101. The electronic device 100 may be provided with input / output components around the periphery of the housing 100A. For example, a hole 105A for a front camera and a hole 106 for a receiver may be provided at the top of the front cover 101. A button 190 may be provided on one edge of the frame 102, and a hole 107 for a microphone, a hole 108 for a speaker, and a hole 109 for a USB port may be provided at the bottom edge of the frame 102. A hole 105B for a rear camera, for example, may be provided at the top of the back cover 103.

[0058] The housing 100A may have a cavity 104 inside, in which the internal components are encapsulated. Figure 1CAs shown, internal components can be housed in the cavity 104, and the internal components may include printed circuit boards (PCBs) 110, a speaker 170A for converting audio electrical signals into sound signals, a receiver 170B for converting audio electrical signals into sound signals, a microphone 170C for converting sound signals into electrical signals, a USB interface 130, a front camera 193A, a rear camera 193B, and a motor 191 for generating vibration prompts and other components. The printed circuit board 110 may be provided with a processor 120, a power management integrated circuit (PMIC) 140, at least one power amplifier (in one embodiment, including a power amplifier (PA) 152A, a power amplifier PA 152B, a power amplifier PA 152C, and a power amplifier PA 152D, where different power amplifiers PA support different frequency bands and are used to amplify transmission signals of different frequency bands. For example, the power amplifier PA 152A and the power amplifier PA 152B can be used to amplify transmission signals in a first bandwidth range, and the power amplifier PA 152C and the power amplifier PA 152D can be used to amplify transmission signals in a second bandwidth range), and at least one envelope tracking modulator (ETM) ETM for powering the power amplifier (in one embodiment, including an ET modulator ETM 151A and an ET modulator ETM 151B, where different ET modulators ETM support different bandwidths. For example, the ET modulator ETM 151A is a power amplifier PA 152A and a power amplifier PA 152D. 152B is powered, and the envelope tracking modulator ETM151B powers the power amplifier PA 152C and the power amplifier PA 152D), a switch 153, and an antenna circuit 154. In addition, the printed circuit board 110 may also include components such as a filter, a low-noise amplifier, an audio codec, an internal memory, a sensor, an inductor, and a capacitor. To clearly illustrate this embodiment, the filter, low-noise amplifier, audio codec, internal memory, sensor, inductor, and capacitor are not shown. Figure 1C . The components on the printed circuit board 110 are arranged tightly so that all the components can be placed in a limited space. The arrangement of the components on the printed circuit board 110 is not limited. In some embodiments, the components on the printed circuit board 110 can be arranged on one side of the printed circuit board 110 (for example, the side facing the back cover 102). In some embodiments, the components on the printed circuit board 110 can be arranged on both sides of the printed circuit board 110 (for example, respectively on the side facing the back cover 102 and on the side facing the front cover 101).

[0059] The processor 120 may include one or more processing units, for example, an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a neural-network processing unit (NPU), a controller, a video codec, a digital signal processor (DSP), a baseband, and / or a radio frequency circuit. The controller may generate an operation control signal based on the instruction opcode and timing signal to control instruction fetching and execution.

[0060] Processor 120 may be provided with a memory for storing instructions and data. In some embodiments, the memory in processor 120 includes a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 120. If processor 120 needs to use the same instruction or data again, it can directly retrieve it from the memory. This avoids duplicate accesses, reduces processor 120 latency, and thus improves system efficiency.

[0061] The processor 120 may frequency modulate the signal according to a mobile communication technology or a wireless communication technology. Mobile communication technologies may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), and emerging wireless communication technologies (also known as fifth generation mobile communication technologies, English: 5th generation mobile networks or 5th generation wireless systems, 5th-Generation, 5th-Generation New Radio, referred to as 5G, 5G technology or 5G NR). Wireless communication technologies may include wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), nearfield communication (NFC), infrared technology (IR), etc.

[0062] The processor 120 may also include at least one baseband and at least one radio frequency circuit. The baseband is used to synthesize the baseband signal to be transmitted and / or to decode the received baseband signal. Specifically, during transmission, the baseband encodes the voice or other data signal into the baseband signal (baseband code) to be transmitted; during reception, it decodes the received baseband signal (baseband code) into the voice or other data signal. The baseband may include components such as an encoder, a decoder, and a baseband processor. The encoder is used to synthesize the baseband signal to be transmitted, and the decoder is used to decode the received baseband signal. The baseband processor may be a microprocessor (MCU), which can be used to control the encoder and decoder. For example, the baseband processor can be used to complete the scheduling of encoding and decoding, communication between the encoder and decoder, and peripheral driving (it can enable components outside the baseband by sending an enable signal to them), etc. The RF circuit is used to process the baseband signal to form a transmit (TX) signal and pass the transmit signal to the power amplifier PA for amplification; or / and, the RF circuit is used to process the receive (RX) signal to form a baseband signal and send the formed baseband signal to the baseband for decoding. In some embodiments, each baseband corresponds to a RF circuit to frequency modulate the signal according to one or more communication technologies. For example, the first baseband and the first RF circuit frequency modulate the signal according to 5G technology, the second baseband and the second RF circuit frequency modulate the signal according to 4G technology, the third baseband and the third RF circuit frequency modulate the signal according to Wi-Fi technology, the fourth baseband and the fourth RF circuit frequency modulate the signal according to Bluetooth technology, and so on. Alternatively, the first baseband and the first RF circuit can frequency modulate the signal according to 4G technology and 5G technology at the same time, the second baseband and the second RF circuit frequency modulate the signal according to Wi-Fi technology, and so on. In some embodiments, one baseband can also correspond to multiple RF circuits to improve integration.

[0063] In some embodiments, the baseband and RF circuits may be integrated into a single integrated circuit with other components of the processor 120. In some embodiments, the baseband and RF circuits may each be a separate device independent of the processor 120. In some embodiments, a baseband and a RF circuit may be integrated into a separate device independent of the processor 120.

[0064] In the processor 120 , different processing units may be independent devices or integrated into one or more integrated circuits.

[0065] Antenna circuit 154 is used to transmit and receive electromagnetic wave signals (radio frequency signals). Antenna circuit 154 may include multiple antennas or multiple groups of antennas (multiple groups of antennas may include two or more antennas), each of which may be used to cover a single or multiple communication frequency bands. The multiple antennas may be multi-band antennas, array antennas, or on-chip antennas.

[0066] The processor 120 is coupled to the antenna circuit 154 to implement various functions associated with transmitting and receiving radio frequency signals. For example, when the electronic device 100 transmits a signal, the baseband combines the data to be transmitted (digital signal) into a baseband signal to be transmitted. The baseband signal is converted by the radio frequency circuit into a transmit signal (radio frequency signal). The transmit signal is amplified by the power amplifier. The amplified output signal of the power amplifier is transmitted to the switch 153 and transmitted through the antenna circuit 154. The path by which the transmit signal is sent from the processor 120 to the switch 153 is the transmit link (or transmit path). When the electronic device 100 needs to receive a signal, the antenna circuit 154 sends the received signal (radio frequency signal) to the switch 153. The switch 153 sends the radio frequency signal to the radio frequency circuit. The radio frequency circuit processes the radio frequency signal into a baseband signal. The radio frequency circuit converts the processed baseband signal into data and sends it to the corresponding application processor. The path by which the radio frequency signal is sent from the switch 153 to the processor 120 is the receive link (or receive path).

[0067] The switch 153 can be configured to selectively electrically connect the antenna circuit 154 to the transmit link or the receive link. In some embodiments, the switch 153 can include multiple switches. The switch 153 can also be configured to provide additional functions, including filtering and / or duplexing signals.

[0068] The SIM card interface 195 is used to connect a SIM card. A SIM card can be connected to and disconnected from the electronic device 100 by inserting or removing it from the SIM card interface 195. The electronic device 100 may support one or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 may support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 simultaneously. The multiple cards can be of the same or different types. Each SIM card can support one or more communication standards, each with a specified frequency band and a different maximum bandwidth. The SIM card interface 195 is also compatible with different types of SIM cards. The SIM card interface 195 is also compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to implement functions such as calls and data communications. In some embodiments, the electronic device 100 uses an eSIM, or embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from it.

[0069] The PMIC 140 is used to manage the power supply in the electronic device 100. For example, the PMIC 140 may include a charging management circuit and a power management circuit. The charging management circuit is used to receive charging input from a charger. For example, in some wired charging embodiments, the charging management circuit may receive charging input from a wired charger via the USB interface 130. The power management circuit is used to receive input from the battery 142 and / or the charging management circuit to power components such as the processor 120, the display 194, the front camera 193A, the rear camera 193B, and the motor 191. In other embodiments, the charging management circuit and the power management circuit may also be provided in the processor 120. In other embodiments, the charging management circuit and the power management circuit may also be provided in different devices.

[0070] In another example, the electronic device provided in the embodiment of the present application takes a 5G base station as an example. The 5G base station can be divided into different architectures such as baseband processing unit (BBU)-active antenna unit (AAU), central unit-distribute unit (CU-DU)-AAU, BBU-remote radio unit (RRU)-antenna, CU-DU-RRU-Antenna, and integrated 5G base station (5G node basestation, gNB). Taking the base station with BBU-RRU architecture as an example, refer to Figure 2As shown, the base station includes a BBU 21, an RRU 22, and an antenna 23; wherein the BBU 21 and the RRU 22 are connected by optical fiber, and the interface between the two is based on the open CPRI (common public radio interface) and the OBSAI (open base station architecture initiative). The BBU 21 processes the generated baseband signal through the RRU 22 and sends it to the antenna 23 for transmission. The RRU 22 includes a digital intermediate frequency module 221, a transceiver module 222, a power amplifier 223 (power amplifier, PA), and a filter 224. The digital intermediate frequency module 221 is used for modulation and demodulation, digital up and down conversion, D / A conversion (digital to analog converter, digital to analog conversion), etc. of the baseband signal transmitted by the optical fiber to form an intermediate frequency signal; the transceiver module 222 completes the conversion of the intermediate frequency signal to the radio frequency signal; the power amplifier 223 is used to amplify the low-power radio frequency signal; the filter 224 is used to filter the radio frequency signal and then transmit the radio frequency signal through the antenna 23.

[0071] The technologies involved in the following embodiments can all be implemented in the electronic devices described above. In the following embodiments, components or signals with the same names as those in the electronic devices described above can be configured as the same components or signals in the electronic devices described above. The following examples illustrate the integrated circuits, chips, and electronic devices provided in the embodiments of this application.

[0072] In combination with the above description, some components in the electronic device (such as one or more of a processor, a power management integrated circuit, a PA, an ETM, a filter, a low noise amplifier, an audio codec, and an internal memory) can be provided on the printed circuit board 110 in the form of a chip and coupled to the printed circuit board 110, for example, they can be connected to the printed circuit board 110 by pin (terminal pin) welding or pad (electrode pad) mounting. Another part of the components (such as sensors, inductors, capacitors) are connected to the printed circuit board 110 in the form of independent components through pin plugging (for example, board-to-board connector (BTB)) or welding. Figure 3As shown, a chip is provided, which includes an integrated circuit 30 and a packaging substrate 50. The integrated circuit 30 is in the form of a bare core, a bare chip or a die. The integrated circuit 30 is coupled to the packaging substrate 50. It should be noted that the functional circuit inside the integrated circuit 30 is coupled to the electrodes (pins, or pads) on the packaging substrate 50 through electrodes (pins, or pads). For example, the pins P of the integrated circuit 30 are soldered to the electrodes (pins, or pads) on the packaging substrate 50 through solder balls, wherein metal wires (not shown) are provided on the packaging substrate 50, and these metal wires connect the pins P of the integrated circuit 30 to the pins 60 of the external chip. In this way, when the chip is connected to the printed circuit board 110 through the pins 60 of the chip, the connection between the integrated circuit 30 and the printed circuit board 110 is achieved. In addition, the integrated circuit 30 is also filled with a packaging material 40, such as an insulating material such as resin or ceramic.

[0073] Specifically, the integrated circuit 30 provided in the embodiment of the present application may include an integrated circuit 30 for use in Figure 1A-Figure 1C or Figure 2 The transistor in the PA of the electronic device provided. Of course, the specific application scenario is not limited to the above Figure 1A-Figure 1C The mobile phone shown, Figure 2 The base station shown, it can be understood that any of the above-mentioned electronic devices that need to use transistors to process signals belong to the application scenarios of the embodiments of the present application. The integrated circuit can be formed by connecting one or more transistors made on a substrate. Exemplarily, when used to implement a radio frequency function in an electronic device, the integrated circuit can be a monolithic microwave integrated circuit (MMIC) or a radiofrequency integrated circuit (RFIC). It can be understood that the MMIC can be integrated with the above-mentioned filters, low-noise amplifiers, and PAs at the same time, and in some examples can also be integrated with mixers, frequency multipliers, phased array units, and the like.

[0074] like Figure 4 As shown, the integrated circuit 30 mainly includes a substrate 31 and a transistor 32 arranged on the substrate 31. In order to prevent the electrostatic discharge from breaking down the transistor 32 and causing the integrated circuit 30 to fail during the process of attaching the integrated circuit 30 to the packaging substrate, usually, a Figure 4 As shown, the gate of the transistor 32 is usually connected to one or more electrostatic discharge (ESD) protection units, through which the electrostatic voltage V accumulated on the gate of the transistor 32 is ESD Transmitted to the ground terminal GND.

[0075] In the embodiments of this application, the specific combination Figure 5 、 Figure 6 As shown, the integrated circuit 30 mainly includes a substrate 31 and a transistor 32 disposed on the substrate 31. In some embodiments of the present application, the gate (gate, G) of the transistor 32 is coupled to a first terminal of a switch device 33, and the second terminal of the switch device 33 is coupled to a ground terminal GND; wherein, the switch device 33 is configured to be in an on state or an off state under the control of a control signal received at a control terminal; Figure 5 As shown, the switch device 33 is in the on state and the electrostatic voltage V ESD Transmitted to the ground terminal GND; or, as Figure 6 As shown, the switch device 33 disconnects the gate G of the transistor 32 from the ground terminal GND in the off state. It should be noted that the source S of the transistor 32 is directly or indirectly connected to the ground terminal GND. For example, in some examples, the source S of the transistor 32 is connected to the ground terminal GND through some intermediate devices (such as resistors, inductors, diodes, etc.). Of course, in order to reduce the parasitic parameters (such as capacitance, capacitance or inductance, etc.) between the transistor 32 and the ground terminal, the source S of the transistor 32 is usually directly connected to the ground terminal GND. Figure 5 and Figure 6 The source S of the transistor 32 can be understood as a first active electrode, and the drain D of the transistor 32 can be understood as a second active electrode. In one embodiment, the source S of the transistor 32 is coupled to the ground terminal, and the drain D of the transistor 32 is coupled to the working power supply; in another embodiment, the drain D of the transistor 32 can be coupled to the ground terminal, and the source S of the transistor 32 is coupled to the working power supply.

[0076] Thus, in the process of attaching the integrated circuit 30 to the package substrate, the electrostatic voltage V ESD Transmitted to the ground terminal GND; it can effectively prevent electrostatic discharge from breaking down the transistor 32 and causing failure of the integrated circuit. In addition, after the integrated circuit 30 is mounted on the packaging substrate, the switching device 33 on the integrated circuit 30 is configured to be in the off state, thereby ensuring that the gate G of the transistor 32 and the ground terminal GND are disconnected, thereby ensuring the normal function of the transistor 32 during operation.

[0077] In particular, transistors based on heteroepitaxial channel layers on substrates have serious ESD problems. Among them, the channel layer of this type of transistor includes a material different from the substrate, and the channel layer is located on the substrate, for example, epitaxially on the substrate. Take the high electron mobility transistor (HEMT) using group III nitride as an example. Among them, HEMTs using group III nitrides have been widely used in power amplifiers of base stations. However, compared with base stations, the battery power supply voltage of the terminal determines that the group III nitride HEMT can only operate at low voltage, which places high demands on the current density of the HEMT. Combined with Figure 7 As shown, high current density is used to compensate for the reduced power density caused by lower operating voltage, while also lowering the knee voltage to increase the effective voltage swing. This requires the introduction of a barrier layer with a high aluminum (Al) content, such as an aluminum content exceeding 20%, in III-nitride HEMTs. Furthermore, from a cost-effective perspective, using silicon (Si) as a substrate for epitaxially growing the III-nitride channel layer, rather than silicon carbide (SiC) substrates, is a viable solution. However, due to the large lattice and thermal mismatch between Si and III-nitrides (e.g., gallium nitride (GaN)), the growth of high-Al content materials is difficult, resulting in poor quality and high defects in the grown materials. When Schottky contacts are formed between metals and these materials through semiconductor processing, these defects act as leakage channels, causing high gate leakage currents and degraded device performance in HEMTs based on these materials. In order to reduce the gate leakage current, it is necessary to introduce an insulating layer (gate dielectric layer) on the barrier layer to form a metal-insulator-semiconductor (MIS)-HEMT structure, thereby realizing a device with low gate leakage current. In the process of mounting the integrated circuit based on the above-mentioned III-nitride HEMT (for example, in the form of a power amplifier chip, a bare chip, a die, etc.) to the packaging substrate of the RF module, ESD problems will inevitably exist. When an ESD event occurs on the gate, the physical structure that withstands the ESD pulse is almost only the gate dielectric layer and the barrier layer. The MIS structure is an insulating medium. When the current passing through it is greater than a certain value, the insulating medium will be broken down, causing the HEMT to fail. Although each electrode (such as Figure 3 The pin P in the chip is connected to the pin 60 outside the chip, so in the chip, the electrode of the III-nitride integrated circuit (such as Figure 3The P shown is not exposed. However, during back-end IC processing, such as IC packaging, ESD events can occur due to issues like production line control, leading to IC failure. In such cases, mass production of integrated circuits using Group III nitrides in terminal applications would be hampered by ESD issues.

[0078] By adopting the solution provided in the embodiment of the present application, during the process of attaching the integrated circuit to the package substrate, the electrostatic voltage V ESD Transmitted to the ground terminal GND; effectively avoiding the problem of electrostatic discharge breaking down the transistor and causing integrated circuit failure.

[0079] Take an integrated circuit containing a HEMT as an example, wherein the integrated circuit comprises a stacked structure formed by stacking multiple materials. Figure 8 、 Figure 9 As shown, Figure 8 shows a schematic cross-sectional view of a transistor in the XZ plane within the three-dimensional coordinate space XYZ. Figure 9 The schematic diagram shows a top view of the transistor structure in the Z direction. Transistor 32 primarily comprises a channel layer 321, a barrier layer 322, a gate dielectric layer 323, and electrodes on the gate dielectric layer 323, such as a gate 325, a source 324, and a drain 326. The source 324 and drain 326 are in contact with the channel layer 321. In some examples, the electrodes are also covered by a first dielectric layer 34. When a Group III nitride HEMT is a Group III nitride, the channel layer 321 and barrier layer 322 in transistor 32 typically comprise a Group III nitride, which is a compound composed of two or more elements. Among the elements in a Group III nitride is nitrogen, and one or more Group III elements in the periodic table, such as aluminum (Al), gallium (Ga), and indium (In), are also included. Typical examples of Group III nitrides include gallium nitride (GaN) and / or aluminum gallium nitride (AlGaN). The electrodes are typically made of metal, such as copper (Cu). The source 324 and the drain 326 form conductive ohmic contacts with the barrier layer 324, respectively, and the gate 325 forms a Schottky contact with the barrier layer 322. The dotted line in the channel layer 321 represents the two-dimensional electron gas (2DEG) generated in the heterostructure formed by the channel layer 321 and the barrier layer 322 in the HEMT. The two-dimensional electron gas moves in the horizontal direction (such as Figure 8In the figure, the mobility of the channel layer 321 (dashed line) is very high and is fundamental to the operation of the HEMT. In some examples, other functional layer structures may be provided between the channel layer 321 and the barrier layer 322, or between the channel layer 321 and the substrate 31. For example, an insertion layer may be provided between the channel layer 321 and the barrier layer 322. The insertion layer increases the density, localization, and mobility of the two-dimensional electron gas, thereby improving device performance, such as achieving excellent switching performance. Therefore, the insertion layer is optional; without the insertion layer in a HEMT, device performance will be reduced. Furthermore, a buffer layer may be provided between the channel layer 321 and the substrate 31. This buffer layer is also optional and serves as a transition layer when the crystal structures of the channel layer 321 and the substrate 31 differ significantly. For example, when the crystal structures of the channel layer 321 and the substrate differ significantly, a buffer layer with a lesser crystal structure than that of the substrate may be first grown epitaxially on the substrate 31, and then the channel layer 321 may be formed epitaxially on the buffer layer. Typically, the integrated circuit is also provided with a first dielectric layer 34 covering the transistor 32, as well as a metal wiring layer 35 and a protective layer 36 provided on the first dielectric layer 34, wherein the electrode of the transistor 32 is electrically connected to the metal wiring in the metal wiring layer 35 through a via h, and the metal wiring in the metal wiring layer 35 is electrically connected to the electrodes (gate electrode Pg, source electrode Ps and drain electrode Pd) outside the protective layer 36 through the via h. Thus, when the integrated circuit is connected to other components such as a package substrate through a patch method, the electrodes outside the protective layer 36 are connected to the electrodes on the package substrate, thereby enabling the PCB to provide signals to the integrated circuit or transmit the signals output by the integrated circuit to the PCB. Among them, the protective layer 36 and the first dielectric layer 34 can be made of insulating materials such as silicon oxide and resin. The metal wiring layer 35 can be formed by one or more patterning processes in an insulating material layer (such as silicon oxide) to form one or more layers of metal wiring for interconnection. The metal wiring of different layers can be electrically connected through vias. The metal wiring is used to achieve interconnection. The protective layer 36 is usually the outermost material layer on the die, and the protective layer is specifically used to protect the devices or metal wiring and other traces on the die. The vias in the embodiments of the present application can also be referred to as metallized holes. Usually, in order to electrically connect the conductive structures on both sides of the dielectric layer, a common hole, i.e., a via, is drilled at the intersection of the conductive structures that need to be electrically connected on both sides of the dielectric layer. In terms of process, a layer of conductive material, such as metal, is made on the cylindrical surface of the hole wall of the via to electrically connect the conductive structures that need to be connected. In the embodiments of the present application, the metal wiring in the metal wiring layer 35 can be electrically connected to the gate electrode Pg, the source electrode Ps and the drain electrode Pd by vias, and the metal wiring in the metal wiring layer 35 can be electrically connected to the gate G, the source S and the drain D of the transistor 32 by vias. Specifically, as Figure 10 、 Figure 11As shown, in order to lead the gate 325, source 324 and drain 326 to connect with other external components, it also includes a gate electrode Pg, a source electrode Ps and a drain electrode Pd arranged in different layers from the gate 325, source 324 and drain 326, wherein the gate electrode Pg, source electrode Ps and drain electrode Pd are arranged outside the protective layer 36, the gate 325 of the transistor 30 is coupled to the gate electrode Pg, the source 324 of the transistor 30 is coupled to the source electrode Ps, and the drain 326 of the transistor 30 is coupled to the drain electrode Pd. The control end of the switching device 33 is coupled to the control electrode Pm, and the control electrode Pm is configured to receive a control signal. Among them, the control electrode Pm can be connected to Figure 8 The gate electrode Pg, source electrode Ps, and drain electrode Pd are formed on the same layer outside the protective layer 36. The control electrode Pm can be coupled to the control terminal of the switching device M through the metal wiring in the metal wiring layer 35. Figure 8 The figure shows that a transistor has three electrodes (gate electrode Pg, source electrode Ps and drain electrode Pd) set outside the protective layer for explanation. Of course, when one of the gate G, source S and drain D of the transistor is directly connected to other devices in the integrated circuit without the need to be connected to the external circuit through the pins of the chip, it is also possible to selectively set only one or two of the gate electrode Pg, source electrode Ps and drain electrode Pd.

[0080] Currently, combined Figure 12 As shown, after the chip is taped out and diced, the cost of on-wafer screening (chip selection), chip packaging, and module test screening is basically 1:1:1. Taking integrated circuits based on group III nitride as an example, at present, the yield of mature processes is only 80%, while the yield of new processes is only 70%. In this case, if the integrated circuits after the tape-out and dicing processes are not screened on the wafer, but the bad bare chips are packaged through chip mounting and then screened out through module testing, the cost will increase greatly. If the yield of the bare chip after the tape-out process is 70%, then the total cost difference between on-wafer screening and not on-wafer screening reaches 20% ((1+0.7+0.7) / (1+1+1)). Therefore, from the perspective of cost control, bare chips need to be screened on the wafer. In this way, in the on-wafer screening stage before the integrated circuit is mounted on the packaging substrate, refer to Figure 13 As shown, a control signal is applied to the control electrode Pm so that the switch device 33 is in the off state, so that the gate G of the transistor 32 and the ground terminal GND are in the open circuit state, then a test signal can be applied to the gate electrode Pg connected to the gate G of the transistor 32, and the on-wafer screening of the transistor 32 can be achieved by detecting the output signal of the drain D; in the process of mounting the integrated circuit to the packaging substrate, refer to Figure 14As shown, a control signal is applied to the control electrode Pm so that the switch device 33 is in the on state (or another state of the switch device 33 is the normally-on state. It can be understood that when one state of the switch device, such as a HEMT, is in the normally-on state, applying a control signal to its gate can change the state of the HEMT to the off state. When the switch device 33 is in the normally-on state, no control signal can be applied to its gate, or the control signal is 0). In this way, the gate G of the transistor 32 and the ground terminal GND are short-circuited through the switch device 33, and the electrostatic voltage V ESD Transmit to the ground terminal GND; after the integrated circuit is mounted on the package substrate, refer to Figure 15 As shown, to ensure the normal operation of transistor 32, the gate G of transistor 32 needs to be disconnected from the ground terminal GND. Therefore, the switch device 33 is turned off by a control signal to disconnect the gate G of transistor 32 from the ground terminal GND. It should be noted that before the integrated circuit is mounted on the packaging substrate, the test signal applied to the gate electrode Pg and the control signal applied to the control electrode Pm can be provided by a probe device capable of providing corresponding signals or voltages. Specifically, the corresponding probe can be connected to the corresponding electrode on the fixture to apply the above-mentioned signal or voltage.

[0081] In addition, during the bonding process of the integrated circuit to the packaging substrate, since the above-mentioned electrodes (gate electrode Pg, source electrode Ps, drain electrode Pd and control electrode Pm) are packaged, it is impossible to apply a control signal to the control electrode Pm through a probe during this process. In addition, if a control signal can be applied to the control electrode Pm through a probe, ESD will also be directly released through the probe, and there will be no electrostatic discharge problem. Therefore, the switching device provided in another embodiment of the present application can be a depletion-type HEMT. Since the depletion-type HEMT is in a normally-on state when no signal is applied to the gate (or the control signal is 0), for the depletion-type HEMT, the gate is not energized. When the voltage is high, there is sufficient two-dimensional electron gas concentration. Therefore, the source S and drain D of the depletion-mode HEMT are in a normally-on state. To turn off the depletion-mode HEMT, a negative voltage must be applied to the gate G of the depletion-mode HEMT. When the negative voltage provided by the gate G of the depletion-mode HEMT is less than the threshold voltage, the depletion-mode HEMT is turned off. The negative voltage on the gate G of the depletion-mode HEMT generates an electric field opposite to the built-in electric field, which reduces the band bending at the barrier layer / channel layer heterojunction interface, reduces the depth of the triangular potential well, and thus reduces the two-dimensional electron gas concentration. Therefore, during the bonding process of the integrated circuit to the packaging substrate, the electrostatic voltage V on the gate G of the transistor 32 can be reduced by the normally-on depletion-mode HEMT. ESD Transmitted to the ground terminal GND.

[0082] Specific, combined Figure 16-18As shown, the switching device 32 includes a depletion-mode HEMT 33, the source S of the depletion-mode HEMT 33 is coupled to the ground terminal GND, the drain D of the depletion-mode HEMT 32 is coupled to the gate G of the transistor 32, and the gate G of the depletion-mode HEMT 33 is coupled to the control electrode Pm, wherein the control electrode Pm and the gate G of the depletion-mode HEMT 33 are electrically connected through a via; the depletion-mode HEMT 33 is in the on state, or the gate G of the depletion-mode HEMT 33 receives the first control voltage V1 (such as the negative voltage mentioned above) transmitted by the control electrode Pm, and the depletion-mode HEMT 33 is in the off state under the control of the first control voltage V1. Figure 16-Figure 18 The source S of the depletion-mode HEMT can be understood as a first active electrode, and the drain D of the depletion-mode HEMT can be understood as a second active electrode. In one embodiment, the source S of the depletion-mode HEMT is coupled to the first end of the electrostatic discharge wire 33, and the drain D of the depletion-mode HEMT is coupled to the gate of the transistor 32. In another embodiment, the drain D of the depletion-mode HEMT can be coupled to the first end of the electrostatic discharge wire, and the source S of the depletion-mode HEMT is coupled to the gate of the transistor 32.

[0083] Specifically, in the on-wafer screening stage before the integrated circuit is mounted on the package substrate, refer to Figure 16 As shown, a negative voltage is applied to the control electrode Pm, so that the depletion-mode HEMT is in the off state, so that the gate G of the transistor 33 and the ground terminal GND are in the open circuit state, then the test signal can be applied to the gate G of the transistor 32 connected to the gate electrode Pg, and the output signal of the drain D of the transistor 32 is detected to achieve on-wafer screening of the transistor 32; in the process of bonding the integrated circuit to the packaging substrate, refer to Figure 17 As shown, no voltage is applied to the control electrode Pm (the control electrode Pm is floating) so that the depletion-type HEMT is in the on state. In this way, the gate G of the transistor 32 and the ground terminal GND are short-circuited through the depletion-type HEMT, and the electrostatic voltage V ESD From the transmission to the ground terminal GND; after the integrated circuit is mounted on the package substrate, refer to Figure 18 As shown, in order to ensure that the transistor 32 works normally, the gate G of the transistor 32 and the ground terminal GND need to be disconnected. Therefore, by applying a negative voltage to the control electrode Pm, the depletion-type HEMT is in the off state, thereby disconnecting the gate G of the transistor 32 and the ground terminal GND.

[0084] In some examples, the channel layer and barrier layer of a depletion-mode HEMT include a Group III nitride. Group III nitrides are compounds composed of two or more elements, including nitrogen, and contain one or more Group III elements from the periodic table, such as Al, Ga, and In. Typical examples of Group III nitrides include GaN and AlGaN.

[0085] In light of the above description, depletion-mode HEMTs typically require a negative gate input voltage for shutdown. In the embodiments of this application, the threshold voltage of a depletion-mode HEMT is -60V to -0.1V. When such HEMTs operate in terminals such as mobile phones, the lowest supply voltage they can provide is generally not too negative, approximately -5V to -10V. Therefore, in some applications, the threshold voltage of a depletion-mode HEMT will be greater than -10V. In contrast, the threshold voltage of a depletion-mode HEMT using Group III nitride is typically -4V to -2V.

[0086] Combine Figure 15 As shown, during the process of pasting the integrated circuit onto the packaging substrate, the control electrode Pm will also accumulate electrostatic charge, so the gate of the depletion-mode HEMT also has an ESD problem. In order to reduce the risk of breakdown of the gate dielectric layer and the barrier layer of the depletion-mode HEMT, the gate dielectric layer of the depletion-mode HEMT is set to be thick enough. The thickness of the gate dielectric layer of the depletion-mode HEMT is 0.1nm-200nm. For example, in order to withstand 100V ESD, the thickness of the gate dielectric layer is about 200nm. When the gate dielectric layer of the depletion-mode HEMT and the gate dielectric layer of the transistor are made of the same material, the thickness of the gate dielectric layer of the depletion-mode HEMT is greater than the thickness of the gate dielectric layer of the transistor. At this time, the depletion-mode HEMT provided in the embodiment of the present application is also called a depletion-mode thick-film HEMT (DTF-HEMT), combined with Figure 8 、 Figure 19 As shown, Figure 19 A schematic diagram of the structure of a depletion-mode HEMT is provided. Figure 6 The structure of the HEMT in the depletion-type HEMT is similar to that of the HEMT in the embodiment of the present invention. The depletion-type HEMT includes a channel layer, a barrier layer, a gate dielectric layer, and electrodes on the gate dielectric layer, such as a gate, a source, and a drain. The source and the drain are in contact with the channel layer. The thickness H2 of the gate dielectric layer of the depletion-type HEMT is greater than Figure 8 The thickness H1 of the gate dielectric layer of the transistor 32 is shown in FIG. In addition, the depletion-mode HEMT 33 and the transistor 32 may further include a fin gate structure. Figure 20 、 Figure 21 shown, among which Figure 20 The diagram shows a schematic top view of a fin-gate transistor in the Z direction within the three-dimensional coordinate space XYZ. Figure 21 The cross-sectional structure diagram of the fin-gate transistor in the XZ plane is shown. In the fin-gate transistor 32, the gate 325 surrounds the stacked barrier layer 322 and the channel layer 321, wherein a gate dielectric layer 323 is included between the gate 325 and the barrier layer 322 and the channel layer 321. Figure 21 and Figure 22 ( Figure 22 As shown in a schematic diagram of a cross-sectional structure of a fin-gate depletion-mode HEMT in an XZ plane, in the fin-gate depletion-mode HEMT 33 and the transistor 32 , the thickness H4 of the gate dielectric layer of the depletion-mode HEMT 33 is greater than the thickness H3 of the gate dielectric layer of the transistor 32 .

[0087] In addition, in semiconductor devices, there are several physical trends: a. The thicker the barrier layer, the more electrons there are under the gate; b. The thicker the gate dielectric layer, the smaller the gate capacitance; c. The gate voltage that just depletes the electrons under the gate is called the threshold voltage. In addition, the integral (or area) of the gate capacitance within a certain gate voltage range corresponds to the total number of electrons. In this way, combined with the above description of the threshold voltage and the thickness of the gate dielectric layer, it is hoped that there will be electrons under the channel layer (so as to ensure that when the gate of the depletion-type HEMT device is suspended, the depletion-type HEMT device is in a low-resistance state), but it is not hoped that there will be too many electrons under the channel layer (if there are too many electrons, then the threshold voltage will be very negative, and due to the limitations of terminal application scenarios such as mobile phones, there is no very negative voltage to turn off the depletion-type HEMT device). Therefore, the embodiment of the present application is about how to make good use of the physical relationship of the integral of the gate capacitance within the gate voltage range. As Figure 23 As shown in FIG, after the gate dielectric layer is thickened (for example, from 10 nm to 200 nm), the gate capacitance is reduced and the ability to deplete electrons is weakened, so a more negative voltage is required, such as Figure 23 In the case of III-nitride devices, a voltage of -100V is required to completely deplete the electrons, which is obviously unacceptable. In order to reduce the voltage required to deplete the electrons, another approach is to reduce the total number of electrons, thereby reducing the integrated area and thus reducing the voltage required to deplete the electrons. In III-nitride devices, the most effective way to reduce the number of electrons is to reduce the thickness of the barrier layer, such as Figure 23 As shown in , the barrier layer thickness is reduced from 20nm to 3nm. Thus, a voltage of -8V can completely deplete electrons, satisfying the terminal's voltage supply capability. In the embodiments of the present application, the thickness of the gate dielectric layer of the depletion-mode HEMT is 0.1nm-100nm. When the barrier layer of the depletion-mode HEMT and the barrier layer of the transistor are made of the same material, the thickness of the barrier layer of the depletion-mode HEMT is less than that of the barrier layer of the transistor.

[0088] Furthermore, in another embodiment, in combination Figure 24As shown, when the integrated circuit is used as a radio frequency circuit, it may also include other components, for example, an inductor L1 connected in series between the power supply Vdc and the transistor 32, and an inductor L2 connected in series between the radio frequency output terminal RF-out, wherein the radio frequency output terminal RF-out and the ground terminal GND are further connected in series with a capacitor C. Figure 24 Only one implementation of a radio frequency circuit is provided. Other possible implementations may include more or fewer other components. Furthermore, it should be noted that these other components may be fabricated directly on the substrate of the integrated circuit, or may be connected as peripheral devices to electrodes on the integrated circuit to form a circuit with a specific function.

[0089] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An integrated circuit, characterized in that: The integrated circuit is used in a radio frequency module, comprising: a substrate and a transistor disposed on the substrate; a gate of the transistor is coupled to a first end of a switch device, and a second end of the switch device is coupled to a ground end; the transistor is used in a power amplifier PA of the radio frequency module; The switch device is configured to be in an on state or an off state under the control of a control signal received by the control terminal; the switch device transmits the electrostatic voltage of the gate of the transistor to the ground terminal in the on state; or, the switch device disconnects the gate of the transistor from the ground terminal in the off state; The transistor includes a HEMT, and the switching device includes a depletion-mode HEMT. A gate dielectric layer of the depletion-mode HEMT and a gate dielectric layer of the transistor are made of the same material. A barrier layer of the depletion-mode HEMT and a barrier layer of the transistor are made of the same material. The gate dielectric layer of the depletion-mode HEMT is thicker than the gate dielectric layer of the transistor, and the barrier layer of the depletion-mode HEMT is thinner than the barrier layer of the transistor.

2. The integrated circuit according to claim 1, wherein: The control terminal of the switching device is coupled to a control electrode, and the control electrode is configured to receive the control signal.

3. The integrated circuit according to claim 1, wherein: The gate of the transistor is also coupled to the gate electrode, and the gate of the transistor is electrically connected to the gate electrode through a via.

4. The integrated circuit according to claim 1, wherein: The switching device comprises a depletion-mode HEMT, wherein a first active electrode of the depletion-mode HEMT is coupled to the ground terminal, a second active electrode of the depletion-mode HEMT is coupled to the gate of the transistor, and the gate of the depletion-mode HEMT is coupled to the control electrode; The depletion-mode HEMT is in an on-state, or a gate of the depletion-mode HEMT receives a first control voltage transmitted by the control electrode, and the depletion-mode HEMT is in an off-state under the control of the first control voltage.

5. The integrated circuit according to claim 1, wherein: The transistor and / or the switching device includes a fin-gate transistor.

6. The integrated circuit according to any one of claims 1 to 5, characterized in that: A channel layer of the transistor includes a Group III nitride.

7. The integrated circuit according to any one of claims 1 to 5, characterized in that: A channel layer of the transistor includes a material different from that of the substrate, and the channel layer is located on the substrate.

8. The integrated circuit according to claim 4, wherein: The channel layer and the barrier layer of the depletion-mode HEMT include group III nitride.

9. The integrated circuit according to claim 8, wherein: The thickness of the barrier layer of the depletion-mode HEMT is 0.1 nm-100 nm.

10. The integrated circuit according to claim 8, wherein: The thickness of the gate dielectric layer of the depletion-mode HEMT is 0.1 nm-200 nm.

11. The integrated circuit according to claim 4, wherein: The threshold voltage of the depletion-mode HEMT is -60V to -0.1V.

12. The integrated circuit according to any one of claims 1 to 5, characterized in that: The integrated circuit is a monolithic microwave integrated circuit MMIC.

13. A chip, characterized in that: The integrated circuit comprises the integrated circuit and the packaging substrate according to any one of claims 1 to 12, wherein the integrated circuit is coupled to the packaging substrate.

14. An electronic device, characterized in that: The device comprises a printed circuit board and the chip according to claim 13; the chip is coupled to the printed circuit board.

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