Non-volatile memory element with Schottky diode

Abstract

A non-volatile memory element with a Schottky diode. The non-volatile memory element comprises: an insulating layer for electrical insulation; a Schottky diode formed on the insulating layer as a single crystal semiconductor layer, the material of which can be silicon, germanium, hexagonal boron nitride, or gallium arsenide; a conductive write wire electrically connected to the front end of the Schottky diode; a memory cell located on the Schottky diode and electrically connected to the rear end of the Schottky diode; and a select wire located on the memory cell and electrically connected to the memory cell. When data is selected for writing into the non-volatile memory element, a current flows through the Schottky diode to write the data into the memory cell.

Description

Technical Field

[0001] The present invention relates to a non-volatile storage element, and in particular to a non-volatile storage element using a Schottky diode as a selector. Background Art

[0002] Figure 1A and Figure 1B Figures 1 and 2 show a typical phase change random access memory (PCRAM) device 10 in a cross-sectional view and a three-dimensional (3D) view. PCRAM device 10 is a non-volatile memory device used in electronic circuits to store data. Even when the electronic circuit is turned off and power is removed, the stored data remains in its phase change region and does not disappear.

[0003] like Figure 1A and Figure 1B As shown, the PCRAM device 10 is formed on a substrate 11 and includes a source / drain 12 , a bidirectional selector 13 , metal plugs 141 and 142 , a phase change region 15 , a ground wire 16 , and a bit wire 17 . The PCRAM device 10 addresses the specific phase change region 15 to which data is to be written via a bidirectional selector 13 and a bit conductor 17. The bidirectional selector 13 is controlled to open a channel between the source / drain 12. The voltage of the bit conductor 17 is controlled to control the current flowing through the metal plug 141, the source / drain 12, the channel, the metal plug 142, the phase change region 15, and the ground conductor 16. This changes the crystalline state of the material in the phase change region 15. Different crystalline states give the phase change region 15 different resistance values, representing different stored data. The material in the phase change region 15 is, for example, a germanium-antimony-tellurium (GeSbTe, GST) alloy, which has different resistance values in its crystalline and amorphous states. The PCRAM device 10 writes data representing "1" and / or "0" into the phase change region 15 by addressing and changing the resistance of the phase change region 15. This is well known to those skilled in the art and will not be described in detail here.

[0004] Figure 2A and Figure 2BThe following diagrams show a cross-sectional schematic and a three-dimensional (3D) schematic of a typical spin transfer torque (STT) magnetoresistive random access memory (MRAM) device 20. The STT-MRAM device 20 is a type of MRAM device, also known as a non-volatile memory device, used in electronic circuits to store data. Even when the electronic circuit is turned off and power is removed, the stored data remains in the magnetic region within the device. The MRAM device includes an upper electrode and a lower electrode, both made of ferromagnetic material, with an oxide layer (such as magnesium oxide) sandwiched between them. When the magnetization directions of the upper and lower ferromagnetic layers change from parallel to antiparallel, their resistance increases. Conversely, when the magnetization directions change from antiparallel to parallel, their resistance decreases. This mechanism changes the resistance of the magnetic region to represent different stored data.

[0005] like Figure 2A and Figure 2B As shown, an STT-MRAM device 20 is formed on a substrate 21 and includes source / drain 22, a bidirectional selector 23, metal plugs 241 and 242, a magnetic region 25, connecting conductive elements 261 and 262, and a bit conductor 27. The STT-MRAM device 20 uses the bidirectional selector 23 and bit conductor 27 to determine the address of the magnetic region 25 where data is written. By controlling the bidirectional selector 23, the channel between the source / drain 22 is turned on. By controlling the voltage of the bit conductor 27, the current flowing through the magnetic region 25, the connecting conductive element 261, the metal plug 241, the channel between the source / drain 22 and the source / drain 22, another metal plug 242, and the connecting conductive element 262 is controlled, thereby changing the magnetization direction of the material in the magnetic region 25. As previously described, the different magnetization directions of the ferromagnetic layers in the upper and lower electrodes result in different resistance values in the magnetic region 25, indicating different stored data. The upper and lower electrodes are made of, for example, cobalt iron (CoFe) or cobalt iron boron (CoFeB). The STT-MRAM device 20 uses this mechanism to write data representing "1" and / or "0" into the magnetic region 25. This mechanism is well known to those skilled in the art and will not be further described here.

[0006] Figure 3A and Figure 3BFigures 30 and 3D (three-dimensional) schematic diagrams of a typical resistive random access memory (RRAM) device 30 are shown. RRAM device 30 is a non-volatile memory device used in electronic circuits to store data. Even when the electronic circuit is turned off and power is removed, the stored data remains in its resistance-variable region.

[0007] like Figure 3A and Figure 3B As shown, the RRAM device 30 is formed on a substrate 31 and includes a source / drain 32 , a bidirectional selector 33 , metal plugs 341 and 342 , a resistance variable region 35 , a ground wire 36 , and a bit wire 37 . The RRAM device 30 addresses the specific resistance variable region 35 to which data is to be written via a bidirectional selector 33 and a bit conductor 37. The bidirectional selector 33 is controlled to open the channel between the source / drain 32. The voltage of the bit conductor 37 is controlled to control the current flowing through a metal plug 341, the channel between the source / drain 32 and the source / drain 32, another metal plug 342, the resistance variable region 35, and the ground conductor 36. This changes the resistance value of the resistance variable region 35, thereby representing different stored data. The resistance variable region 35 includes two metal layers separated by a dielectric layer. The metal layers are made of, for example, copper telluride (CuTe) or copper germanium (CuGe) alloy. The RRAM device 30 addresses and changes the resistance value of the resistance variable region 35 in the manner described above to write data representing "1" or / and "0" into the resistance variable region 35. This is well known to those skilled in the art and will not be described in detail here.

[0008] Conventional non-volatile memory devices and selectors for writing data to storage units are all bidirectional switches, such as the aforementioned bidirectional selectors 15, 25, and 35, which are, for example, metal oxide semiconductor (MOS) devices. Therefore, the use of bidirectional selectors in non-volatile memory devices has at least the following disadvantages: First, taking MOS devices as bidirectional selectors as an example, because they require a source, a gate, and a drain, the area of MOS devices is larger than that of diodes, such as Schottky diodes. In terms of technological advancement in miniaturization, the basic conditions for traditional non-volatile memory devices are poor; second, the on-state current is also limited by the electrical characteristics of the MOS device. The MOS device has a saturation region in operation. Compared with diodes, such as Schottky diodes, the on-state current of the MOS device is relatively low. Taking MRAM devices as an example, when using MOS devices as bidirectional selectors, the current for writing data to the magnetic region must usually reach 107 A / cm 2 To achieve this current, the MOS device area must be significantly larger than that of a Schottky diode. Third, the MOS device channel is formed in the semiconductor substrate, resulting in relatively high leakage current. As non-volatile memory device technology continues to shrink in size and increase in current per unit area, the application range of traditional bidirectional selectors for controlling non-volatile memory devices is significantly limited.

[0009] Another related technology is the 90nm 512Mb PCRAM device proposed by JHOh et al. in 10.1109 / IEDM.2006.346905. This paper discloses a PCRAM device fabricated using standard CMOS process steps. This prior art PCRAM device forms an epitaxial silicon layer on a silicon substrate heavily doped with N-type impurities. A PN diode is then formed within this epitaxial silicon layer as the PCRAM device's selector. Because the PN diode is formed within the epitaxial silicon layer, its on-resistance is higher than that of a PN diode formed in a single-crystal silicon layer. Furthermore, the heavily N-type doped silicon substrate of this PCRAM device cannot effectively isolate it from other devices, resulting in relatively high leakage current. This also poses challenges in scaling the device in the face of evolving semiconductor process technologies.

[0010] In view of this, the present invention addresses the above-mentioned deficiencies in the prior art and proposes a non-volatile memory element with a Schottky diode, which can reduce the area of the non-volatile memory element and increase the current per unit area, thereby expanding the application range of the non-volatile memory element. Summary of the Invention

[0011] From one perspective, the present invention provides a non-volatile memory element, comprising: an insulating layer for electrical insulation; a first Schottky diode formed on a single crystal semiconductor layer on the insulating layer, the material of which can be silicon, germanium, hexagonal boron nitride layer or gallium arsenide; a first write wire that is conductive and electrically connected to a first front end of the first Schottky diode; a memory cell located on the first Schottky diode and electrically connected to a first rear end of the first Schottky diode; and a select wire that is conductive, located on the memory cell and electrically connected to the memory cell; when the non-volatile memory element is selected to write a first data, a first current flows through the first Schottky diode to write the first data into the memory cell.

[0012] From another perspective, the present invention provides a nonvolatile memory device comprising: a nonvolatile memory element array comprising a plurality of nonvolatile memory elements; and a control circuit for controlling the nonvolatile memory element array to perform read and write operations on the nonvolatile memory elements. The nonvolatile memory elements include: an insulating layer for electrical insulation; a first Schottky diode formed in a single crystal semiconductor layer on the insulating layer, the material of which may be silicon, germanium, hexagonal boron nitride, or gallium arsenide; a first write conductive line having conductivity and electrically connected to a first front end of the first Schottky diode; a memory cell located on the first Schottky diode and electrically connected to a first rear end of the first Schottky diode; and a select conductive line located on the memory cell and electrically connected to the memory cell. When the nonvolatile memory element is selected for writing a first data, a first current flows through the first Schottky diode to write the first data into the memory cell.

[0013] In a preferred embodiment, the first Schottky diode is stacked and connected to the insulating layer.

[0014] In a preferred embodiment, the first write conductive line is stacked and connected to the insulating layer, and the first Schottky diode is stacked and connected to the first write conductive line.

[0015] In a preferred embodiment, the non-volatile memory element further includes: a second Schottky diode formed in the single crystal semiconductor layer on the insulating layer, the material of which can be silicon, germanium, hexagonal boron nitride, or gallium arsenide; and a second write conductive line, which is conductive and electrically connected to a second front end of the second Schottky diode. When the non-volatile memory element is selected to write a second data, a second current flows through the second Schottky diode to write the second data into the memory cell.

[0016] In a preferred embodiment, the second Schottky diode is stacked and connected to the insulating layer.

[0017] In a preferred embodiment, the second write conductive line is stacked and connected to the insulating layer, and the second Schottky diode is stacked and connected to the second write conductive line.

[0018] In a preferred embodiment, the non-volatile memory element further includes: a first connecting conductive unit for electrically connecting the memory cell to the first rear end of the first Schottky diode, wherein a portion of the first connecting conductive unit is stacked and connected to the first rear end; and a second connecting conductive unit for electrically connecting the first connecting conductive unit to the second rear end of the second Schottky diode to electrically connect the memory cell to the second rear end; wherein the first write conductive line is stacked and connected to the insulating layer, and the first front end is stacked and connected to the first write conductive line. The first rear end is stacked and connected to the first front end; a first part of the second connected conductive unit is stacked and connected to the insulating layer, a second part of the second connected conductive unit is stacked and connected to the first part, and another part of the first connected conductive unit is stacked and connected to the second part; the second rear end is stacked and connected to the first part, and the second front end is stacked and connected to the second rear end, and the second write wire is stacked and connected to the second front end; the first wire and the first part are formed by the same metal deposition process step.

[0019] In a preferred embodiment, the nonvolatile memory element further includes a first connecting conductive unit electrically connected between the first Schottky diode and the memory cell to electrically connect the memory cell to the first rear end of the first Schottky diode.

[0020] In a preferred embodiment, the nonvolatile memory element further includes a second connecting conductive unit electrically connected between the second Schottky diode and the memory cell to electrically connect the memory cell to the second rear end of the second Schottky diode.

[0021] In a preferred embodiment, the non-volatile memory element is a phase change random access memory (PCRAM), a magnetoresistive random access memory (MRAM), or a resistive random access memory (RRAM).

[0022] In a preferred embodiment, the first write conductive line is a metal conductive line.

[0023] In a preferred embodiment, the first write conductive line and the second write conductive line are metal conductive lines.

[0024] In a preferred embodiment, the nonvolatile memory element is formed on a semiconductor-on-insulator (SOI) substrate or a semiconductor-on-metal-insulator (SMOI) substrate.

[0025] In a preferred embodiment, the first connecting conductive unit and the second writing conductive line are formed by the same metal deposition process.

[0026] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1A and 1B A typical phase change random access memory (PCRAM) device 10 is shown in a cross-sectional schematic diagram and a 3D (three dimensional) schematic diagram.

[0028] Figure 2A and 2B A cross-sectional schematic diagram and a 3D (three dimensional) schematic diagram of a typical spin transfer torque (STT) magnetoresistive random access memory (MRAM) device 20 are shown respectively.

[0029] Figure 3A and 3B A cross-sectional schematic diagram and a 3D (three dimensional) schematic diagram of a typical resistive random access memory (RRAM) device 30 are shown respectively.

[0030] Figure 4A and 4B A schematic cross-sectional view and a 3D schematic view are shown for one embodiment of a non-volatile memory element according to the present invention.

[0031] Figure 4C Display as Figure 4A and 4B The cross-sectional view of an embodiment of the arrangement of the non-volatile memory element 40 on the same selection conductor 46 is shown.

[0032] Figure 4D A schematic cross-sectional view showing one embodiment of a nonvolatile memory element according to the present invention.

[0033] Figure 4E A schematic cross-sectional view showing one embodiment of a nonvolatile memory element according to the present invention.

[0034] Figure 4F A schematic diagram showing one embodiment of a nonvolatile memory device according to the present invention.

[0035] Figure 5A and 5B A schematic cross-sectional view and a 3D schematic view are shown for one embodiment of a non-volatile memory element according to the present invention.

[0036] Figure 6A A schematic cross-sectional view showing one embodiment of a nonvolatile memory element according to the present invention.

[0037] Figure 6B A schematic cross-sectional view showing one embodiment of a nonvolatile memory element according to the present invention.

[0038] Figure 7A and 7B A schematic cross-sectional view and a 3D schematic view are shown for one embodiment of a non-volatile memory element according to the present invention.

[0039] Figure 8A 、 8B 8C show a cross-sectional schematic diagram, a 3D schematic diagram, and an operation table of an embodiment of a non-volatile memory element according to the present invention.

[0040] Figure 8D A 3D schematic diagram showing one embodiment of a non-volatile memory element according to the present invention.

[0041] Figure 9A 、 9B 9C show a cross-sectional schematic diagram, a 3D schematic diagram, and an operation table of an embodiment of a non-volatile memory element according to the present invention.

[0042] Figure 9D A schematic diagram showing one embodiment of a nonvolatile memory device according to the present invention.

[0043] Figure 10A A 3D schematic diagram showing one embodiment of a non-volatile memory element according to the present invention.

[0044] Figure 10B A 3D schematic diagram showing one embodiment of a non-volatile memory element according to the present invention.

[0045] Figure 11A and11B A 3D schematic diagram and an operation table showing one embodiment of a non-volatile memory element according to the present invention.

[0046] Figure 11C A schematic diagram showing one embodiment of a nonvolatile memory device according to the present invention.

[0047] Figure 12 A 3D schematic diagram showing one embodiment of a non-volatile memory element according to the present invention.

[0048] Figure 13A and 13B A 3D schematic diagram and a top view schematic diagram are shown for one embodiment of a non-volatile memory element according to the present invention.

[0049] Explanation of symbols in the figure

[0050] 4, 9, 11: Non-volatile storage devices

[0051] 10, 20, 40, 40', 50, 60, 70, 80, 80', 90, 100, 100', 110, 120, 130: non-volatile storage elements

[0052] 11, 21, 31, 41, 51, 61, 71, 81, 91: semiconductor substrates

[0053] 12, 22, 32: Source / Drain

[0054] 13, 23, 33: Bidirectional selector

[0055] 15: Phase change region

[0056] 16, 36: Grounding wire

[0057] 17, 27, 37: Position wires

[0058] 25: Magnetic zone

[0059] 35: Resistance change area

[0060] 42, 42', 52, 62, 72, 82, 82', 92, 102, 112, 122, 132: Insulation layer

[0061] 43, 43', 53, 63, 731, 732, 831, 831', 832, 832', 931, 932, 1031, 1032, 1033, 1034, 1131, 1132, 1133, 1134, 1231, 1232, 1233, 1234, 1331, 1332, 1333, 1334: Schottky diodes

[0062] 43a, 43a', 53a, 63a, 731a, 732a, 831a, 832a, 831a', 832a', 931a, 932a: front end

[0063] 43b, 43b', 53b, 63b, 731b, 732b, 831b, 832b, 831b', 832b', 931b, 932b: backend

[0064] 44, 44', 54, 64, 74, 841, 842, 841', 842', 942, 971, 1041, 1042, 1071, 1141, 1142, 1241, 1242, 1341, 1342: Write wire

[0065] 45, 45', 55, 65, 75, 85, 85', 95, 105, 115, 125, 135: storage unit

[0066] 46, 46', 56, 66, 76, 86, 86', 96, 106, 116, 126, 136: Select wire

[0067] 57, 67, 77, 87, 261, 262, 872, 972, 1043, 1044, 1071: Connecting conductive units

[0068] 141, 142, 241, 242, 341, 342: metal bolt

[0069] 871, 871', 941: Part I

[0070] 872, 872', 921: Part II

[0071] 873, 873': Part III

[0072] 1121, 1122, 1221, 1222, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328: Conductor plugs

[0073] 1172, 1173, 1272, 1273, 1371, 1372, 1373, 1374, 1375: wires

[0074] I0: first current

[0075] I1: Second current

[0076] Vr: read voltage

[0077] Vw: write voltage DETAILED DESCRIPTION

[0078] The foregoing and other technical aspects, features, and effects of the present invention will be more clearly understood in the following detailed description of preferred embodiments with reference to the accompanying drawings. The drawings herein are schematic, primarily intended to illustrate the hierarchical relationships between layers of the relevant device structures. The shapes, thicknesses, and widths are not drawn to scale.

[0079] Figure 4A and 4B A cross-sectional schematic diagram and a 3D (three-dimensional) schematic diagram of one embodiment of a nonvolatile memory element according to the present invention are shown. The nonvolatile memory element 40 according to the present invention is formed on a semiconductor substrate 41 and includes an insulating layer 42, a Schottky diode 43, a write conductive line 44, a memory cell 45, and a select conductive line 46. The insulating layer 42 is formed on the semiconductor substrate 41 and provides electrical insulation. Schottky diode 43 is formed in a single crystal semiconductor layer on insulating layer 42. The material of the layer may be silicon (Si), germanium (Ge), hexagonal boron nitride (hBN), or gallium arsenide (GaAs). Front end 43a is metal, forming a Schottky contact with the single crystal silicon layer, single crystal germanium layer, hBN layer, or single crystal GaAs layer. For example, an ion implantation process is used to implant N-type impurities (P-type impurities may also be implanted, but N-type impurities are preferred) in the form of accelerated ions at back end 43b (into the single crystal silicon layer, single crystal germanium layer, hBN layer, or single crystal GaAs layer), thereby forming Schottky diode 43. A write wire 44 is conductive and electrically connected to front end 43a (a metal terminal in this embodiment) of Schottky diode 43. Schottky diode 43 is unidirectionally conductive during operation. The memory cell 45 is located on the Schottky diode 43 and is electrically connected to the rear end 43b (in this embodiment, the N-type semiconductor end) of the Schottky diode 43. The select conductor 46 is conductive and located on and electrically connected to the memory cell 45. When the non-volatile memory element 40 is selected and data is written to the memory cell 45, a first current I0 flows through the Schottky diode 43 to write the data to the memory cell 45.

[0080] The non-volatile memory element 40 is addressed via the select wire 46 and the write wire 44 to determine the memory cell 45 at a specific address to which data is written. The potentials of the select wire 46 and the write wire 44 are adjusted to turn on the Schottky diode 43, and a first current I0 is caused to flow through the write wire 44, the Schottky diode 43, the memory cell 45, and the select wire 46 to write the data into the memory cell 45. The memory cell 45 can be a phase change region of a PCRAM element, a magnetic region of an MRAM element, or a resistance change region of an RRAM element. The so-called data, for example, is an electronic property representing "1" or "0", such as the crystalline state of the material, the magnetization direction, or the resistance. This is well known to those skilled in the art and will not be described in detail here.

[0081] It should be noted that because a Schottky diode includes a metal terminal and a semiconductor terminal, for ease of description, the "front end" described herein below can be either the metal terminal or the semiconductor terminal; the "back end" described herein below can also be either the metal terminal or the semiconductor terminal, but the front end and the back end form a Schottky contact. In addition, the metal terminal and the semiconductor terminal of the Schottky diode are both connected to other wires via ohmic contacts. Among them, the wires, such as write wires, select wires, or conductive units, are not described in detail.

[0082] Figure 4C Display as Figure 4A and 4B The cross-sectional view of an embodiment of the arrangement of the non-volatile memory element 40 on the same selection conductor 46 is shown. Figure 4C As shown, a plurality of nonvolatile memory elements 40 may be arranged continuously on the same selection conductor 46 , and a nonvolatile memory element array in which a plurality of nonvolatile memory elements 40 are arranged may be formed by the plurality of selection conductors 46 .

[0083] Figure 4D A cross-sectional view of an embodiment of a non-volatile memory element according to the present invention is shown. Figure 4A and 4B The difference of the embodiment shown is that the write wire 44 of this embodiment is stacked and connected to the front end 43a (metal end in this embodiment) of the Schottky diode 43, instead of Figure 4A As shown, the write wire 44 is laterally connected to the front end 43 a of the Schottky diode 43 . Figure 4D It is intended to illustrate that the wire 44 can not only be Figure 4A As shown, it is connected to the front end 43a in the transverse direction; the wire 44 can also be as shown Figure 4D As shown, it is connected to the front end 43a in the longitudinal direction.

[0084] Figure 4EA cross-sectional schematic diagram shows an embodiment of a nonvolatile memory element according to the present invention. The nonvolatile memory element 40' according to the present invention is formed on a semiconductor substrate 41' and includes an insulating layer 42', a Schottky diode 43', a write conductor 44', a memory cell 45', and a select conductor 46'. The insulating layer 42' is formed on the semiconductor substrate 41' and provides electrical insulation. Schottky diode 43' is formed in a single crystal silicon layer, single crystal germanium layer, hexagonal boron nitride layer, or single crystal gallium arsenide layer on insulating layer 42'. A rear end 43b' is metal, forming a Schottky contact with the single crystal silicon layer, single crystal germanium layer, hexagonal boron nitride layer, or single crystal gallium arsenide layer. For example, an ion implantation process is performed to implant N-type impurities (P-type impurities may also be implanted, but N-type impurities are preferred) in the form of accelerated ions into the front end 43a' (the single crystal silicon layer, single crystal germanium layer, hexagonal boron nitride layer, or single crystal gallium arsenide layer), thereby forming Schottky diode 43'. A write conductor 44' is conductive and electrically connected to the front end 43a' (the N-type semiconductor end in this embodiment) of Schottky diode 43'. Schottky diode 43' is unidirectionally conductive during operation. A memory cell 45' is located on the Schottky diode 43' and is electrically connected to a rear end 43b' (a metal end in this embodiment) of the Schottky diode 43'. A selection conductor 46' is conductive and located on and electrically connected to the memory cell 45'. When the non-volatile memory element 40' is selected and data is written to the memory cell 45', a first current I0' flows through the Schottky diode 43' to write the data to the memory cell 45'.

[0085] This embodiment and Figure 4A and 4B The difference between the embodiment shown is that the front end 43a' of this embodiment is an N-type semiconductor end and the rear end 43b' is a metal end, instead of the N-type semiconductor end. Figure 4A As shown, the front end 43a is a metal end, and the back end 43b is an N-type semiconductor end. Figure 4E The purpose is to illustrate that when a Schottky diode is applied to the selector of the non-volatile memory element of the present invention, its conduction current direction and Schottky contact can be changed according to the required application.

[0086] The advantages of the present invention over the prior art are at least as follows: First, according to the present invention, the non-volatile memory element adopts a unidirectional conductive selector (i.e., Schottky diode), and does not need to adopt a bidirectional conductive selector as in the prior art, which can save the space occupied by the selector and has a smaller area; Second, according to the present invention, the non-volatile memory element adopts a unidirectional conductive selector (Schottky diode) and is not limited to the electrical characteristics of a bidirectional conductive selector such as a MOS element. For example, the present invention can adopt a Schottky diode as a selector, which has a higher conduction current than a MOS element and has a wider range of applications; Third, according to the present invention, the non-volatile memory element adopts a unidirectional conductive selector (Schottky diode), which can be directly electrically connected to the write wire 44. Compared with the prior art using a bidirectional conductive selector such as a MOS element, the Schottky diode according to the present invention can greatly reduce the leakage current; and the write wire can be further formed on the insulating layer, which can further reduce the leakage current. For example, in this embodiment, the non-volatile In a preferred embodiment, the write conductive line 44 of the nonvolatile memory element 40 can be formed on an insulating layer 42, thereby providing better electrical isolation from other conductive regions. This provides a better insulation effect than conventional methods, thereby reducing leakage current during operation of the nonvolatile memory element 40. Fourth, the forward conduction voltage of a Schottky diode is lower than that of a PN diode (approximately 0.3V lower). Furthermore, generally speaking, the current required to write data to a nonvolatile memory element is higher than that required for a volatile memory element. Furthermore, at the same saturation current as a PN diode, the voltage drop across a Schottky diode is even lower (approximately 0.37V). Therefore, a nonvolatile memory element employing a Schottky diode can further reduce the operating voltage compared to a nonvolatile memory element employing a PN diode, thereby achieving the purpose of data writing. Furthermore, compared to a nonvolatile memory element employing a MOS element as a selector, the present invention achieves a greater reduction in operating voltage. Furthermore, when the present invention is applied to multiple Schottky diodes (described in detail later), it can replace bidirectional channels or be applied to multi-directional control (such as SOT-MRAM devices) to ensure that the currents in the bidirectional channels are approximately equal. Fifth, Schottky diodes have an extremely fast response time of approximately 100 ps, making them suitable for fast applications.

[0087] Regarding the fourth advantage of the present invention, using a Schottky diode as a selector for a non-volatile memory element can reduce the operating voltage. The details are as follows: First, the current formula of the PN diode is as follows:

[0088] J d =J ds (e Vd / nVt -1)

[0089] Where, Jd is the current flowing through the PN diode;

[0090] Jds is the saturation current of the PN diode, which is approximately 10 -11 ~10 -12 A;

[0091] Vd is the voltage across the PN diode when it is conducting, which is approximately 0.7V;

[0092] Vt is the thermal voltage, which is about 26mV at room temperature;

[0093] n is the ideality factor, which is approximately 1 to 2 for silicon.

[0094] Compared with the Schottky diode, the current formula of the Schottky diode is as follows:

[0095] J s =J ss (e Vd / nVt -1)

[0096] Where, Jd is the current flowing through the Schottky diode;

[0097] Jss is the saturation current of the Schottky diode, which is about 10 -5 A;

[0098] Vd is the voltage across the Schottky diode when it is conducting, which is approximately 0.3V;

[0099] Vt is the thermal voltage, which is about 26mV at room temperature;

[0100] n is the ideality factor, which is approximately 1 to 2 for silicon.

[0101] From the above formula, we can see that in addition to the fact that the voltage across the Schottky diode when it is turned on is about 0.4V lower than that across the PN diode when it is turned on, when Jd=Js, because Jss is about 10 of Jds 6 ~10 7 times, such as 10 6 Calculation shows that in order for a Schottky diode to achieve the same conduction current as a PN diode, the operating voltage can be lowered by 0.06*6=0.36V. Therefore, when a Schottky diode is used as a selector for a non-volatile storage element, the operating voltage can be reduced by 0.3V+0.36V=0.66V compared to when a PN diode is used as a selector for a non-volatile storage element.

[0102] Figure 4FA schematic diagram illustrates an embodiment of a nonvolatile memory device according to the present invention. As shown, the nonvolatile memory device 4 according to the present invention includes a nonvolatile memory element array 400 and a control circuit 410. The nonvolatile memory element array 400 is composed of a plurality of nonvolatile memory elements 40. The control circuit 410 is used to control the nonvolatile memory element array 400 and perform read and write operations on the nonvolatile memory elements 40. As described above, the non-volatile memory element includes: an insulating layer 42 for electrical insulation; a Schottky diode 43 formed in a single crystal silicon layer, a single crystal germanium layer, a hexagonal boron nitride layer, or a single crystal gallium arsenide layer on the insulating layer 42; a conductive selection wire 46 electrically connected to a front end 43a of the Schottky diode 43; a memory cell 45 located on the Schottky diode 43 and electrically connected to a rear end 43b of the Schottky diode 43; and a conductive selection wire 46 located on the memory cell 45 and electrically connected to the memory cell 45. When the non-volatile memory element 40 is selected for writing data, a first current I0 flows through the Schottky diode 43 to write the data into the memory cell 45.

[0103] Figure 5A and 5BA cross-sectional schematic diagram and a 3D schematic diagram of an embodiment of a nonvolatile memory element according to the present invention are shown. The nonvolatile memory element 50 according to the present invention is formed on a semiconductor substrate 51 and includes an insulating layer 52, a Schottky diode 53, a write conductive line 54, a memory cell 55, a select conductive line 56, and a connecting conductive unit 57. The insulating layer 52 is formed on the semiconductor substrate 51 and provides electrical insulation. Schottky diode 53 is formed in a single crystal silicon layer, single crystal germanium layer, hexagonal boron nitride layer, or single crystal gallium arsenide layer on insulating layer 52. Front end 53a is metal, forming a Schottky contact with the single crystal silicon layer, single crystal germanium layer, hexagonal boron nitride layer, or single crystal gallium arsenide layer. P-type impurities or N-type impurities (in this embodiment, N-type impurities) are implanted in the form of accelerated ions at rear end 53b (in the single crystal silicon layer, single crystal germanium layer, hexagonal boron nitride layer, or single crystal gallium arsenide layer), thereby forming Schottky diode 53. Write wire 54 is conductive and electrically connected to front end 53a (in this embodiment, a metal terminal) of Schottky diode 53. Schottky diode 53 is unidirectionally conductive during operation. The memory cell 55 is located on the Schottky diode 53 and is electrically connected to the back end 53b (in this embodiment, the N-type semiconductor end) of the Schottky diode 53. The select conductor 56 is conductive and located on and electrically connected to the memory cell 55. When the non-volatile memory element 50 is selected and data is written to the memory cell 55, a first current I0 flows through the Schottky diode 53 to write the data into the memory cell 55.

[0104] This embodiment and Figure 4A and 4B The embodiment shown is different in that, in this embodiment, the non-volatile memory element 50 further includes a connecting conductive unit 57, which is conductive and is used to electrically connect the memory cell 55 to the back end 53b of the Schottky diode 53 (the N-type end in this embodiment), wherein the connecting conductive unit 57 and the back end 53b of the Schottky diode 53 (the N-type semiconductor end in this embodiment) form an ohmic contact, which is well known to those skilled in the art and will not be described in detail here. In this embodiment, as Figure 5A and 5B As shown, the connecting conductive unit 57 is, for example but not limited to, stacked and connected to the rear end 53 b of the Schottky diode 53 , and the storage unit 55 is stacked and connected to the connecting conductive unit 57 .

[0105] Figure 6AA cross-sectional schematic diagram shows an embodiment of a non-volatile memory element according to the present invention. A non-volatile memory element 60 according to the present invention is formed on a semiconductor substrate 61. The non-volatile memory element 60 includes an insulating layer 62, a Schottky diode 63, a write conductor 64, a memory cell 65, a select conductor 66, and a connecting conductive unit 67. The insulating layer 62 is formed on the semiconductor substrate 61 and is electrically insulating. The Schottky diode 63 is formed in a single crystal semiconductor layer on the insulating layer 62. The material of the Schottky diode 63 may be silicon, germanium, hexagonal boron nitride, or gallium arsenide. The front end 63a is metal and forms a Schottky contact with the single crystal semiconductor layer. For example, in an ion implantation process, P-type impurities or N-type impurities (in this embodiment, N-type impurities) are implanted in the form of accelerated ions at the back end 63b (the single crystal semiconductor layer) to form the Schottky diode 63. A write conductor 64 is conductive and electrically connected to a front end 63a (a metal end in this embodiment) of a Schottky diode 63. Schottky diode 63 is unidirectionally conductive during operation. A memory cell 65 is located above Schottky diode 63 and electrically connected to a rear end 63b (an N-type semiconductor end in this embodiment) of Schottky diode 63 via a connecting conductive element 67. A select conductor 66 is conductive and located above and electrically connected to memory cell 65. When nonvolatile memory element 60 is selected and data is written to memory cell 65, a first current I0 flows through Schottky diode 63 to write the data into memory cell 65.

[0106] This embodiment and Figure 4A and 4B The embodiment shown differs in that, in this embodiment, the nonvolatile memory element 60 further includes a conductive connecting element 67, which is conductive and electrically connects the memory cell 65 to the rear end 63b of the Schottky diode 63 (in this embodiment, the N-type semiconductor end). The conductive connecting element 67 and the rear end 63b of the Schottky diode 63 (in this embodiment, the N-type semiconductor end) form an ohmic contact, which is well known to those skilled in the art and will not be described in detail here. The conductive connecting element 67 is, for example, a metal wire or a metal plug, and is used to electrically connect the memory cell 65 to the rear end 73b of the Schottky diode 63. Furthermore, in this embodiment, as shown in FIG6 , the write wire 64 is, for example, but not limited to, stacked on the insulating layer 62, and the Schottky diode 63 is stacked and connected to the write wire 64. For information on how to form a single crystal silicon layer on a metal layer, please refer to US 2010 / 0044670 A1.

[0107] Figure 6B A cross-sectional schematic diagram showing another embodiment of a nonvolatile memory element according to the present invention. Figure 6AThe key point is that in the non-volatile memory element 60 of this embodiment, the front end 63a of the Schottky diode 63 is an N-type semiconductor terminal, while the rear end 63b is a metal terminal located above the front end 63a (N-type semiconductor terminal) and electrically connected to the connecting conductive unit 67. During actual operation, the first current I0 flows downward into the N-type semiconductor and then into the write conductive line 64.

[0108] Figure 7A and 7B A cross-sectional schematic diagram and a 3D schematic diagram of an embodiment of a nonvolatile memory element according to the present invention are shown. A nonvolatile memory element 70 according to the present invention is formed on a semiconductor substrate 71 and includes an insulating layer 72, write conductive lines 741 and 742, Schottky diodes 731 and 732, a memory cell 75, a select conductive line 76, and a connecting conductive unit 77. The insulating layer 72 is formed on the semiconductor substrate 71 and provides electrical insulation. Schottky diodes 731 and 732 are formed in a single crystal semiconductor layer on the insulating layer 72. The front end 731a and the rear end 732b are metal, forming Schottky contacts with the single crystal semiconductor layer. For example, accelerated ions, such as N-type impurities (P-type impurities may also be implanted, but N-type impurities are preferred), are implanted into the rear end 731b and the front end 732a (the single crystal semiconductor layer) to form Schottky diodes 731 and 732.

[0109] In this embodiment, the Schottky diode 731 is stacked and connected on the insulating layer 72, and the front end 731a and the back end 731b of the Schottky diode 731 are, for example, but not limited to, adjacent in the lateral direction. The non-volatile memory element 70 of this embodiment further includes, for example, a Schottky diode 732 formed on the insulating layer 72, with the front end 732a formed in the aforementioned single crystal semiconductor layer. For example, in an ion implantation process, N-type impurities are implanted in the front end 732a in the form of accelerated ions, for example, but not limited to, N-type impurities, and the front end 732a forms a Schottky contact with the metal back end 732b, thereby forming the Schottky diode 732. In this embodiment, the Schottky diode 732 is stacked and connected on the insulating layer 72, and the front end 732a and the back end 732b of the Schottky diode 732 are, for example, but not limited to, adjacent in the lateral direction.

[0110] Write wire 741 is conductive and electrically connected to front end 731a of Schottky diode 731. In this embodiment, write wire 741 is, for example, but not limited to, laterally connected to front end 731a. Write wire 742 is conductive and electrically connected to front end 732a of Schottky diode 732. In this embodiment, write wire 742 is, for example, but not limited to, stacked and connected to front end 732a. Memory cell 75 is located on Schottky diodes 731 and 732, and is electrically connected to rear ends 731b and 732b of Schottky diodes 731 and 732 via connecting conductive element 77. In this embodiment, connecting conductive element 77 is laterally located between rear ends 731b and 732b. In this embodiment, select wire 76 is located on memory cell 75 and electrically connected to memory cell 75.

[0111] When the non-volatile memory element 70 is selected to be written with one data, a first current I0 flows through the Schottky diode 731 to write the data into the memory cell 75. When the non-volatile memory element 70 is selected to be written with another data, a second current I1 flows through the Schottky diode 732 to write the other data into the memory cell 75. It should be noted that the first current I0 and the second current I1 are in opposite directions when flowing through the memory cell 75.

[0112] It should be noted that in this embodiment, the direction of the Schottky junctions of the Schottky diodes 731 and 732 can be adjusted according to the circuit design and is not limited to the N-type semiconductor region on the left and the Schottky metal region on the right as shown in the figure; it can also be the Schottky metal region on the top and the N-type semiconductor region on the bottom; or the Schottky metal region on the bottom and the N-type semiconductor region on the top (i.e., arranged up and down, rather than horizontally). In a preferred embodiment, the write wires 741 and 742 are metal wires, which are formed of metal materials such as, but not limited to, aluminum, copper, or aluminum-copper alloy. In a preferred embodiment, the select wire and write wire described in the present invention are, for example, but not limited to, metal wires.

[0113] According to the present invention, in a preferred embodiment, as shown in this embodiment, the non-volatile memory element is formed on a semiconductor-on-insulator (SOI) substrate or a semiconductor-on-metal-insulator (SMOI) substrate. SOI substrates and SMOI substrates are well known to those skilled in the art and are not described in detail here.

[0114] It should be noted that, in different applications of non-volatile memory elements, the current path of the first current I0 may also be different. Figure 7A As shown, when the non-volatile memory element 70 is an RRAM element, the memory cell 75 is a resistance change region, and the current path of the first current I0 is as follows: Figure 7A As shown, for example, the first current I0 flows through Schottky diode 731, through connecting conductive element 77, and to memory cell 75, thereby changing the state of the material in memory cell 75. In this case, select conductor 76 is electrically connected to ground potential, for example. When non-volatile memory element 70 is a spin orbit torque (SOT) MRAM element, memory cell 75 is a magnetic region. The current path of first current I0, for example, flows through Schottky diode 731 to connecting conductive element 77, and does not flow through memory cell 75. This changes the magnetization direction of the electrode in memory cell 75, thereby changing the resistance of memory cell 75, thereby writing data into memory cell 75.

[0115] Figure 8A 、 8B 8C respectively show a cross-sectional schematic diagram, a 3D schematic diagram and an operation table of an embodiment of a non-volatile memory element according to the present invention. Figure 8A and 8B As shown, the nonvolatile memory element 80 according to the present invention is a three-terminal element formed on a semiconductor substrate 81. The nonvolatile memory element 80 includes an insulating layer 82, write conductors 841 and 842, Schottky diodes 831 and 832, a memory cell 85, a select conductor 86, and a connecting conductive unit 87. The three terminals of the nonvolatile memory element 80 are the write conductors 841 and 842 and the select conductor 86. The connecting conductive unit 87 includes a first portion 871, a second portion 872, and a third portion 873. The Schottky diode 831 includes a front end 831a and a rear end 831b. The Schottky diode 832 includes a front end 832a and a rear end 832b.

[0116] An insulating layer 82 is formed on the semiconductor substrate 81 and provides electrical insulation. Schottky diodes 831 and 832 are formed in a single crystal silicon layer on the insulating layer 82. Write conductors 841 and 842 are conductive and electrically connected to the front ends 831a (in this embodiment, the Schottky metal end) and 832a (in this embodiment, the N-type end) of the Schottky diodes 831 and 832, respectively. The Schottky diodes 831 and 832 are unidirectionally conductive. A memory cell 85 is located on the Schottky diodes 831 and 832 and is electrically connected to the rear ends 831b (in this embodiment, the N-type end) and 832b (in this embodiment, the Schottky metal end) of the Schottky diodes 831 and 832 via a connecting conductive unit 87. The connecting conductive unit 87 includes a first portion 871, a second portion 872, and a third portion 873. The select conductor 86 is conductive and located on the memory cell 85, electrically connected to the memory cell 85. When the non-volatile memory element 80 is selected and data is written into the memory cell 85, a first current I0 flows through the Schottky diode 831 to write the data into the memory cell 85. When the non-volatile memory element 80 is selected and another data is written into the memory cell 85, a second current I1 flows through the Schottky diode 832 to write the other data into the memory cell 85. In this embodiment, the first current I0 and the second current I1 flow through the memory cell 85 in opposite directions.

[0117] For example, if Figure 8C As shown in the operation table, when the nonvolatile memory element 80 is addressed and data representing "0" is written into the memory cell 85, for example, by electrically connecting the write conductor 841 to a write voltage Vw and the select conductor 86 to a ground potential, a first current I0 is generated. The first current I0 flows from the write conductor 841 through the Schottky diode 831 (with the Schottky metal end on top and the semiconductor N-type end on the bottom), then through the connecting conductive element 87 (the first portion 871 and the third portion 873), and then through the memory cell 85 to the select conductor 86. During this process, the crystal state of the material of the memory cell 85, the magnetization direction of the magnetic region, or the resistance value of the resistance change region are changed, thereby writing the data representing "0" into the memory cell 85. The write conductor 842 is electrically floating. In other non-selected nonvolatile memory elements 80, the write conductors 841 and 842 and the select conductor 86 are also electrically floating.

[0118] On the other hand, when the nonvolatile memory element 80 is addressed and data representing "1" is written into the magnetic region 85, for example, by electrically connecting the select conductor 86 to a write voltage Vw and the write conductor 842 to a ground potential, a second current I1 is generated. This current I1 flows from the select conductor 86 through the memory cell 85, then through the connecting conductive element 87 (the third portion 873 and the second portion 872), and then through the Schottky diode 832 (with the Schottky metal terminal on top and the semiconductor N-type terminal on the bottom), before reaching the write conductor 842. During this process, the crystallization state of the memory cell 85 material, the magnetization direction of the magnetic region, or the resistance value of the resistance change region are changed, thereby writing the data representing "1" into the memory cell 85. The write conductor 841 is electrically floating. In other non-selected nonvolatile memory elements 80, the write conductors 841 and 842 and the select conductor 86 are also electrically floating. The write voltage Vw is, for example, a positive voltage and is at least higher than the forward voltage of the Schottky diode, and enables current to flow from one end electrically connected to the write voltage Vw to the other end electrically connected to the ground potential.

[0119] In a preferred embodiment, when reading the data in the memory cell 85, for example, the selection wire 86 is electrically connected to the read voltage Vr, and the data in the memory cell 85 is determined to be "0" or "1" based on the voltage of the write wire 842.

[0120] Figure 8D A 3D schematic diagram showing an embodiment of a non-volatile memory element according to the present invention. The non-volatile memory element 80' according to the present invention is a three-terminal element formed on a semiconductor substrate 81', and the non-volatile memory element 80' includes an insulating layer 82', write conductors 841' and 842', Schottky diodes 831' and 832', a storage unit 85', a selection conductor 86', and a connecting conductive unit 87'. Among them, the three ends of the non-volatile memory element 80' are the write conductors 841' and 842' and the selection conductor 86'. Among them, the connecting conductive unit 87' includes a first part 871', a second part 872', and a third part 873'. The Schottky diode 831' includes a front end 831a' and a rear end 831b'. The Schottky diode 832' includes a front end 832a' and a rear end 832b'. This embodiment is different from Figure 8A and 8B The embodiment shown differs in that the write conductor 841' is laterally connected to the Schottky diode 831', and the front end 831a is laterally connected to the back end 831b. The write conductor 842' is laterally connected to the front end 832a' of the Schottky diode 832'.

[0121] Figure 9A 、 9B9C show a cross-sectional schematic diagram, a 3D schematic diagram and an operation table of an embodiment of a non-volatile memory element according to the present invention. Figure 9A and 9B As shown, a nonvolatile memory element 90 according to the present invention is formed on a semiconductor substrate 91. The nonvolatile memory element 90 includes an insulating layer 92, write conductive lines 942 and 971, Schottky diodes 931 and 932, a memory cell 95, a select conductive line 96, and connecting conductive units 94 and 972. This embodiment is applicable, for example but not limited to, a SOT-MRAM element or a bidirectional RRAM element.

[0122] An insulating layer 92 is formed on the semiconductor substrate 91 and provides electrical insulation. Write conductors 942 and 971 are conductive and electrically connected to the front end 931a (in this embodiment, the N-type terminal) of Schottky diode 931 and the front end 932a (in this embodiment, the Schottky metal terminal) of Schottky diode 932, respectively. Schottky diodes 931 and 932 are formed in a single crystal semiconductor layer on the insulating layer 92 and the first conductive layer 940, respectively. The material of the single crystal semiconductor layer may be silicon, germanium, hexagonal boron nitride, or gallium arsenide. Memory cell 95 is located above Schottky diodes 931 and 932 and is electrically connected to the rear ends 931b (in this embodiment, the Schottky metal terminal) and 932b (in this embodiment, the N-type terminal) of Schottky diodes 931 and 932, respectively. A select conductor 96 is located above memory cell 95 and is electrically connected to memory cell 95. When the nonvolatile memory element 90 is selected for writing a data, a first current I0 flows through the Schottky diode 931 to write the data into the memory cell 95. When the nonvolatile memory element 90 is selected for writing another data, a second current I1 flows through the Schottky diode 932 to write the other data into the memory cell 95. In this embodiment, the first current I0 and the second current I1 flow through the memory cell 95 in opposite directions.

[0123] In this embodiment, the connecting conductive unit 972 is used to electrically connect the memory cell 95 to the rear end 931b of the Schottky diode 931, wherein a portion of the connecting conductive unit 972 is stacked and connected to the rear end 931b. The connecting conductive unit 94 is used to electrically connect the connecting conductive unit 972 to the rear end 932b of the Schottky diode 932, thereby electrically connecting the memory cell 95 to the rear end 932b. The write conductive line 942 is stacked and connected to the insulating layer 92, and the front end 931a is stacked and connected to the first write conductive line 942, and the rear end 931b is stacked and connected to the front end 931a. The first portion 941 of the connecting conductive unit 94 is stacked and connected to the insulating layer 92, and the second portion 921 of the connecting conductive unit 94 is stacked and connected to the first portion 941, and another portion of the connecting conductive unit 972 is stacked and connected to the second portion 921. The rear end 932b of the Schottky diode 932 is stacked and connected to the first portion 941 , the front end 932a of the Schottky diode 932 is stacked and connected to the rear end 932b , and the write wire 971 is stacked and connected to the front end 932a .

[0124] The write conductor 942 and the first portion 941 are formed by the same metal deposition process step. The front end 931a and the rear end 932b are formed by the same ion implantation process step, or by the same epitaxial growth process step. The rear end 931b and the front end 932a are formed by the same metal deposition process step. The connecting conductive unit 972 and the write conductor 971 are formed, for example but not limited to, by the same metal deposition process step. For example, the write conductor 942 and the first portion 941 of the connecting conductive unit 94 are formed in the first conductive layer 940 and are conductive. The first conductive layer 940 is located on the insulating layer 92 and is connected to the insulating layer 92.

[0125] It should be noted that the so-called "same metal deposition process step" refers to a metal layer formed by a single metal deposition process step, and through the same lithography process step, using the same mask, the wiring design (layout) of the metal layer formed by the metal deposition process step is defined, and then through the same etching process step, the metal wires and areas are formed. The so-called "same ion implantation process step" refers to an impurity doping process step formed at the same depth of a semiconductor layer using the same single or single group (including multiple) of ion beams with the same species of impurities and the same acceleration voltage. Among them, the epitaxial process step refers to a process step of growing new crystals on the original single crystal silicon layer to form a new semiconductor layer, also known as an epitaxial growth process step. The above process steps are well known to those skilled in the art and will not be described in detail here.

[0126] For example, if Figure 9C As shown in the operation table, when the nonvolatile memory element 90 is addressed and data representing "0" is written into the memory cell 95, for example, the write conductor 942 is electrically connected to the ground potential and the select conductor 96 is electrically connected to the write voltage Vw, generating a first current I0. The first current I0 flows from the select conductor 96 through the memory cell 95, then through the connecting conductive element 972, and then through the Schottky diode 931 (with the N-type region at the bottom and the Schottky metal region at the top) to reach the write conductor 942. During this process, the crystal state of the material of the memory cell 95, the magnetization direction of the magnetic region, or the resistance value of the resistance change region are changed, thereby writing the data representing "0" into the memory cell 95. The write conductor 971 is electrically floating. In other non-selected nonvolatile memory elements 90, the write conductors 942 and 971 and the select conductor 96 are electrically floating, for example.

[0127] On the other hand, when the nonvolatile memory element 90 is addressed and data representing "1" is written into the memory cell 95, for example, by electrically connecting the select conductor 96 to the ground potential and the write conductor 971 to the write voltage Vw, a second current I1 is generated. This current flows from the write conductor 971 through the Schottky diode 932 (similar to the Schottky diode 931, with an N-type region at the bottom and a Schottky metal region at the top), then through the first portion 941 and the second portion 921 of the connecting conductive element 94, through the connecting conductive element 972, and finally through the memory cell 95 before reaching the select conductor 96. During this process, the crystal state of the material of the memory cell 95, the magnetization direction of the magnetic region, or the resistance value of the variable resistance region are changed, thereby writing the data representing "1" into the memory cell 95. The write conductor 942 is electrically floating. In other nonvolatile memory elements 90 that are not selected, the write conductors 942 and 971 and the select conductor 96 are electrically floating.

[0128] In a preferred embodiment, when reading the data in the storage cell 95, for example, the selection wire 96 is electrically connected to the read voltage Vr, and the data in the storage cell 75 is determined to be "0" or "1" based on the voltage of the write wire 971.

[0129] Furthermore, regarding how to form a single-crystal silicon layer on a metal layer, also known as the SMOI process, please refer to US2010 / 0044670A1. However, this application mentions that it is applicable to both PCRAM and MRAM devices. However, the claim that it is applicable to MRAM devices is incorrect because MRAM devices require currents in two different directions, which cannot be achieved with a single Schottky diode.

[0130] Figure 9DA schematic diagram shows an embodiment of a nonvolatile memory device according to the present invention. As shown, the nonvolatile memory device 9 according to the present invention includes a nonvolatile memory element array 900 and a control circuit 910. The nonvolatile memory element array 900 is composed of a plurality of nonvolatile memory elements 90. The control circuit 910 is used to control the nonvolatile memory element array 900 and perform read and write operations on the nonvolatile memory elements 90. As described above, the nonvolatile memory element includes: an insulating layer 92 for electrical insulation; Schottky diodes 931 and 932 formed in a single crystal silicon layer, a single crystal germanium layer, a hexagonal boron nitride layer, or a single crystal gallium arsenide layer on the insulating layer 92; conductive write wires 942 and 971 electrically connected to front ends 931a and 932a of the Schottky diode 931, respectively; a memory cell 95 located on the Schottky diodes 931 and 932, electrically connected to rear ends 931b and 932b of the Schottky diodes 931 and 932, respectively; and a conductive select wire 96 located on the memory cell 95 and electrically connected to the memory cell 95. When data is selected for writing into the nonvolatile memory element 90, a first current I0 or a second current I1 flows through the Schottky diode 931 or 932 to write the data into the memory cell 95.

[0131] Figure 10A A 3D schematic diagram showing an embodiment of a non-volatile memory element according to the present invention. Figure 10A As shown, the nonvolatile memory element 100 according to the present invention includes an insulating layer 102 , write conductive lines 1042 and 1071 , Schottky diodes 1031 and 1032 , a memory cell 105 , a selection conductive line 106 , and connecting conductive units 1072 and 104 .

[0132] This embodiment and Figure 9A and 9B The difference between the embodiment shown is that, in this embodiment, the N-type semiconductor region is stacked and connected to the Schottky metal region; Figure 9A and 9B In the illustrated embodiment, a Schottky metal region is stacked and connected to an N-type semiconductor region. This embodiment illustrates that, according to the present invention, an N-type semiconductor region can be stacked and connected to a Schottky metal region, or a Schottky metal region can be stacked and connected to an N-type semiconductor region. The conduction current direction of the Schottky diode needs to be adjusted according to the circuit's operational requirements.

[0133] Figure 10B A schematic diagram showing an embodiment of a non-volatile memory element according to the present invention is shown. This embodiment is intended to illustrate the arrangement and connection of multiple non-volatile memory elements. Figure 10BAs shown, the non-volatile memory devices 100 and 100 ′ share write conductive lines 1042 and 1071 , for example.

[0134] Figure 11A and 11B A 3D schematic diagram and an operation table showing an embodiment of a non-volatile memory element according to the present invention are shown. Figure 11A As shown, the non-volatile memory element 110 according to the present invention is a five-terminal element formed on a semiconductor substrate (not shown, please refer to other embodiments, such as Figure 9A The nonvolatile memory element 110 includes an insulating layer 112, write conductive lines 1141 and 1142, conductive lines 1172 and 1173, Schottky diodes 1131, 1132, 1133, and 1134, conductive plugs 1121 and 1122, a memory cell 115, a select conductive line 116, and connecting conductive units 1171, 1143, and 1144. The five terminals of the nonvolatile memory element 110 are the write conductive lines 1141 and 1142, conductive lines 1172 and 1173, and the select conductive line 106.

[0135] An insulating layer 112 is formed on a semiconductor substrate (not shown) and provides electrical insulation. Write conductors 1141 and 1142 and conductors 1072 and 1073 are electrically conductive. Schottky diodes 1131, 1132, 1133, and 1134 are unidirectional conductors, such as, but not limited to, the Schottky diodes shown in the figure. Memory cell 115 is located above Schottky diodes 1131, 1132, 1133, and 1134 and connecting conductive element 1171. Select conductor 116 is located above memory cell 115 and is electrically connected to memory cell 115. When a data is selected for writing into the nonvolatile memory element 110, a first current I0 flows from the write conductive line 1141 through the Schottky diode 1131, the connecting conductive unit 1171, the conductor plug 1121, the connecting conductive unit 1143, the Schottky diode 1132, and the conductive line 1172 to write the data into the memory cell 115. In this embodiment, the nonvolatile memory element 110 is, for example, but not limited to, a spin orbit torque (SOT) MRAM element. When another data is selected for writing into the nonvolatile memory element 110, a second current I1 flows through the Schottky diodes 1133 and 1134 to write the other data into the memory cell 115. This embodiment is, for example, but not limited to, an SOT-MRAM element.

[0136] For example, if Figure 11BAs shown in the operation table, when the non-volatile memory element 110 is addressed and data representing "0" is written into the memory cell 115, for example, the write conductive line 1141 is electrically connected to the write voltage Vw, and the conductive line 1172 is electrically connected to the ground potential, thereby generating a first current I0. The first current I0 flows from the write conductive line 1141, passes through the Schottky diode 1131 (with the Schottky metal region at the bottom and the N-type region at the top), then flows through the connecting conductive unit 1171, then flows through the conductor plug 1121, then flows through the connecting conductive unit 1143, then flows through the Schottky diode 1132, and reaches the conductive line 1172. During this process, the first current I0 flows through the connecting conductive unit 1171 electrically connected to the electrode in the memory cell 115, thereby changing the magnetization direction of the magnetic region, and writing the data representing "0" into the memory cell 115. The write conductive line 1142 and the conductive line 1173 are electrically floating with the select conductive line 116 . In other unselected nonvolatile memory elements 110 , the write conductive lines 1141 and 1142 , the conductive lines 1172 and 1173 and the select conductive line 116 are electrically floating, for example.

[0137] On the other hand, when the non-volatile memory element 110 is addressed and data representing "1" is written into the memory cell 115, for example, the write wire 1142 is electrically connected to the write voltage Vw, and the wire 1173 is electrically connected to the ground potential, thereby generating a second current I1. The second current I1 flows from the write wire 1142, passes through the Schottky diode 1133 (with the Schottky metal region at the bottom and the N-type region at the top), then flows through the connecting conductive unit 1171, then flows through the conductor plug 1122, then flows through the connecting conductive unit 1144, then flows through the Schottky diode 1134, and reaches the wire 1173. During this process, the second current I1 flows through the connecting conductive unit 1171 electrically connected to the electrode in the memory cell 115, but in a direction opposite to the current direction of the aforementioned process of writing data representing "0", thereby changing the magnetization direction of the magnetic region and writing data representing "1" into the memory cell 115. The write conductive line 1141 and the conductive line 1172 are electrically floating with the select conductive line 116 . In other unselected nonvolatile memory elements 110 , the write conductive lines 1141 and 1142 , the conductive lines 1172 and 1173 , and the select conductive line 116 are electrically floating, for example.

[0138] In a preferred embodiment, when reading data in the memory cell 115 , for example, the selection conductor 116 is electrically connected to the read voltage Vr, and the data in the memory cell 115 is determined to be “0” or “1” based on the voltage of the write conductor 1142 .

[0139] Figure 11CA schematic diagram shows an embodiment of a nonvolatile memory device according to the present invention. As shown, the nonvolatile memory device 11 according to the present invention includes a nonvolatile memory element array 1100 and a control circuit 1110. The nonvolatile memory element array 1100 is composed of a plurality of nonvolatile memory elements 110. The control circuit 1110 is used to control the nonvolatile memory element array 1100 and perform read and write operations on the nonvolatile memory elements 110. As described above, the nonvolatile memory element 110 includes an insulating layer 112, write conductors 1141 and 1142, conductors 1172 and 1173, Schottky diodes 1131, 1132, 1133, and 1134, conductor plugs 1121 and 1122, a memory cell 115, a select conductor 116, and connecting conductive units 1171, 1143, and 1144.

[0140] Figure 12 A 3D schematic diagram showing an embodiment of a non-volatile memory element according to the present invention. Figure 12 As shown, the non-volatile memory element 120 according to the present invention is a five-terminal element formed on a semiconductor substrate (not shown, please refer to other embodiments, such as Figure 9A The nonvolatile memory element 120 includes an insulating layer 122, write conductive lines 1241 and 1242, conductive lines 1272 and 1273, Schottky diodes 1231, 1232, 1233, and 1234, conductive lines 1221 and 1222, a memory cell 125, a select conductive line 126, and connecting conductive units 1271, 1243, and 1244. The five terminals of the nonvolatile memory element 120 are the write conductive lines 1241 and 1242, the conductive lines 1272 and 1273, and the select conductive line 116.

[0141] This embodiment and Figure 11A and 11B The difference between the embodiment shown is that, in this embodiment, the Schottky metal region is stacked and connected to the N-type semiconductor region; Figure 11A and 11B In the illustrated embodiment, an N-type semiconductor region is stacked and connected to a Schottky metal region. This embodiment illustrates that, according to the present invention, an N-type semiconductor region can be stacked and connected to a Schottky metal region, or a Schottky metal region can be stacked and connected to an N-type semiconductor region. The conduction current direction of the Schottky diode needs to be adjusted according to the circuit's operational requirements.

[0142] Figure 13A and 13B A 3D schematic diagram and a top view schematic diagram of an embodiment of a non-volatile memory element according to the present invention are shown. Figure 13A and 13BAs shown, the non-volatile memory element 130 according to the present invention is a five-terminal element formed on a semiconductor substrate (not shown, please refer to other embodiments, such as Figure 9A The nonvolatile memory element 130 includes an insulating layer 132, write conductive lines 1341 and 1342, conductive lines 1371, 1372, 1373, 1374, and 1375, Schottky diodes 1331, 1332, 1333, and 1334, conductive plugs 1321, 1322, 1323, 1324, 1325, 1326, 1327, and 1328, a memory cell 135, and a select conductive line 136. The five terminals of the nonvolatile memory element 130 are the write conductive lines 1341 and 1342, the conductive lines 1373 and 1375, and the select conductive line 136.

[0143] Insulating layer 132 is formed on a semiconductor substrate (not shown) and provides electrical insulation. Write conductors 1341 and 1342 and conductors 1371, 1372, 1373, 1374, and 1375 are electrically conductive. Schottky diodes 1331, 1332, 1333, and 1334 are unidirectional conductors, such as, but not limited to, the Schottky diodes shown in the figure. Memory cell 135 is located above Schottky diodes 1331, 1332, 1333, and 1334 and the connecting conductive element (conductors 1371, 1372, 1374, and 1375 and conductor plugs 1322, 1323, 1324, 1326, 1327, and 1328). Select conductor 136 is located above memory cell 135 and is electrically connected to memory cell 135. When a data is selected for writing into the nonvolatile memory device 130, a first current I0 flows from the write conductor 1341 through the Schottky diode 1331, the conductor plug 1322, the conductors 1371 and 1372, the conductor plug 1323, the Schottky diode 1332, the conductor plug 1324, and finally to the conductor 1373, thereby writing the data into the memory cell 135. In this embodiment, the nonvolatile memory device 130 is, for example but not limited to, a spin orbit torque (SOT) MRAM device. When another data is selected for writing into the nonvolatile memory device 130, a second current I1 flows through the Schottky diodes 1333 and 1334, thereby writing the other data into the memory cell 135.

[0144] For example, if Figure 13AAs shown, when the non-volatile memory element 130 is addressed and data representing "0" is written into the memory cell 135, for example, the write conductor 1341 is electrically connected to the write voltage Vw, and the conductor 1373 is electrically connected to the ground potential, thereby generating a first current I0. The first current I0 flows from the write conductor 1341, through the conductor plug 1321, and then through the Schottky diode 1331 (with the Schottky metal region on the top and the N-type region on the bottom), and then flows through the conductor plug 1322, and then flows through the conductors 1371 and 1372, and then flows through the conductor plug 1323, and then flows through the Schottky diode 1332, and then flows through the conductor plug 1324, and reaches the conductor 1373. In this process, the first current I0 flows through the conductor 1372 electrically connected to the electrode in the memory cell 135, thereby changing the magnetization direction of the magnetic region, and writing the data representing "0" into the memory cell 135. The write conductive line 1342 and the conductive line 1375 are electrically floating with the select conductive line 136. In other unselected nonvolatile memory elements 130, the write conductive lines 1341 and 1342, the conductive lines 1373 and 1375, and the select conductive line 136 are electrically floating.

[0145] On the other hand, when the non-volatile memory element 130 is addressed and data representing "1" is written into the memory cell 135, for example, the write conductor 1342 is electrically connected to the write voltage Vw, and the conductor 1375 is electrically connected to the ground potential, thereby generating a second current I1, which flows from the write conductor 1342, through the conductor plug 1325, and then through the Schottky diode 1333 (the Schottky metal region is on the top and the N-type region is on the bottom), and then flows through the conductor plug 1326, and then flows through the conductors 1374 and 1372, and then flows through the conductor plug 1327, and then flows through the Schottky diode 1334, and then flows through the conductor plug 1328, and reaches the conductor 1375. During this process, a second current I1 is passed through the conductive line 1372 electrically connected to the electrode in the memory cell 135 to change the magnetization direction of the magnetic region. During this process, the second current I1 is passed through the conductive line 1372 electrically connected to the electrode in the memory cell 135 in a direction opposite to the current used in the aforementioned process of writing data representing "0," thereby changing the magnetization direction of the magnetic region and writing data representing "1" into the memory cell 135. The write conductive line 1341, the conductive line 1373, and the select conductive line 136 are electrically floating. In other unselected non-volatile memory elements 130, the write conductive lines 1341 and 1342, the conductive lines 1373 and 1375, and the select conductive line 136 are electrically floating, for example.

[0146] Please also refer to Figure 13BSchematic top view, in this embodiment, in terms of the semiconductor manufacturing stage, the write conductors 1341 and 1342 and the select conductor 136 are all formed in the same metal deposition process step; the conductors 1371, 1372, 1373, 1374 and 1375 are all formed in the same metal deposition process step; in addition, the conductor plugs 1321, 1322, 1323, 1324, 1325, 1326, 1327 and 1328 are formed in the conductor plug process step.

[0147] like Figure 13B Schematic top view of a nonvolatile memory element 130, shown as a dashed black outline. This embodiment illustrates the nonvolatile memory element array layout in a nonvolatile memory device according to the present invention. It can be seen that compared to conventional nonvolatile memory devices, the nonvolatile memory device according to the present invention can significantly reduce circuit area.

[0148] The present invention has been described above with respect to a preferred embodiment, but the above is only to make it easier for those skilled in the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. For example, other process steps or structures can be added without affecting the main characteristics of the component. All of these can be derived by analogy based on the teachings of the present invention. In addition, the various embodiments described are not limited to individual applications, but can also be applied in combination, for example, but not limited to the use of two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any embodiment of the present invention does not necessarily achieve all purposes or advantages, and therefore, any of the claims should not be limited to this.

Claims

1. A non-volatile memory element, characterized in that: Include: an insulating layer for electrical insulation; a first Schottky diode comprising a first front end formed at least in part by a single crystal semiconductor layer on the insulating layer; a second Schottky diode comprising a second back end formed at least in part by the single crystal semiconductor layer on the insulating layer; a first write conductive wire having conductivity and electrically connected to the first front end of the first Schottky diode; a second write conductive wire having conductivity and electrically connected to a second front end of the second Schottky diode; a memory cell located on the first Schottky diode, the memory cell being electrically connected to a first rear end of the first Schottky diode; a selection wire, conductive, located on the memory cell and electrically connected to the memory cell; a first connecting conductive unit for electrically connecting the memory cell to the first rear end of the first Schottky diode, wherein a portion of the first connecting conductive unit is stacked and connected to the first rear end; and a second connecting conductive unit, configured to electrically connect the first connecting conductive unit to the second rear end of the second Schottky diode, so as to electrically connect the storage unit to the second rear end; When the non-volatile memory element is selected to write a first data, a first current flows through the first Schottky diode to write the first data into the memory cell; When the non-volatile memory element is selected to write a second data, a second current flows through the second Schottky diode to write the second data into the memory cell; wherein the first write conductive line is stacked and connected to the insulating layer, the first front end is stacked and connected to the first write conductive line, and the first rear end is stacked and connected to the first front end; wherein a first portion of the second connecting conductive unit is stacked and connected to the insulating layer, a second portion of the second connecting conductive unit is stacked and connected to the first portion, and another portion of the first connecting conductive unit is stacked and connected to the second portion; wherein the second rear end is stacked and connected to the first portion, the second front end is stacked and connected to the second rear end, and the second write wire is stacked and connected to the second front end; The first write conductive line and the first portion are formed by the same metal deposition process step.

2. The nonvolatile memory element according to claim 1, wherein The first Schottky diode is stacked and connected to the insulating layer.

3. The nonvolatile memory element according to claim 1, wherein: The first write conductive line is stacked and connected to the insulating layer, and the first Schottky diode is stacked and connected to the first write conductive line.

4. The nonvolatile memory element according to claim 1, wherein The second Schottky diode is stacked and connected to the insulating layer.

5. The nonvolatile memory element according to claim 1, wherein The second write conductive line is stacked and connected to the insulating layer, and the second Schottky diode is stacked and connected to the second write conductive line.

6. The nonvolatile memory element according to claim 1, wherein: The first connecting conductive unit is electrically connected between the first Schottky diode and the memory cell to electrically connect the memory cell to the first rear end of the first Schottky diode.

7. The nonvolatile memory element according to claim 1, wherein: The second connecting conductive unit is electrically connected between the second Schottky diode and the memory cell to electrically connect the memory cell to the second rear end of the second Schottky diode.

8. The nonvolatile memory element according to any one of claims 1 to 7, wherein: The non-volatile memory element is a phase change random access memory, a magnetoresistive random access memory or a resistive random access memory.

9. The nonvolatile memory element according to any one of claims 1 to 7, wherein: The first writing wire is a metal wire.

10. The nonvolatile memory element according to any one of claims 1 to 5, wherein: The first write conductive line and the second write conductive line are metal conductive lines.

11. The nonvolatile memory element according to any one of claims 1 to 7, wherein: The non-volatile memory element is formed on a semiconductor substrate on an insulating layer or a semiconductor substrate on an insulating layer-metal layer.

12. The nonvolatile memory element according to claim 1, wherein The first connecting conductive unit and the second writing conductive line are formed by the same metal deposition process step.

13. The nonvolatile memory element according to claim 1, wherein The material of the single crystal semiconductor layer can be silicon, germanium, hexagonal boron nitride or gallium arsenide.

14. A non-volatile storage device, characterized in that: Include: a non-volatile memory element array, comprising a plurality of non-volatile memory elements; as well as a control circuit for controlling the non-volatile memory element array to perform read and write operations on the non-volatile memory elements; The non-volatile storage element includes: an insulating layer for electrical insulation; a first Schottky diode comprising a first front end formed at least in part by a single crystal semiconductor layer on the insulating layer; a second Schottky diode comprising a second back end formed at least in part by the single crystal semiconductor layer on the insulating layer; a first write conductive wire having conductivity and electrically connected to the first front end of the first Schottky diode; a second write conductive wire having conductivity and electrically connected to a second front end of the second Schottky diode; a memory cell located on the first Schottky diode, the memory cell being electrically connected to a first rear end of the first Schottky diode; a selection wire, conductive, located on the memory cell and electrically connected to the memory cell; a first connecting conductive unit for electrically connecting the memory cell to the first rear end of the first Schottky diode, wherein a portion of the first connecting conductive unit is stacked and connected to the first rear end; and a second connecting conductive unit, configured to electrically connect the first connecting conductive unit to the second rear end of the second Schottky diode, so as to electrically connect the storage unit to the second rear end; When the non-volatile memory element is selected to write a first data, a first current flows through the first Schottky diode to write the first data into the memory cell; When the non-volatile memory element is selected to write a second data, a second current flows through the second Schottky diode to write the second data into the memory cell; wherein the first write conductive line is stacked and connected to the insulating layer, the first front end is stacked and connected to the first write conductive line, and the first rear end is stacked and connected to the first front end; wherein a first portion of the second connecting conductive unit is stacked and connected to the insulating layer, a second portion of the second connecting conductive unit is stacked and connected to the first portion, and another portion of the first connecting conductive unit is stacked and connected to the second portion; wherein the second rear end is stacked and connected to the first portion, the second front end is stacked and connected to the second rear end, and the second write wire is stacked and connected to the second front end; The first write conductive line and the first portion are formed by the same metal deposition process step.

15. The nonvolatile memory device according to claim 14, wherein: The first Schottky diode is stacked and connected to the insulating layer.

16. The nonvolatile memory device according to claim 14, wherein: The first write conductive line is stacked and connected to the insulating layer, and the first Schottky diode is stacked and connected to the first write conductive line.

17. The nonvolatile memory device according to claim 14, wherein: The second Schottky diode is stacked and connected to the insulating layer.

18. The nonvolatile memory device according to claim 14, wherein: The second write conductive line is stacked and connected to the insulating layer, and the second Schottky diode is stacked and connected to the second write conductive line.

19. The nonvolatile memory device according to claim 14, wherein: The first connecting conductive unit is electrically connected between the first Schottky diode and the memory cell to electrically connect the memory cell to the first rear end of the first Schottky diode.

20. The nonvolatile memory device according to claim 14, wherein: The second connecting conductive unit is electrically connected between the second Schottky diode and the memory cell to electrically connect the memory cell to the second rear end of the second Schottky diode. 21 . The nonvolatile memory device of claim 14 , wherein the nonvolatile memory element is a phase change random access memory, a magnetoresistive random access memory, or a resistive random access memory. 22 . The nonvolatile memory device of claim 14 , wherein a material of the single crystal semiconductor layer is silicon, germanium, hexagonal boron nitride, or gallium arsenide.

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