Semiconductor device

Abstract

Embodiments provide a semiconductor device with excellent reliability. The semiconductor device of the embodiments includes a semiconductor layer having an element region and an element separation region; a first insulating film provided on the semiconductor layer; a first electrode provided on the first insulating film and extending in a first direction; a second electrode provided on the semiconductor layer, arranged in a second direction intersecting the first direction, and extending in the first direction; a third electrode provided on the semiconductor layer, arranged in the second direction, and extending in the first direction; a second insulating film provided between the first insulating film and the semiconductor layer, sandwiching the third electrode in the second direction; a first field plate electrode provided on the first electrode and connected to the first electrode; a second field plate electrode provided on the first field plate electrode and connected to the second electrode; and a third field plate electrode provided on the third electrode and connected to the third electrode. The second insulating film extends from the element separation region to a portion of the element region.

Description

[0001] This application claims priority from Japanese Patent Application No. 2021-46675 (Filing date: March 19, 2021) as a base application. This application includes the entire contents of the base application by reference to the base application. TECHNICAL FIELD

[0002] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0003] A transistor, a diode, or the like semiconductor device is used in a circuit such as a switching power supply circuit, an inverter circuit, or the like. These semiconductor devices are required to have high withstand voltage and low on-resistance. Also, sometimes a field plate electrode is used in a semiconductor device in order to prevent concentration of an electric field. SUMMARY

[0004] Embodiments of the present application provide a semiconductor device with high reliability.

[0005] The semiconductor device of the embodiment has a semiconductor layer having an element region and an element separation region, a first insulating film provided on the semiconductor layer, a first electrode provided on the first insulating film and extending in a first direction, a second electrode provided on the semiconductor layer, arranged in a second direction intersecting the first direction and extending in the first direction, a third electrode provided on the semiconductor layer, arranged in the second direction and extending in the first direction, a second insulating film provided between the first insulating film and the semiconductor layer, sandwiching the third electrode in the second direction, a first field plate electrode provided on the first electrode and connected to the first electrode, a second field plate electrode provided on the first field plate electrode and connected to the second electrode, and a third field plate electrode provided on the third electrode and connected to the third electrode. The second insulating film extends from the element separation region to a part of the element region. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a schematic view of a semiconductor device of the embodiment.

[0007] Figures 2-12 is a schematic cross-sectional view of a semiconductor device of the embodiment.

[0008] Figures 13-29 is a process cross-sectional view of a semiconductor device of the embodiment.

[0009] Figure 30 is a schematic view of a semiconductor device of the embodiment.

[0010] Figure 31 、 Figure 32 is a schematic cross-sectional view of a semiconductor device of the embodiment. DETAILED DESCRIPTION

[0011] Hereinafter, an embodiment of the present application will be described with reference to the drawings. In the following description, like or similar components are designated by like or similar reference numerals, and description thereof will be omitted at times.

[0012] In the present specification, "nitride semiconductor layer" includes "GaN-based semiconductor". "GaN-based semiconductor" is a general term for gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), and semiconductors having intermediate compositions thereof.

[0013] In the present specification, "undoped" means that the impurity concentration is 2 x 10 16 cm -3 or less.

[0014] In the present specification, in order to express positional relationships of components and the like, the upward direction of the drawing is referred to as "up", and the downward direction of the drawing is referred to as "down". In the present specification, "up" and "down" are not necessarily terms expressing relationships with the direction of gravity.

[0015] The physical properties in the present specification are values in an atmosphere at 25°C.

[0016] (First Embodiment)

[0017] The semiconductor device of the first embodiment has a semiconductor element having a semiconductor layer, and a wiring layer on the semiconductor element. Hereinafter, a GaN-based semiconductor device will be described as an example, but the semiconductor element can also be a horizontal transistor other than a GaN-based semiconductor.

[0018] Figure 1 is a schematic view of the semiconductor device 100 of the first embodiment. Figures 2-12 is a schematic cross-sectional view of the semiconductor device 100 of the first embodiment. Figure 2 is a partial cross-sectional view of the A-A' cross section of Figure 1 Figure 3 is a partial cross-sectional view of the B-B' cross section of Figure 1 Figure 4 is a partial cross-sectional view of the C-C' cross section of Figure 1 Figure 5 is a partial cross-sectional view of the D-D' cross section of Figure 1 Figure 6 is a partial cross-sectional view of the E-E' cross section of Figure 1 Figure 7 is a partial cross-sectional view of the F-F' cross section of Figure 1 Figure 8 is a partial cross-sectional view of the G-G' cross section of Figure 1 Figure 9 is a partial cross-sectional view of the H-H' cross section of Figure 1 Figure 10 is​​​​​​​​Figure 1 A partial sectional view of the JJ′ section. Figure 11 yes Figure 1 A partial sectional view of the KK′ section. Figure 12 It includes Figure 2 A partial sectional view of the LL′ section. In the sectional view, the reference numerals of the object's parts (e.g., if...) are... Figure 3 The right side of the semiconductor device 100 indicates the cross-sectional position (e.g., if it is...). Figure 3 Then it is 100(AA′)).

[0019] Semiconductor device 100 is, for example, a HEMT (High Electron Mobility Transistor) using GaN-based semiconductors. Semiconductor device 100 contains component regions that operate as transistors and non-component regions that do not operate as transistors. In semiconductor device 100, Figure 1 The area defined by the dotted line in the center is the component area. Additionally, in the semiconductor device 100, there exists... Figure 1 The component separation area is sandwiched between the component areas defined by dotted lines.

[0020] Figure 1 The semiconductor device 100 includes a semiconductor layer 1, a first insulating film 2, a first electrode 3, a second electrode 4, a third electrode 5, a first field plate electrode 6, a second field plate electrode 7, a third field plate electrode 8, a second insulating film 11, a third insulating film 9, a fourth insulating film 10, and a component separation region 12.

[0021] Semiconductor layer 1 is stacked in the following order: substrate 1A, buffer layer 1B, channel layer 1C (first nitride semiconductor layer), and barrier layer 1D (second nitride semiconductor layer), and includes a device region and a device separation region 12. The device separation region 12 is provided from the surface of the barrier layer 1D of semiconductor layer 1. The areas of the channel layer 1C and the barrier layer 1D of semiconductor layer 1 where the device separation region 12 is not provided are the device regions.

[0022] The substrate 1A is formed of silicon (Si), for example. In addition to silicon, sapphire (Al2O3) or silicon carbide (SiC) can also be used, for example.

[0023] A buffer layer 1B is disposed on the substrate 1A. The buffer layer 1B has the function of mitigating the lattice mismatch between the substrate 1A and the channel layer 1C. The buffer layer 1B is, for example, made of aluminum gallium nitride (Al). W Ga 1-W The multilayer structure of N(0<W≤1) is formed.

[0024] The channel layer 1C is provided on the buffer layer 1B. The channel layer 1C is also referred to as an electron travel layer. The channel layer 1C is, for example, undoped aluminum gallium nitride (Al X Ga 1-X N (0 < X < 1). More specifically, the channel layer 1C is, for example, undoped gallium nitride (GaN). The thickness of the channel layer 1C is, for example, 0.1 μm or more and 10 μm or less. In an embodiment, the thickness is the length (height) of each component in the stacking direction of the channel layer 1C and the barrier layer 1D, that is, the third direction (Z direction), including the channel layer 1C.

[0025] The barrier layer 1D is provided on the channel layer 1C. The barrier layer 1D is also referred to as an electron supply layer. The band gap of the barrier layer 1D is larger than that of the channel layer 1C. The barrier layer 1D is, for example, undoped aluminum gallium nitride (Al Y Ga 1-Y N (0 < Y < 1, X < Y). More specifically, the barrier layer 1D is, for example, undoped Al 0.25 Ga 0.75 N. The thickness of the barrier layer 1D is, for example, 2 nm or more and 100 nm or less.

[0026] A heterojunction interface is formed between the channel layer 1C and the barrier layer 1D. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface, and becomes a carrier of the semiconductor device 100.

[0027] The element separation region 12 is a high-resistance region formed by ion implantation. The element separation region 12 is formed, for example, at least to the inside of the channel layer 1C. As the ion species for performing element separation, for example, nitrogen or argon or the like can be applied. In addition, the dose accompanying ion implantation is, for example, about 1 x 1013 14 (ions / cm 2 ). The acceleration energy for performing ion implantation is, for example, about 100 keV or more and 200 keV or less. The region in which the element separation region 12 is formed (the boundary between the element separation region 12 and the element region) can be confirmed by cross-sectional observation using a transmission electron microscope (TEM) or the like.

[0028] The first electrode 3 is a gate electrode having a plurality of gate fingers extending in the first direction (X direction). The gate fingers of the comb shape of the gate electrode 3 extend in the first direction, and the gate fingers are arranged in the second direction (Y direction). The gate electrode 3 is an electrode provided on the first insulating film 2 provided on the channel layer 1C and the barrier layer 1D. The gate electrode 3 is electrically connected to the channel layer 1C and the barrier layer 1D. The gate electrode 3 directly contacts the first insulating film 2, for example. The gate electrode 3 is provided between the second electrode 4 and the third electrode 5. The gate electrode 3 is connected to the first electrode pad (gate electrode pad) 3A or the first field plate electrode 6. In the case where the first field plate electrode 6 is connected to the first electrode pad 3A, the gate electrode 3 has only the shape of the gate finger portion, for example.

[0029] The first direction intersects the second direction and the third direction. The second direction intersects the first direction and the third direction. It is preferable that the first direction be orthogonal to the plane formed by the second direction and the third direction, the second direction be orthogonal to the plane formed by the first direction and the third direction, and the third direction be orthogonal to the plane formed by the first direction and the second direction.

[0030] The gate electrode 3 is titanium nitride (TiN), for example.

[0031] A gate insulating film serving as the first insulating film 2 is provided between the gate electrode 3 and the barrier layer 1D, and the semiconductor device 100 can be of the MIS (Metal Insulator Semiconductor) type HEMT. The gate insulating film 2 is provided between the second electrode 4 and the third electrode 5. The gate insulating film 2 is an oxide or a nitride oxide, for example. The gate insulating film 2 is silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide, silicon nitride oxide, or aluminum nitride oxide, for example. The gate insulating film 2 is a dense insulating film. The gate insulating film 2 is a denser insulating film than the second insulating film 11. It is preferable that the density of the gate insulating film 2 be 2 g / cm 3 The density of the gate insulating film 2 is 3.16 g / cm 3 The thickness of the gate insulating film 2 is 10 nm or more and 100 nm or less, for example.

[0032] It is preferable that the semiconductor device 100 include the first field plate electrode 6. By providing the field plate electrode, the concentration of the electric field to the electrode can be alleviated. Figure 1 The portion surrounded by the broken line in FIG. 1 represents the first field plate electrode 6. The first field plate electrode 6 is a gate field plate electrode connected to the gate electrode 3.

[0033] The gate field plate electrode 6 is provided on the gate electrode 3. The gate field plate electrode 6 is directly electrically connected to the gate electrode 3. The gate field plate electrode 6 includes, for example, a columnar portion which is in contact with the gate electrode 3 and a plate-shaped portion which is in contact with the columnar portion, and is provided with a step difference. The columnar portion is sandwiched by the plate-shaped portion and the gate electrode 3. The width of the plate-shaped portion of the gate field plate electrode 6 in the second direction is preferably longer than the width of the gate electrode 3 in the second direction. The width of the columnar portion of the gate field plate electrode 6 in the second direction is preferably shorter than the width of the gate electrode 3 in the second direction. Another gate field plate electrode not shown which is connected to the gate electrode 3 can be provided between the gate field plate electrode 6 and the third electrode 5. The end surface of the gate field plate electrode 6 (also including the gate field plate electrode not shown which is optionally used) on the third electrode 5 side is preferably located at a position closer to the second electrode 4 side than the end surface of the second field plate electrode 7 on the third electrode 5 side in the second direction.

[0034] The second electrode 4 is a source electrode having a plurality of gate fingers extending in the first direction. The gate fingers of the comb shape of the source electrode 4 extend in the first direction, and the gate fingers are arranged in the second direction (Y direction). The gate fingers of the source electrode 4 are sandwiched by the gate fingers of the gate electrode 3, for example. The source electrode 4 is provided on the semiconductor layer 1, and more specifically, on the channel layer 1C and the barrier layer 1D. The source electrode 4 is electrically connected to the channel layer 1C and the barrier layer 1D. The source electrode 4 is connected to a second electrode pad (source electrode pad) 4A, for example. In the case where the second field plate electrode 7 is connected to the second electrode pad 4A, the source electrode 4 has only the shape of the gate finger portion, for example.

[0035] The source electrode 4 is a metal electrode, for example. The source electrode 4 is an aluminum film containing 50 wt% or more of aluminum as a main component or a laminated structure of titanium (Ti) and aluminum (Al), for example. An ohmic contact is preferably provided between the source electrode 4 and the barrier layer 1D.

[0036] The semiconductor device 100 preferably includes the second field plate electrode 7. By providing the field plate electrode, the concentration of the electric field to the electrode can be alleviated. Figure 1 The portion surrounded by the double-dot chain line in FIG. 1 represents the second field plate electrode 7. The second field plate electrode 7 is a source field plate electrode which is connected to the source electrode 4. The source field plate electrode 7 is located above the source electrode 4, the gate electrode 3 which sandwiches the source electrode 4, and the gate field plate electrode 6 in a manner such that the source electrode 4 is located in the middle or substantially in the middle and covers the source electrode 4.

[0037] The third electrode 5 is a drain electrode having a plurality of gate fingers extending in the first direction (X direction). The gate fingers of the comb shape of the drain electrode 5 extend in the first direction, and the gate fingers are arranged in the second direction (Y direction). The gate fingers of the drain electrode 5 are reversed to the gate fingers of the source electrode 4, that is, the source electrode 4 is arranged opposite to the drain electrode 5. The drain electrode 5 is arranged on the channel layer 1C and the barrier layer 1D. The drain electrode 5 is electrically connected to the channel layer 1C and the barrier layer 1D. The drain electrode 5 is, for example, in contact with the barrier layer 1D. The drain electrode 5 is connected to a third electrode pad (drain electrode pad) 5A, for example, or the third field plate electrode 8 is connected to the third electrode pad 5A. In the case where the third field plate electrode 8 is connected to the third electrode pad 5A, the drain electrode 5 has only the shape of the gate finger portion, for example.

[0038] The drain electrode 5 is, for example, a metal electrode. The drain electrode 5 is, for example, an aluminum film containing 50 wt% or more of aluminum as a main component or a laminated structure of titanium (Ti) and aluminum (Al). It is preferable that the drain electrode 5 and the barrier layer 1D be in ohmic contact.

[0039] The distance between the source electrode 4 and the drain electrode 5 is, for example, 5 μm or more and 30 μm or less.

[0040] Further, it is also possible to have a configuration in which the source electrode 4 and the drain electrode 5 are in direct contact with the channel layer 1C.

[0041] The second insulating film 11 is an insulating film arranged between the gate electrode 3 and the semiconductor layer 1. The second insulating film 11 sandwiches the drain electrode 5 in the second direction. The second insulating film 11 is a buffer film. It is preferable that the buffer film 11 extend from the element separation region of the semiconductor layer 1 to a part of the element region. The buffer film 11 is arranged between the semiconductor layer 1 and the gate electrode 3 of the element separation region 12.

[0042] The buffer film 11 is, for example, an oxide or a nitride oxide. The buffer film 11 is, for example, silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide, silicon nitride oxide, or aluminum nitride oxide. The buffer film 11 is an insulating film having a low density. The buffer film 11 is an insulating film having a lower density than the gate insulating film 2. It is preferable that the density of the buffer film 11 be, for example, 2 g / cm 3 3 g / cm 3 3 g / cm 3 It is preferable that the density (g / m2) of the buffer film 11 be 95% or less of the gate insulating film 2. Further, the thickness of the buffer film 11 is thicker than that of the gate insulating film 2, and is, for example, 20 nm or more and 500 nm or less.

[0043] The third insulating film 9 is an interlayer insulating film. The third insulating film 9 is provided between the gate insulating film 2 and the fourth insulating film 10. The third insulating film 9 covers the gate electrode 3, the source electrode 4, and the drain electrode 5. The third insulating film 9 is, for example, an oxide or a nitride. The third insulating film 9 is, for example, silicon oxide (SiO2), silicon nitride (SiN), or a high-k material, or the like. As the high-k material, hafnium oxide (HfO2) can be given. The third insulating film 9 is a low-density insulating film. The third insulating film 9 is a low-density insulating film having a lower density than the gate insulating film 2. The density of the third insulating film 9 is preferably, for example, 2 g / cm 3 The density of the third insulating film 9 is preferably, for example, 2 g / cm 3 The density of the third insulating film 9 is preferably, for example, 2 g / cm 3 The density of the third insulating film 9 is preferably, for example, 2 g / cm 3 The density of the third insulating film 9 is preferably, for example, 2 g / cm 3 The density of the third insulating film 9 is preferably, for example, 2 g / cm 3 The density of the third insulating film 9 is preferably, for example, 2 g / cm

[0044] The fourth insulating film 10 is an interlayer insulating film. The fourth insulating film 10 is provided on the third insulating film 9. The fourth insulating film 10 covers the gate field plate electrode 6, the source electrode 4, and the drain electrode 5. The fourth insulating film 10 is, for example, an oxide or a nitride. The fourth insulating film 10 is, for example, silicon oxide (SiO2), silicon nitride (SiN), or a high-k material, or the like. As the high-k material, hafnium oxide (HfO2) or the like can be given. The fourth insulating film 10 is a low-density insulating film. The fourth insulating film 10 is a low-density insulating film having a lower density than the gate insulating film 2. The density of the fourth insulating film 10 is preferably, for example, 2 g / cm 3 The density of the third insulating film 9 is preferably, for example, 2 g / cm 3 The density of the third insulating film 9 is preferably, for example, 2 g / cm 3 The density of the third insulating film 9 is preferably, for example, 2 g / cm

[0045] The kind of element of the semiconductor layer 1, the semiconductor region, the element injected into the element separation region 12, and the element concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry), EDX (Energy Dispersive X-ray Spectroscopy). Also, the relative level of the element concentration can be determined from the level of the carrier concentration found by SCM (Scanning Capacitance Microscopy). Also, the distance such as the depth, the thickness, the width, and the interval of the impurity region can be found by SIMS. Also, the distance such as the depth, the thickness, the width, and the interval of the impurity region can be found by a comparison image of the SCM image and the atom probe image.

[0046] Next, the buffer film 11 and the layer and region located in the periphery thereof will be described. The buffer film 11 is mainly provided on the element separation region 12. At the boundary of the element region and the element separation region 12 of the semiconductor layer 1, the buffer film 11 is also provided in the vicinity of the drain electrode 5 and in a part of the element region. Also, at the boundary of the element region and the element separation region 12 of the semiconductor layer 1, the buffer film 11 is not provided on the element region side in the vicinity of the gate electrode 3. Also, at the boundary of the element region and the element separation region 12 of the semiconductor layer 1, there are a form in which the buffer film 11 is not provided on the element region side in the vicinity of the source electrode 4 and a form in which the buffer film 11 is provided in a part of the element region.

[0047] Figure 2 The cross-sectional view of FIG. 6A shows a cross section of the element region in which the buffer film 11 is not present. Also, Figure 3 The cross-sectional view of FIG. 6B shows a cross section of the element region close to the element separation region 12 in which the buffer film 11 exists sandwiching the drain electrode 5. The same cross section as that of Figure 3 continues until the boundary of the element region and the element separation region 12. If entering the element separation region 12, the buffer film 11 is not present on the lower surface side of the gate electrode 3 and on the side surface side of the source electrode 4. Figure 3 The element separation region 12 appears on the surface side of the semiconductor layer 1 in the cross-sectional view of FIG. 6C. Also, in the cross section further inside the element separation region 12, the buffer film 11 is provided on the lower surface side of the gate electrode 3 and on the side surface side of the source electrode 4.

[0048] The electric field tends to concentrate at the boundary between the device region and the device separation region 12 around the leading edge of the gate finger of the drain electrode 5. There is a concern that the semiconductor layer 1 may degrade due to the device separation region 12; the breakdown voltage of the semiconductor layer 1 itself may decrease near the device separation region 12 and the boundary between the device separation region 12 and the device region. If the device separation region 12 is formed using a gate insulating film 2, it would result in a configuration where the gate insulating film 2 is directly connected to the device separation region 12. However, since there is a concern that the gate insulating film 2 may also degrade due to the formation of the device separation region 12, the insulation of the gate insulating film 2 near the device region and the device separation region 12 may also decrease. Therefore, it is preferable to provide a buffer film 11 at the boundary between the device region and the device separation region 12 around the leading edge of the gate finger of the drain electrode 5 to improve the breakdown voltage of the insulating film on the semiconductor layer 1 and thus improve the reliability of the semiconductor device 100.

[0049] To improve the withstand voltage of areas where the electric field tends to concentrate, the following is preferred: Figure 3 As shown in the cross-sectional view, the buffer film 11 has a side surface that is in contact with the drain electrode 5, and the side surface of the buffer film 11 opposite to the side surface that is in contact with the drain electrode 5 is located in the second direction between the source field plate electrode 7 and the drain field plate electrode 8. Since the drain electrode 5 is not in contact with the semiconductor layer 1 through the buffer film 11, therefore... Figure 4 As shown in the cross-sectional view, the surface of the drain electrode 5 facing the semiconductor layer 1 on the component region and the component separation region 12 is not in contact with the buffer film 11, while the surface of the end of the drain electrode 5 in the first direction is in contact with the buffer film 11. Furthermore, the root portion of the gate finger of the drain electrode 5 is as follows... Figure 9 As shown in the cross-sectional view, no buffer film 11 is provided between the drain electrode 5 and the semiconductor layer 1.

[0050] like Figure 12 As shown in the cross-sectional view, the buffer film 11 has a protrusion with a width extending in a second direction from the side of the drain electrode 5 in the element region. Therefore, as... Figure 5 As shown in the cross-sectional view, the buffer film 11 is located near the boundary between the element region and the element separation region 12, and preferably also sandwiches the side of the drain electrode 5 in the element region. The buffer film 11 overlaps with the drain field plate electrode 8 in the third direction.

[0051] The preferred buffer film 11 sandwiches the drain electrode 5 and is located on the opposite side of the side that is in contact with the drain electrode 5. Figure 3 S1) is located in the second direction on the surface from the source field plate electrode 7 side of the drain field plate electrode 8. Figure 3 The surface from S2 in the middle to the drain field plate electrode 8 side of the source field plate electrode 7 ( Figure 3Between S1 and S2 (the surface of buffer membrane 11 is located on the side of the reference line of surface S2 (double-dotted line) along the arrow direction of the dashed line from the reference line (single-dotted line) of surface S2), the reference line of surface S3 is closer to the reference line of surface S2 than the reference line of surface S3 (double-dotted line). That is, preferably as follows Figure 5 , 6 As shown in the cross-sectional view of 11, the side of the buffer film 11 opposite to the side that is in contact with the drain electrode 5 sandwiches the drain electrode 5. The side opposite to the side that is in contact with the drain electrode 5 is located in the third direction at a position that does not overlap with the source field plate electrode 7 and does not overlap with the drain field plate electrode 8.

[0052] More specifically, the buffer film 11 preferably sandwiches the side opposite to the side where the drain electrode 5 is connected to the drain electrode 5. Figure 3 S1) is located in the second direction on the surface from the source field plate electrode 7 side of the drain field plate electrode 8. Figure 3 The buffer film 11 is located at a distance of 0.1 μm to 20 μm from the source field plate electrode 7 (in the direction of the dashed arrow) starting from the reference line (single-dotted line) of the S2 surface, which is closer to the reference line of the S2 surface than the reference line (double-dotted line) of the S3 surface, and exists at a distance of 0.1 μm to 20 μm from the reference line of the S2 surface towards the direction of the dashed arrow. If the side of the buffer film 11 opposite to the side that is in contact with the drain electrode 5 is located on the drain electrode 5 side in the second direction, the withstand voltage is easily reduced. In view of this, it is more preferable that the side of the buffer film 11 that is in contact with the drain electrode 5 and sandwiches the drain electrode 5 is located in the second direction at a distance of 0.1 μm to 12 μm from the surface of the drain field plate electrode 8 towards the source field plate electrode 7.

[0053] Preferably, in the portion of the buffer film 11 that sandwiches the drain electrode 5, the distance from the boundary between the element region and the element separation region 12 towards the element region (first direction) is 0.1 μm to 3.0 μm. Figure 5 The buffer film 11 is provided up to the position of L1. In the portion sandwiching the drain electrode 5, if the buffer film 11 is not provided on the side closer to the element region than the boundary between the element region and the element separation region 12, the withstand voltage is difficult to improve. Furthermore, if a large amount of buffer film 11 is formed in the element region, the actual element region becomes smaller. More preferably, the buffer film 11 is provided in the portion sandwiching the drain electrode 5 up to a position 0.1 μm to 0.5 μm away from the boundary between the element region and the element separation region 12 in the direction toward the element region (first direction).

[0054] From the viewpoint of expanding the effective element region, it is preferable that the buffer film 11 sandwich the drain electrode 5 at least on the element separation region 12, and that the buffer film 11 is not provided at a position of more than 3.0 μm from the boundary of the element region and the element separation region 12 toward the element region side in the first direction in the portion sandwiching the drain electrode 5 (the length protruding toward the element region side in the first direction from the boundary of the element region and the element separation region 12 in the portion sandwiching the drain electrode 5 by the buffer film 11 is at most 3.0 μm), and preferably at a position of more than 0.1 μm (the length protruding toward the element region side in the first direction from the boundary of the element region and the element separation region 12 in the portion sandwiching the drain electrode 5 by the buffer film 11 is at most 0.1 μm). In the portion where the buffer film 11 is not provided between the drain electrode 5 and the semiconductor layer 1, the drain electrode 5 is in contact with the semiconductor layer 1.

[0055] As shown in FIG. 10, it is preferable that the buffer film 11 is not provided between the semiconductor layer 1 and the gate insulating film 2 under the gate electrode 3 on the element region. Figure 7 Figure 7 is a cross-sectional view of a root portion of a gate finger of the gate electrode 3. Figure 10 is a cross-sectional view of a tip portion of a gate finger of the gate electrode 3.

[0056] Figure 7 As shown in FIG. 10, it is preferable that the buffer film 11 is not provided between the semiconductor layer 1 and the gate insulating film 2 under the gate electrode 3 on the element region.

[0057] In the case where the buffer film 11 is provided between the semiconductor layer 1 and the gate insulating film 2 under the gate electrode 3 on the element region, if the semiconductor device 100 is of the normally-off type, it is difficult for the semiconductor device 100 to break near the element separation region 12. If the gate cannot break due to the buffer film 11, it is preferable that the buffer film 11 is not provided under the gate electrode 3 on the element region because leakage will occur near the element separation region 12. From the viewpoint of improving the reliability of the semiconductor device 100 based on the above viewpoint, it is preferable that the buffer film 11 is not provided between the semiconductor layer 1 and the gate insulating film 2 under the gate electrode 3 from a position of 0.1 μm or more and 3.0 μm or less in the first direction on the element separation region 12 side from the boundary of the element region and the element separation region 12 (the distance of the buffer film 11 between the semiconductor layer 1 and the gate insulating film 2 under the gate electrode 3 from the boundary of the element region and the element separation region 12 is 0.1 μm or more and 3.0 μm or less in the first direction on the element separation region 12 side. Figure 7 ​The L2 is 0.1 μm or more and 3.0 μm or less. More preferably, it is not provided up to a distance of 0.1 μm or more and 0.5 μm or less (the distance from the boundary between the element region and the element separation region 12 to the buffer film 11 between the semiconductor layer 1 and the gate insulating film 2 below the gate electrode 3). Figure 7 (L2) is 0.1μm or more and 0.5μm or less.

[0058] Additionally, the buffer film 11 clamps at least the root and tip portions of the gate finger of the source electrode 4 in the element separation region 12. For example... Figure 8 , Figure 11 , Figure 12 As shown in the cross-sectional view, no buffer film 11 is provided between the source electrode 4 and the semiconductor layer 1 in the element separation region 12 of the semiconductor layer 1.

[0059] Next, refer to Figures 13 to 29 The manufacturing method of the semiconductor device 100 is described using a process cross-sectional view. The manufacturing method of the semiconductor device 100 includes: a step of forming a buffer film 11 on a semiconductor layer 1; a step of forming a device separation region 12 on the semiconductor layer 1 with the buffer film 11 in place; a step of patterning the buffer film 11; a step of forming a gate insulating film 2 on the patterned buffer film 11 and on the semiconductor layer 1; a step of forming a gate electrode 3 on the gate insulating film 2 and the buffer film 11; a step of forming a third insulating film 9; a step of opening an opening in the insulating film on the semiconductor layer 1; a step of forming a source electrode 4, a drain electrode 5, and a gate field plate electrode 6; a step of forming a fourth insulating film 10; a step of opening an opening in the insulating film on the source electrode 4 and the drain electrode 5; and a step of forming a source field plate electrode 7 and a drain field plate electrode 8. In the process cross-sectional view, the reference numerals for the components being examined (e.g., in...) are used to indicate the components being examined. Figure 15 The right side of component 101 indicates the cross-sectional position (e.g., in...). Figure 15 The value in the middle is 100 (LL′)).

[0060] First, the process of forming a buffer film 11 on the semiconductor layer 1 includes forming the buffer film 11 on the barrier layer 1D of the semiconductor layer 1, for example, by a PE-CVD (Plasma-Enhanced Chemical Vapor Deposition) method. Since the insulating film is formed by the PE-CVD method, a low-density insulating film can be formed.

[0061] The procedure of forming the element isolation region 12 in the semiconductor layer 1 with the buffer film 11 interposed includes ion implantation of nitrogen or argon to the surface of the semiconductor layer 1 of the member on which the buffer film 11 is formed. The ion implantation is performed from the surface of the buffer film 11. The acceleration energy of the ion implantation is, for example, about 100 keV or more and 200 keV or less. The buffer film 11 is deteriorated by the ion implantation, and the withstand voltage of the buffer film 11 itself is lowered. Since the element isolation region 12 is not formed with the gate insulating film 2 interposed, it is preferable that the deterioration of the gate insulating film 2 accompanying the formation of the element isolation region 12 does not occur from the viewpoint of improving the reliability of the semiconductor device 100.

[0062] By performing the procedure of forming the element isolation region 12 in the semiconductor layer 1 with the buffer film 11 interposed, it is possible to obtain Figure 13 、 14 the semiconductor device of the member 101 shown in the cross-sectional view of the procedure. Figure 13 is a partial cross-sectional view of the member 101 corresponding to the position of the A-A' cross section of Figure 1 . Figure 14 is a partial cross-sectional view of the member 101 corresponding to the positions of the C-C', D-D', E-E', F-F', and G-G' cross sections of Figure 1 . Figure 15 is a partial cross-sectional view of the member 101 corresponding to the position of the L-L' cross section of Figure 2 .

[0063] Since the member 101 is before the patterning of the buffer film 11, the buffer film 11 is formed on the entire surface of the semiconductor layer 1 including the element region as shown in Figure 15 . Therefore, the buffer film 11 is also provided in the partial cross-sectional view corresponding to the position of the A-A' cross section. Also, all the partial cross-sectional views corresponding to the positions of the C-C', D-D', E-E', F-F', and G-G' cross sections are the same.

[0064] The procedure of patterning the buffer film 11, for example, uses a mask to remove a part of the buffer film 11. On the element region, the buffer film 11 is removed on a part of the element isolation region 12 except for the portions sandwiching the drain electrode 5 and the portion on which the buffer film 11 is formed to sandwich the drain electrode 5, so that the buffer film 11 remains on the portions sandwiching the drain electrode 5 and the portion on which the buffer film 11 is formed to sandwich the drain electrode 5. By this patterning, the shape of the buffer film 11 constituting the portions sandwiching the drain electrode 5 and the gate electrode 3 side recesses is formed.

[0065] The patterning of the buffer film 11 is performed in a manner that the semiconductor layer 1 is exposed up to a portion of the element separation region 12 for the portion and the periphery thereof that form the gate electrode 3 and the source electrode 4, and the semiconductor layer 1 is exposed up to a portion of the element region for the portion and the periphery thereof that form the drain electrode 5.

[0066] The step of forming the gate insulating film 2 on the patterned buffer film 11 and the semiconductor layer 1 includes, for example, forming the gate insulating film 2 on the buffer film 11 and the semiconductor layer 1 exposed by the patterning by a LP-CVD (Low-Pressure Chemical Vapor Deposition) method. By this step, the component 102 shown in the cross-sectional view of the step Figures 16 to 19 is obtained. Since the buffer film 11 is patterned after the formation of the element separation region 12, the element separation region 12 is formed without the gate insulating film 2 therebetween, so that in the semiconductor device 100 manufactured thereby, defects due to ion implantation of the element separation region 12 do not occur in the gate insulating film 2, which is preferable from the viewpoint of the withstand voltage.

[0067] Figure 16 is a partial cross-sectional view of the component 102 corresponding to the position of the A-A' cross section of Figure 1 .

[0068] Figure 17 is a partial cross-sectional view of the component 102 corresponding to the position of the C-C', D-D' cross sections of Figure 1 .

[0069] Figure 18 is a partial cross-sectional view of the component 102 corresponding to the position of the E-E', F-F', G-G' cross sections of Figure 1 . Figure 19 is a partial cross-sectional view of the component 102 corresponding to the position of the L-L' cross section of Figure 2 .

[0070] For the portion that forms the gate electrode 3, the gate insulating film 2 is formed directly on the semiconductor layer 1 in order to expose the surface of the semiconductor layer 1 to a portion of the element separation region 12 by the patterning of the buffer film 11. In addition, the gate insulating film 2 is also formed on the buffer film 11 remaining due to the patterning.

[0071] Since the patterning of the buffer film 11 is performed as described above, the buffer film 11 of Figure 17 is replaced with the gate insulating film 2, and the position where the buffer film 11 is provided is processed as different from Figure 13 . Figure 17 and Figure 18 . Thus, the shape of the surface of the buffer film 11 and the gate insulating film 2 in the first direction and the second direction is processed as Figure 19The buffer film 11 is formed on the portion where the drain electrode 5 is formed as well as on the element region, and the peripheral portion of the gate electrode 3 and the source electrode 4 other than the portion where the drain electrode 5 is formed is formed without the buffer film 11 on the element region and is formed in a shape that is recessed from the boundary of the element region and the element separation region 12 toward the element separation region 12.

[0072] The step of forming the gate electrode 3 on the gate insulating film 2 and the buffer film 11 includes forming a metal of the gate electrode 3 on the gate insulating film 2 and the buffer film 11 and performing patterning of the gate electrode 3.

[0073] The step of forming the third insulating film 9 includes forming the third insulating film on the gate insulating film 2 and the gate electrode 3 of the portion where the gate electrode 3 is formed. Then, the portion where the gate insulating film 2 and the gate electrode 3 are covered with the third insulating film 9 is obtained. Figures 20 to 22 The step of the portion 103 shown in the cross-sectional view. The third insulating film 9 is formed by, for example, a PE-CVD (Plasma-Enhanced Chemical Vapor Deposition) method to form an insulating film with low density.

[0074] Figure 20 is a partial cross-sectional view of the portion 103 corresponding to the position of the A-A' cross section of Figure 1

[0075] Figure 21 is a partial cross-sectional view of the portion 103 corresponding to the position of the C-C', D-D' cross sections of Figure 1

[0076] Figure 22 is a partial cross-sectional view of the portion 102 corresponding to the position of the F-F' cross section of Figure 1 The portion 103 is formed with the third insulating film 9 on the gate insulating film 2 of the portion 102, for example, as shown in the cross-sectional view of

[0077] Figure 21 The portion where the gate electrode 3 is formed is sandwiched by the gate insulating film 2 and the third insulating film 9, as shown in the cross-sectional view of Figure 22

[0078] ​​​​The process of opening the insulating film on semiconductor layer 1 includes removing a portion of buffer film 11, gate insulating film 2, and third insulating film 9 to form source electrode 4, drain electrode 5, and gate field plate electrode 6. According to the shapes of source electrode 4 and drain electrode 5, a portion of buffer film 11, gate insulating film 2, and third insulating film 9 are removed such that the surface of semiconductor layer 1 is exposed. Similarly, according to the shape of the columnar portion of gate field plate electrode 6, a portion of third insulating film 9 is removed such that the surface of gate electrode 3 is exposed. Thus, it is possible to obtain a partially opened portion of the insulating film on semiconductor layer 1. Figures 23 to 26 The process cross-sectional view shows component 104.

[0079] Figure 23 Is with Figure 1 The position of section AA′ corresponds to a partial sectional view of component 104. Figure 24 Is with Figure 1 The position of the CC′ section corresponds to a partial sectional view of component 104. Figure 25 Is with Figure 1 The position of the GG′ section is equivalent to that of a partial sectional view of component 104. Figure 26 Is with Figure 2 The position of the LL′ section is a partial sectional view of component 104.

[0080] In the region of the columnar portion of component 104 forming the gate field plate electrode 6, such as Figure 23 As shown in the cross-sectional view, a groove is formed that extends along the first direction and exposes the gate electrode 3 on the bottom surface.

[0081] In the region of component 104 where the source electrode 4 and drain electrode 5 are formed, the buffer film 11 and gate insulating film 2 are removed from the element region to form a trench on the bottom surface exposing the semiconductor layer 1. Additionally, for example... Figure 24 As shown in the cross-sectional view, in the region of component 104 where the source electrode 4 and drain electrode 5 are formed, a portion of the buffer film 11 and the gate insulating film 2 remains, such that the leading edge portion of the gate finger on the element separation region 12 is in contact with the buffer film 11 and the gate insulating film 2. For example, as Figure 25 As shown in the cross-sectional view, the buffer film 11 and the gate insulating film 2 are removed such that the root portion of the gate finger is also in contact with the buffer film 11 and the gate insulating film 2, according to the shape of the source electrode 4 and the drain electrode 5. Figure 26 As shown in the cross-sectional view, the surface of the semiconductor layer 1 is exposed in the region of component 104 where the source electrode 4 and the drain electrode 5 are formed.

[0082] The process of forming the source electrode 4, the drain electrode 5, and the gate field plate electrode 6 includes forming a metal of the source electrode 4, the drain electrode 5, and the gate field plate electrode 6 on the portion of the third insulating film 9 opened in the process of opening the insulating film on the semiconductor layer 1 and patterning according to the shape of each electrode. Further, the component 105 shown in the process cross-sectional view of FIG. 10 is obtained. Figures 27 to 29

[0083] Figure 27 Figure 1 Figure 28 Figure 1 Figure 29 Figure 1 Figure 27 As shown in FIG. 11, the component 105 is formed with the source electrode 4, the drain electrode 5, and the gate field plate electrode 6 in the groove of the component 104. In the front end portion of the gate finger, for example, as shown in FIG. 12, the drain electrode 5 is also formed on a portion of the exposed semiconductor layer 1 and the third insulating film 9. Further, as shown in FIG. 13, for example, the source electrode 4 is formed on the exposed semiconductor layer 1. Figure 28 Figure 29

[0084] The process of forming the fourth insulating film 10 includes forming the fourth insulating film 10 on the source electrode 4, the drain electrode 5, the gate field plate electrode 6, and the third insulating film 9. The fourth insulating film 10 is formed as a low-density insulating film by, for example, a PE-CVD (Plasma-Enhanced Chemical Vapor Deposition) method.

[0085] The process of opening the insulating film on the source electrode 4 and the drain electrode 5 includes removing a portion of the fourth insulating film 10 for forming the source field plate electrode 7 and the drain field plate electrode 8. A portion of the fourth insulating film 10 is removed so as to expose the surface of the source electrode 4 in accordance with the shape of the columnar portion of the source field plate electrode 7, thereby forming a groove in which the source electrode 4 is exposed on the bottom surface. Further, a portion of the fourth insulating film 10 is removed so as to expose the surface of the drain electrode 5 in accordance with the shape of the columnar portion of the drain field plate electrode 8, thereby forming a groove in which the drain electrode 5 is exposed on the bottom surface.

[0086] ​​​​​​​​​The process of forming the source field plate electrode 7 and the drain field plate electrode 8 includes forming a metal of the source field plate electrode 7 and the drain field plate electrode 8 on the fourth insulating film 10 at the portion opened in the process of opening the insulating film on the source electrode 4 and the drain electrode 5, and patterning according to the shape of each electrode. For example, the semiconductor device 100 can be manufactured by the method described above.

[0087] (Second Embodiment)

[0088] The semiconductor device of the second embodiment is a modification of the semiconductor device 100 of the first embodiment. Figure 30 A schematic view of the semiconductor device 200 of the second embodiment is shown. Figure 31 is a partial cross-sectional view of the semiconductor device 200 corresponding to the position of the M-M' cross section of Figure 30 Figure 32 is a partial cross-sectional view of the semiconductor device 200 corresponding to the position of the N-N' cross section of Figure 31 Figure 30 The gate field plate electrode 6, the source field plate electrode 7, and the drain field plate electrode 8 not shown in FIG. 2 are connected to the gate electrode pad 3A, the source electrode pad 4A, and the drain electrode pad 5A, respectively.

[0089] The semiconductor device 200 of the second embodiment is a mode in which the gate electrode 3, the source electrode 4, and the drain electrode 5 are not comb-shaped and a plurality of gate finger electrodes are arranged.

[0090] In the semiconductor device 200 of the second embodiment, the buffer film 11 also performs the sandwiching action with the drain electrode 5 in the source electrode 4. By the source electrode 4 side also being sandwiched by the buffer film 11, the withstand voltage between the source and the drain is further improved, the withstand voltage of the semiconductor device 200 is improved, and the reliability of the device is further improved.

[0091] It is preferable that the buffer film 11 sandwiching the source electrode 4 be provided at a position in the first direction from the same position under the gate electrode 3 as the buffer film 11 to a position at a distance of 0.1 μm or more and 3.0 μm or less in the direction of the element region (the first direction) from the boundary of the element region and the element separation region 12, and it is preferable to be provided at a position at a distance of 0.1 μm or more and 0.5 μm or less.

[0092] Several embodiments of the present application have been described, but these embodiments are merely examples and are not intended to limit the scope of the application. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. For example, the constituent elements of one embodiment can be substituted or changed with the constituent elements of another embodiment. These embodiments and modifications are included in the scope, spirit of the application, and the range of the application recited in the technical solution and equivalents thereof.​​

Claims

1. A semiconductor device, characterized in that, have: The semiconductor layer has a component region and a component separation region; A first insulating film is disposed on the semiconductor layer; The first electrode is disposed on the first insulating film and extends along the first direction; The second electrode is disposed on the semiconductor layer, arranged in a second direction intersecting the first direction and extending along the first direction; The third electrode is disposed on the semiconductor layer, arranged in the second direction and extending along the first direction; The second insulating film is disposed between the first insulating film and the semiconductor layer, and the third electrode is sandwiched in the second direction; A first field plate electrode is disposed on the first electrode and connected to the first electrode; The second field plate electrode is disposed on the first field plate electrode and connected to the second electrode; as well as A third field plate electrode is disposed on and connected to the third electrode. The second insulating film extends from the component separation region to a portion of the component region. The second insulating film has a side that is in contact with the third electrode. The side of the second insulating film opposite to the side that is in contact with the third electrode is located between the second field plate electrode and the third field plate electrode in the second direction. The side of the second insulating film opposite to the side that is in contact with the third electrode is located in the second direction at a distance of 0.1 μm to 20 μm from the surface of the third field plate electrode toward the second field plate electrode.

2. The semiconductor device according to claim 1, characterized in that, The second insulating film is not disposed between the semiconductor layer on the element region and the first insulating film below the first electrode.

3. The semiconductor device according to claim 1 or 2, characterized in that, The second insulating film is disposed between the semiconductor layer and the first electrode in the component separation region.

4. The semiconductor device according to claim 1 or 2, characterized in that, The thickness of the second insulating film is above 20 nm and below 500 nm.

5. The semiconductor device according to claim 1 or 2, characterized in that, The density of the first insulating film (g / cm³) 3 The density of the second insulating film (g / cm³) 3 )high.

6. The semiconductor device according to claim 1 or 2, characterized in that, The second insulating film is provided in the portion sandwiching the third electrode, extending to a position 0.1 μm to 3.0 μm away from the boundary between the element region and the element separation region toward the element region. The second insulating film is not disposed between the semiconductor layer and the first insulating film below the first electrode, up to a position 0.1 μm to 3.0 μm away from the boundary between the element region and the element separation region towards the element separation region.

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