High-voltage level conversion circuit

Abstract

The present application provides a high-voltage level conversion circuit. The high-voltage level conversion circuit includes a latch module, a low-voltage transmission module, and a control module. The control module outputs a target signal in response to a low-voltage pulse signal output by the low-voltage transmission module to drive the latch module to continuously output the target signal. Thus, compared with the traditional method that requires continuous provision of a low-voltage domain signal to maintain driving, this solution uses a low-voltage pulse signal with a short duration. After successfully activating the control module, by using the holding output function of the latch module, continuous output of the target signal can still be achieved after the low-voltage pulse signal disappears.

Description

Technical Field

[0001] This application relates to the field of integrated circuit drive control, and particularly to a high-voltage level conversion circuit. Background Art

[0002] A level conversion circuit is used to achieve level conversion between two different power domains. In a half-bridge drive circuit, due to the difference in the reference ground terminal, a high-voltage level conversion circuit is required to convert the low-voltage domain into a high-voltage domain to obtain the desired drive signal.

[0003] The existing method is to use a low-voltage domain signal to control the conduction of a switching circuit, thereby turning on the high-voltage domain power supply connected to the switching circuit to achieve high-voltage level conversion through the high-voltage domain power supply. However, this method requires continuous supply of the low-voltage domain signal to maintain the conduction of the switching circuit, and thus maintain the output of the high-voltage level. Summary of the Invention

[0004] This application provides a high-voltage level conversion circuit that can maintain the output of the high-voltage level without continuously supplying the low-voltage domain signal.

[0005] A high-voltage level conversion circuit is applied to a floating power supply module, and the floating power supply module is used to provide a target signal. The high-voltage level conversion circuit includes:

[0006] A low-voltage transmission module for outputting a low-voltage pulse signal;

[0007] A latching module connected to the floating power supply module;

[0008] A control module is respectively connected to the low-voltage transmission module, the latching module, and the floating power supply module. The control module outputs the target signal in response to the low-voltage pulse signal to drive the latching module to continuously output the target signal.

[0009] In one embodiment, the low-voltage pulse signal includes a first pulse signal or a second pulse signal; the target signal includes a first level signal and a second level signal; the latching module includes a first electrode terminal and a second electrode terminal;

[0010] The control module includes:

[0011] A first switching unit, a first end of the first switching unit is connected to the floating power supply module, a second end of the first switching unit is connected to the low-voltage transmission module, a third end of the first switching unit is connected to the first electrode terminal, a fourth end of the first switching unit is connected to the second electrode terminal, the first switching unit outputs the first level signal to the first electrode terminal in response to the first pulse signal, and outputs the second level signal to the second electrode terminal; the latching module is further configured to continuously output the first level signal through the first electrode terminal, and continuously output the second level signal through the second electrode terminal;

[0012] A second switching unit, a first end of the second switching unit is connected to the floating power supply module, a second end of the second switching unit is connected to the low-voltage transmission module, a third end of the second switching unit is connected to the second electrode terminal, a fourth end of the second switching unit is connected to the first electrode terminal, the second switching unit outputs the first level signal to the second electrode terminal in response to the second pulse signal, and outputs the second level signal to the first electrode terminal; the latching module is further configured to continuously output the second level signal through the first electrode terminal, and continuously output the first level signal through the second electrode terminal.

[0013] In one embodiment, the first switching unit includes a field effect transistor PL1, a field effect transistor PL2, a field effect transistor PL3, a field effect transistor NL1, and a field effect transistor NL2;

[0014] The drain of the field effect transistor PL1, the gate of the field effect transistor PL1, the gate of the field effect transistor PL2, and the gate of the field effect transistor PL3 are commonly connected and connected to the low-voltage transmission module;

[0015] The source of the field effect transistor PL1, the source of the field effect transistor PL2, and the source of the field effect transistor PL3 are commonly connected and connected to the power supply terminal of the floating power supply module;

[0016] The drain of the field effect transistor PL2, the drain of the field effect transistor NL1, the gate of the field effect transistor NL1, and the gate of the field effect transistor NL2 are commonly connected;

[0017] The source of the field effect transistor NL1 and the source of the field effect transistor NL2 are commonly connected and connected to the ground terminal of the floating power supply module;

[0018] The drain of the field effect transistor PL3 is connected to the first electrode terminal; the drain of the field effect transistor NL2 is connected to the second electrode terminal.

[0019] In one embodiment, the high-voltage level conversion circuit further includes:

[0020] A first clamping unit, a first end of the first clamping unit is connected to a source electrode of the field effect transistor PL1, a second end of the first clamping unit is connected to a drain electrode of the field effect transistor PL1, and the first clamping unit is configured to clamp a voltage between the source electrode and the drain electrode of the field effect transistor PL1 within a first voltage threshold.

[0021] In one embodiment, the second switching unit includes a field effect transistor PR1, a field effect transistor PR2, a field effect transistor PR3, a field effect transistor NR1, and a field effect transistor NR2;

[0022] A drain electrode of the field effect transistor PR1, a gate electrode of the field effect transistor PR1, a gate electrode of the field effect transistor PR2, and a gate electrode of the field effect transistor PR3 are commonly connected and are connected to the low-voltage transmission module;

[0023] A source electrode of the field effect transistor PR1, a source electrode of the field effect transistor PR2, and a source electrode of the field effect transistor PR3 are commonly connected and are connected to a power supply terminal of the floating power supply module;

[0024] A drain electrode of the field effect transistor PR2, a drain electrode of the field effect transistor NR1, a gate electrode of the field effect transistor NR1, and a gate electrode of the field effect transistor NR2 are commonly connected;

[0025] A source electrode of the field effect transistor NR1 and a source electrode of the field effect transistor NR2 are commonly connected and are connected to a ground terminal of the floating power supply module;

[0026] A drain electrode of the field effect transistor PR3 is connected to the second electrode terminal; a drain electrode of the field effect transistor NR2 is connected to the first electrode terminal.

[0027] In one embodiment, the high-voltage level conversion circuit further includes:

[0028] A second clamping unit, a first end of the second clamping unit is connected to a source electrode of the field effect transistor PR1, a second end of the second clamping unit is connected to a drain electrode of the field effect transistor PR1, and the second clamping unit is configured to clamp a voltage between the source electrode and the drain electrode of the field effect transistor PR1 within a second voltage threshold.

[0029] In one embodiment, the latching module includes a field effect transistor PL4, a field effect transistor PR4, a field effect transistor NL3, and a field effect transistor NR3;

[0030] A source electrode of the field effect transistor PL4, a source electrode of the field effect transistor PR4, and a power supply terminal of the floating power supply module are commonly connected;

[0031] The drain of the field effect transistor PL4, the gate of the field effect transistor PR4, the drain of the field effect transistor NL3, and the gate of the field effect transistor NR3 are commonly connected to serve as the first electrode terminal;

[0032] The gate of the field effect transistor PL4, the drain of the field effect transistor PR4, the gate of the field effect transistor NL3, and the drain of the field effect transistor NR3 are commonly connected to serve as the second electrode terminal;

[0033] The source of the field effect transistor NL3, the source of the field effect transistor NR3, and the ground terminal of the floating power supply module are commonly connected.

[0034] In one embodiment, the high-voltage level conversion circuit further includes:

[0035] A first current biasing module, which is respectively connected to an external power supply terminal, the ground terminal of the floating power supply module, the source of the field effect transistor NL3, and the source of the field effect transistor NR3, and is used for generating a first bias current according to an external current provided by the external power supply terminal and outputting the first bias current to the source of the field effect transistor NL3 and the source of the field effect transistor NR3; wherein, the current value of the first bias current is less than the current value of the first pulse signal or the current value of the second pulse signal.

[0036] In one embodiment, the high-voltage level conversion circuit further includes:

[0037] A second current biasing module, which is respectively connected to the first current biasing module, the power supply terminal of the floating power supply module, the source of the field effect transistor PL4, and the source of the field effect transistor PR4;

[0038] The first current biasing module is further used for conducting the conductive path between the second current biasing module and the ground terminal of the floating power supply module to drive the second current biasing module to generate a second bias current, and the second current biasing module is further used for outputting the second bias current to the source of the field effect transistor PL4 and the source of the field effect transistor PR4; wherein, the current value of the second bias current is less than the current value of the first pulse signal or the current value of the second pulse signal.

[0039] In one embodiment, the high-voltage level conversion circuit further includes:

[0040] A filtering module, which includes a first input terminal and a second input terminal. The first input terminal is connected to the first electrode terminal, and the second input terminal is connected to the second electrode terminal. The filtering module is used for maintaining the output of the first level signal and the second level signal output by the latching module at the previous output moment if the voltage values of the first level signal and the second level signal output by the latching module are the same.

[0041] In one embodiment, the low-voltage transmission module includes a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a first delay unit, a second delay unit, a first NOR gate, a second NOR gate, a first NAND gate, a second NAND gate, a field-effect transistor NM4, and a field-effect transistor NM5;

[0042] The input terminal of the first NOT gate is used to receive an input signal, and the output terminal of the first NOT gate is respectively connected to the input terminal of the second NOT gate, the input terminal of the second delay unit, and the first terminal of the second NAND gate;

[0043] The output terminal of the second NOT gate is respectively connected to the first terminal of the first NAND gate and the input terminal of the first delay unit;

[0044] The input terminal of the third NOT gate is used to receive a control signal, and the output terminal of the third NOT gate is respectively connected to the control terminal of the first NOR gate and the control terminal of the second NOR gate;

[0045] The input terminal of the first NOR gate is connected to the output terminal of the first delay unit, and the output terminal of the first NOR gate is connected to the second terminal of the first NAND gate;

[0046] The input terminal of the second NOR gate is connected to the output terminal of the second delay unit, and the output terminal of the second NOR gate is connected to the second terminal of the second NAND gate;

[0047] The input terminal of the fourth NOT gate is connected to the output terminal of the first NAND gate, and the output terminal of the fourth NOT gate is connected to the gate of the field-effect transistor NM4;

[0048] The input terminal of the fifth NOT gate is connected to the output terminal of the second NAND gate, and the output terminal of the fourth NOT gate is connected to the gate of the field-effect transistor NM5;

[0049] The drain of the field-effect transistor NM4 is connected to the second terminal of the first switch unit, the drain of the field-effect transistor NM5 is connected to the second terminal of the second switch unit, and the source of the field-effect transistor NM4 and the source of the field-effect transistor NM5 are connected to the reference ground terminal.

[0050] The above high-voltage level conversion circuit includes a latch module, a low-voltage transmission module, and a control module. The control module outputs a target signal in response to the low-voltage pulse signal output by the low-voltage transmission module to drive the latch module to continuously output the target signal. Thus, compared with the traditional method that requires continuously providing a low-voltage domain signal to maintain the drive, this solution uses a low-voltage pulse signal with a short duration. After successfully activating the control module, by using the holding output function of the latch module, the continuous output of the target signal can still be achieved after the low-voltage pulse signal disappears. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 Structural block diagram of a high - voltage level conversion circuit according to an embodiment of the present application;

[0052] Figure 2 Structural block diagram of a high - voltage level conversion circuit according to another embodiment of the present application;

[0053] Figure 3 Circuit structure diagram of a high - voltage level conversion circuit according to an embodiment of the present application;

[0054] Figure 4 Circuit structure diagram of a high - voltage level conversion circuit according to another embodiment of the present application;

[0055] Figure 5 Circuit structure diagram of a high - voltage level conversion circuit according to another embodiment of the present application;

[0056] Figure 6 Circuit structure diagram of a high - voltage level conversion circuit according to another embodiment of the present application;

[0057] Figure 7 Circuit structure diagram of a high - voltage level conversion circuit according to another embodiment of the present application;

[0058] Figure 8 Circuit structure diagram of a high - voltage level conversion circuit according to another embodiment of the present application;

[0059] Figure 9 Circuit structure diagram of a high - voltage level conversion circuit according to another embodiment of the present application;

[0060] Figure 10 Signal waveform diagram according to an embodiment of the present application;

[0061] Figure 11 Circuit structure diagram of a high - voltage level conversion circuit according to another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0062] It should be understood that the specific embodiments described herein are only for explaining the present application and are not used to limit the present application.

[0063] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application belong to the scope of protection of the present application.

[0064] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture (as shown in the attached drawings). If the specific posture changes, the directional indications will also change accordingly. The connection described herein can be a direct connection or an indirect connection.

[0065] In addition, in the present application, descriptions such as "first" and "second" are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0066] Figure 1 A high-voltage level conversion circuit for an embodiment, the high-voltage level conversion circuit is applied to a floating power supply module 100, and the floating power supply module 100 is used to provide a target signal. The high-voltage level conversion circuit includes a low-voltage transmission module 110, a latch module 120, and a control module 130. The low-voltage transmission module 110 is used to output a low-voltage pulse signal; the latch module 120 is connected to the floating power supply module 100; the control module 130 is respectively connected to the low-voltage transmission module 110, the latch module 120, and the floating power supply module 100. The control module 130 outputs a target signal in response to the low-voltage pulse signal to drive the latch module 120 to continuously output the target signal.

[0067] It can be understood that the low-voltage pulse signal can be a short-pulse signal with a low voltage amplitude and a short pulse duration, which can be used as an instantaneous excitation for triggering the control module 130 to output a target signal. After the control module 130 responds to the low-voltage pulse signal, it outputs the target signal to the latch module 120. The latch module 120 receives the target signal output by the control module 130 on the one hand and the target signal directly output by the floating power supply module 100 on the other hand. The latch module 120 can respond to the target signal output by the control module 130 and then continuously output the target signal directly output by the floating power supply module 100 to achieve the latching of the target signal. Since the requirements for excitation are relatively low, a low-voltage pulse signal with a short pulse time can be used to achieve the continuous output of the target signal, thus reducing the overall requirements for the circuit.

[0068] Among them, the duration of the target signal output by the control module 130 can be the same as the pulse duration of the low-voltage pulse signal. When the low-voltage pulse signal disappears, the control module 130 also stops outputting the target signal. The target signal output by the control module 130 can be used as an excitation signal to trigger the latching module 120 to perform latching. When it disappears, due to the latching function of the latching module 120, the latching of the target signal can still be achieved.

[0069] In addition, the traditional level conversion method requires a pull-up resistor to be set between the high-voltage power supply and the switching circuit, and the high-voltage domain output is obtained after voltage division by the pull-up resistor. In this way, the pull-up resistor will continuously generate power consumption, resulting in a higher overall power consumption of the circuit; while the high-voltage level conversion circuit in this embodiment does not set additional energy-consuming components when realizing the high-voltage domain output, and the overall power consumption of the circuit is relatively low.

[0070] The control module 130 of the above high-voltage level conversion circuit responds to the low-voltage pulse signal output by the low-voltage transmission module 110 to output a target signal to drive the latching module 120 to continuously output the target signal. In this way, compared with the traditional method that requires continuous provision of a low-voltage domain signal to maintain driving, this solution uses a low-voltage pulse signal with a short duration. After successfully exciting the control module 130, by using the holding output function of the latching module 120, the continuous output of the target signal can still be achieved after the low-voltage pulse signal disappears, reducing the requirements for level conversion.

[0071] In one embodiment, as Figure 2As shown, the low-voltage pulse signal includes a first pulse signal or a second pulse signal; the target signal includes a first level signal and a second level signal; the latching module 120 includes a first electrode terminal Q1 and a second electrode terminal Q2; the control module 130 includes a first switching unit 131 and a second switching unit 132. The first end a1 of the first switching unit 131 is connected to the floating power supply module 100, the second end a2 of the first switching unit 131 is connected to the low-voltage transmission module 110, the third end a3 of the first switching unit 131 is connected to the first electrode terminal Q1, and the fourth end a4 of the first switching unit 131 is connected to the second electrode terminal Q2. The first switching unit 131 outputs a first level signal to the first electrode terminal Q1 and outputs a second level signal to the second electrode terminal Q2 in response to the first pulse signal; the latching module 120 is further configured to continuously output the first level signal through the first electrode terminal Q1 and continuously output the second level signal through the second electrode terminal Q2; the first end b1 of the second switching unit 132 is connected to the floating power supply module 100, the second end b2 of the second switching unit 132 is connected to the low-voltage transmission module 110, the third end b3 of the second switching unit 132 is connected to the second electrode terminal Q2, and the fourth end b4 of the second switching unit 132 is connected to the first electrode terminal Q1. The second switching unit 132 outputs a first level signal to the second electrode terminal Q2 and outputs a second level signal to the first electrode terminal Q1 in response to the second pulse signal; the latching module 120 is further configured to continuously output the second level signal through the first electrode terminal Q1 and continuously output the first level signal through the second electrode terminal Q2.

[0072] Specifically, when the low-voltage pulse signal includes the first pulse signal, the first switching unit 131 is turned on. On the one hand, the first switching unit 131 receives the target signal through the first end a1, where the target signal includes a first level signal and a second level signal. When the first pulse signal transmitted by the low-voltage transmission module 110 is received at the second end a2 of the first switching unit 131, the first switching unit 131 outputs a first level signal through the third end a3 and outputs a second level signal through the fourth end a4. Among them, when the first switching unit 131 receives the first pulse signal, since the pulse duration of the first pulse signal is short, the duration of the first level signal and the second level signal output by the first switching unit 131 is also short. When the first pulse signal disappears, the first switching unit 131 also stops outputting the first level signal and the second level signal. On the other hand, the latching module 120 directly receives the target signal output by the floating power supply module 100, and the target signal includes a first level signal and a second level signal, which can be provided by the power supply terminal and the ground terminal of the floating power supply module 100 respectively.

[0073] After the first electrode terminal Q1 of the latch module 120 receives the first level signal output by the first switch unit 131 and the second electrode terminal Q2 receives the second level signal output by the first switch unit 131, on the one hand, the latch module 120 can directly output the two level signals through the two electrode terminals. On the other hand, the latch module 120 is simultaneously excited by the two level signals, latches the first level signal and the second level signal provided by the floating power supply module 100. When the first switch unit 131 stops outputting the two level signals, the latch module 120 continuously outputs the first level signal provided by the floating power supply module 100 through the first electrode terminal Q1, and simultaneously continuously outputs the second level signal provided by the floating power supply module 100 through the second electrode terminal Q2. In this way, only a short pulse is needed to trigger to achieve continuous output of the signal.

[0074] Similarly, when the low voltage pulse signal includes the second pulse signal, the second switch unit 132 is turned on. On the one hand, the second switch unit 132 receives the target signal through the first terminal b1, where the target signal includes the first level signal and the second level signal. When the second pulse signal transmitted by the low voltage transmission module 110 is received at the second terminal b2 of the second switch unit 132, the second switch unit 132 outputs the first level signal through the third terminal b3 and simultaneously outputs the second level signal through the fourth terminal b4. Among them, when the second switch unit 132 receives the second pulse signal, since the pulse duration of the second pulse signal is short, the duration of the first level signal and the second level signal output by the second switch unit 132 is also short. When the second pulse signal disappears, the second switch unit 132 also stops outputting the first level signal and the second level signal. On the other hand, the latch module 120 directly receives the target signal output by the floating power supply module 100, and the target signal includes the first level signal and the second level signal.

[0075] After the first electrode terminal Q1 of the latch module 120 receives the second level signal output by the second switch unit 132 and the second electrode terminal Q2 receives the first level signal output by the second switch unit 132, on the one hand, the latch module 120 can directly output the two level signals through the two electrode terminals. On the other hand, the latch module 120 is simultaneously excited by the two level signals, latches the first level signal and the second level signal provided by the floating power supply module 100. When the second switch unit 132 stops outputting the two level signals, the latch module 120 continuously outputs the second level signal provided by the floating power supply module 100 through the first electrode terminal Q1, and simultaneously continuously outputs the first level signal provided by the floating power supply module 100 through the second electrode terminal Q2. In this way, only a short pulse is needed to trigger to achieve continuous output of the signal.

[0076] Among them, the first electrode terminal Q1 and the second electrode terminal Q2 of the latch module 120 can be respectively one of the positive terminal and the negative terminal, and the first level signal and the second level signal can be respectively one of the low level and the high level. For example, when the first level signal is the low level and the second level signal is the high level, the first electrode terminal Q1 outputs the first level signal as the negative terminal, and the second electrode terminal Q2 outputs the second level signal as the positive terminal.

[0077] In one embodiment, the structures of the first switch unit 131 and the second switch unit 132 can be the same, that is, their response conditions are also the same. At this time, the low-voltage transmission module 110 can be provided with two output terminals to respectively transmit the first pulse signal to the first switch unit 131 and transmit the second pulse signal to the second switch unit 132. In another embodiment, the structures of the first switch unit 131 and the second switch unit 132 can also be different, that is, their response conditions are also different. At this time, the low-voltage transmission module 110 can be provided with one output terminal to simultaneously transmit the first pulse signal or the second pulse signal to the first switch unit 131 and the second switch unit 132. Since the first switch unit 131 only responds to the first pulse signal and the second switch unit 132 only responds to the second pulse signal, at most only one of the first switch unit 131 and the second switch unit 132 is turned on at the same moment.

[0078] In the above embodiment, the control module 130 can realize the positive and negative output of the two electrode terminals of the latch module 120 by setting the first switch unit 131 and the second switch unit 132 and selectively turning on one of the switch units. The structure is simple and easy to implement.

[0079] In one embodiment, as Figure 3 shown, the first switch unit 131 includes a field effect transistor PL1, a field effect transistor PL2, a field effect transistor PL3, a field effect transistor NL1, and a field effect transistor NL2. The drain of the field effect transistor PL1, the gate of the field effect transistor PL1, the gate of the field effect transistor PL2, and the gate of the field effect transistor PL3 are commonly connected and connected to the low-voltage transmission module 110. The source of the field effect transistor PL1, the source of the field effect transistor PL2, and the source of the field effect transistor PL3 are commonly connected and connected to the power supply terminal U1 of the floating power supply module 100. The drain of the field effect transistor PL2, the drain of the field effect transistor NL1, the gate of the field effect transistor NL1, and the gate of the field effect transistor NL2 are commonly connected. The source of the field effect transistor NL1 and the source of the field effect transistor NL2 are commonly connected and connected to the ground terminal U2 of the floating power supply module 100. The drain of the field effect transistor PL3 is connected to the first electrode terminal. The drain of the field effect transistor NL2 is connected to the second electrode terminal.

[0080] Among them, the power supply terminal U1 of the floating power supply module 100 can output a first-level signal, and the power supply terminal U2 of the floating power supply module 100 can output a second-level signal; the field effect transistors PL1, PL2, and PL3 can be P-type field effect transistors, and the field effect transistors NL1 and NL2 can be N-type field effect transistors. When the drain of the field effect transistor PL1, as the second terminal of the first switching unit 131, receives a first pulse signal, since the drain of the field effect transistor PL1 is connected to its gate, and the gates of the field effect transistors PL2 and PL3, the first pulse signal will also be transmitted to the gates of the field effect transistors PL1, PL2, and PL3. The sources of the field effect transistors PL1, PL2, and PL3 are connected to the power supply terminal U1, and the voltage value of the first-level signal is greater than the voltage value of the first pulse signal. Therefore, the voltage at the source of each field effect transistor is greater than the voltage at its gate, and the field effect transistors PL1, PL2, and PL3 are all turned on, and the first-level signal of the power supply terminal U1 is transmitted to the first electrode terminal; at the same time, when the field effect transistor PL2 is turned on, the first-level signal is transmitted to the drain of the field effect transistor NL1, and then transmitted to the gates of the field effect transistors NL1 and NL2. The sources of the field effect transistors NL1 and NL2 are connected to the ground terminal U2. Since the voltage value of the first-level signal is greater than the voltage value of the second-level signal, the voltage at the gates of the field effect transistors NL1 and NL2 is greater than the voltage at their sources, and the field effect transistors NL1 and NL2 are turned on, and the second-level signal of the ground terminal is transmitted to the second electrode terminal.

[0081] In one embodiment, the high-voltage level conversion circuit further includes a first clamping unit 141. As Figure 3 shown, the first end of the first clamping unit 141 is connected to the source of the field effect transistor PL1, and the second end of the first clamping unit 141 is connected to the drain of the field effect transistor PL1. The first clamping unit 141 is used to clamp the voltage between the source and the drain of the field effect transistor PL1 within a first voltage threshold.

[0082] Among them, the first clamping unit 141 may include a Schottky diode. The cathode of the Schottky diode is used as the first end of the first clamping unit 141, and the anode is used as the second end of the first clamping unit 141. When the voltage between the source and the drain of the field effect transistor PL1 exceeds the first voltage threshold, the Schottky diode is reversely broken down, and the voltage across it is then maintained at a specific voltage value. In this way, it can be ensured that the voltage between the source and the drain of the field effect transistor PL1 does not exceed the first voltage threshold, thereby ensuring that the field effect transistor PL1 is not broken down. The number of Schottky diodes can be set to multiple, for example, the diodes N1 and N2 in Figure 3 wherein the two diodes are connected in series. Figure 3Only the circuit connection when the first clamping unit 141 includes two Schottky diodes is shown exemplarily. The specific number of Schottky diodes can be determined according to the source-drain voltage of the field effect transistor PL1 expected after breakdown. In addition, the first clamping unit 141 may further include a resistor R1. One end of the resistor R1 is connected to the cathode of the diode N2, and the other end of the resistor R1 is connected to the source of the field effect transistor PL1.

[0083] It can be understood that since the source of the field effect transistor PL1 is commonly connected to the source of the field effect transistor PL2, the source of the field effect transistor PL3, and the power supply terminal, the first end of the first clamping unit 141 is also connected to the source of the field effect transistor PL2, the source of the field effect transistor PL3, and the power supply terminal. Similarly, the second end of the first clamping unit 141 is also connected to the gate of the field effect transistor PL1, the gate of the field effect transistor PL2, and the gate of the field effect transistor PL3.

[0084] In one embodiment, the high-voltage level conversion circuit may further include a resistor R2 and a resistor R3, as Figure 3 shown, where the resistor R2 and the resistor R3 are connected in series between the source and the gate of the field effect transistors PL1, PL2, and PL3, and are used to effectively turn off the three field effect transistors when the first pulse signal is not received. In addition, the high-voltage level conversion circuit may further include a resistor R7, which is used to effectively turn off the field effect transistors NL1 and NL2 when the first pulse signal is not received.

[0085] In one embodiment, as Figure 3 shown, the second switch unit 132 includes field effect transistors PR1, PR2, PR3, NR1, and NR2; the drain of the field effect transistor PR1, the gate of the field effect transistor PR1, the gate of the field effect transistor PR2, and the gate of the field effect transistor PR3 are commonly connected and are connected to the low-voltage transmission module 110; the source of the field effect transistor PR1, the source of the field effect transistor PR2, and the source of the field effect transistor PR3 are commonly connected and are connected to the power supply terminal of the floating power supply module 100; the drain of the field effect transistor PR2, the drain of the field effect transistor NR1, the gate of the field effect transistor NR1, and the gate of the field effect transistor NR2 are commonly connected; the source of the field effect transistor NR1 and the source of the field effect transistor NR2 are commonly connected and are connected to the ground terminal of the floating power supply module 100; the drain of the field effect transistor PR3 is connected to the second electrode terminal; the drain of the field effect transistor NR2 is connected to the first electrode terminal.

[0086] Among them, the power supply terminal U1 of the floating power supply module 100 can output a first level signal, and the power supply terminal U2 of the floating power supply module 100 can output a second level signal; the field effect transistors PR1, PR2, and PR3 can be P-type field effect transistors, and the field effect transistors NR1 and NR2 can be N-type field effect transistors. When the drain of the field effect transistor PR1, as the second terminal of the second switching unit 132, receives the second pulse signal, since the drain of the field effect transistor PR1 is connected to its gate, and the gates of the field effect transistors PR2 and PR3, the second pulse signal will also be transmitted to the gates of the field effect transistors PR1, PR2, and PR3. The sources of the field effect transistors PR1, PR2, and PR3 are connected to the power supply terminal U1, and the voltage value of the first level signal is greater than the voltage value of the second pulse signal. Therefore, the voltage at the source of each field effect transistor is greater than the voltage at its gate, and the field effect transistors PR1, PR2, and PR3 are all turned on, and the first level signal of the power supply terminal U1 is transmitted to the second electrode terminal; at the same time, when the field effect transistor PR2 is turned on, the first level signal is transmitted to the drain of the field effect transistor NR1, and then transmitted to the gates of the field effect transistors NR1 and NR2. The sources of the field effect transistors NR1 and NR2 are connected to the ground terminal U2. Since the voltage value of the first level signal is greater than the voltage value of the second level signal, the voltage at the gates of the field effect transistors NR1 and NR2 is greater than the voltage at their sources, and the field effect transistors NR1 and NR2 are turned on, and the second level signal of the ground terminal is transmitted to the first electrode terminal.

[0087] In one embodiment, the high-voltage level conversion circuit further includes a second clamping unit 142, as Figure 3 shown, the first end of the second clamping unit 142 is connected to the source of the field effect transistor PR1, and the second end of the second clamping unit 142 is connected to the drain of the field effect transistor PR1. The second clamping unit 142 is used to clamp the voltage between the source and the drain of the field effect transistor PR1 within a second voltage threshold.

[0088] Among them, the second clamping unit 142 may include a Schottky diode. The cathode of the Schottky diode is used as the first end of the second clamping unit 142, and the anode is used as the second end of the second clamping unit 142. When the voltage between the source and the drain of the field effect transistor PR1 exceeds the second voltage threshold, the Schottky diode is reversely broken down, and the voltage across it is then maintained at a specific voltage value. In this way, it can be ensured that the voltage between the source and the drain of the field effect transistor PR1 does not exceed the second voltage threshold, thereby ensuring that the field effect transistor PR1 is not broken down. The number of Schottky diodes can be set to multiple, for example, it can be the diodes N3 and N4 in Figure 4 wherein two diodes are connected in series. Figure 3Only the circuit connection when the second clamping unit 142 includes two Schottky diodes is shown exemplarily. The specific number of Schottky diodes can be determined according to the source-drain voltage of the field effect transistor PR1 expected after breakdown. In addition, the second clamping unit 142 may further include a resistor R4. One end of the resistor R4 is connected to the cathode of the diode N4, and the other end of the resistor R4 is connected to the source of the field effect transistor PR4.

[0089] It can be understood that since the source of the field effect transistor PR1 is commonly connected to the sources of the field effect transistors PR2 and PR3 and the power supply terminal, the first end of the second clamping unit 142 is also connected to the sources of the field effect transistors PR2 and PR3 and the power supply terminal. Similarly, the second end of the second clamping unit 142 is also connected to the gates of the field effect transistors PR1, PR2, and PR3.

[0090] In one embodiment, the high-voltage level conversion circuit may further include a resistor R5 and a resistor R6, as Figure 3 shown, where the resistors R5 and R6 are connected in series between the sources and gates of the field effect transistors PR1, PR2, and PR3, and are used to effectively turn off these three field effect transistors when the second pulse signal is not received. In addition, the high-voltage level conversion circuit may further include a resistor R8, which is used to effectively turn off the field effect transistors NR1 and NR2 when the second pulse signal is not received.

[0091] In one embodiment, as Figure 4 shown, the latch module 120 includes field effect transistors PL4, PR4, NL3, and NR3; the sources of the field effect transistors PL4 and PR4 and the power supply terminal of the floating power supply module 100 are commonly connected; the drains of the field effect transistors PL4, the gates of the field effect transistors PR4, the drains of the field effect transistors NL3, and the gates of the field effect transistors NR3 are commonly connected to serve as the first electrode terminal; the gates of the field effect transistors PL4, the drains of the field effect transistors PR4, the gates of the field effect transistors NL3, and the drains of the field effect transistors NR3 are commonly connected to serve as the second electrode terminal; the sources of the field effect transistors NL3 and NR3 and the ground terminal of the floating power supply module 100 are commonly connected.

[0092] Among them, the field effect transistor PL4 and the field effect transistor PR4 can be P-type field effect transistors, and the field effect transistors NL3 and NR3 can be N-type field effect transistors. On the one hand, when the first electrode terminal receives the first level signal transmitted by the first switching unit 131 and the second electrode terminal receives the second level signal transmitted by the first switching unit 131, the field effect transistor PL4 and the field effect transistor NR3 are turned on. When the field effect transistor PL4 is turned on, the first level signal directly output from the power supply terminal can be continuously transmitted to the first electrode terminal through the field effect transistor PL4. While the first level signal is output outward through the first electrode terminal, the field effect transistor NR3 also remains in the on state under the excitation of the first level signal; when the field effect transistor NR3 is turned on, the second level signal directly output from the ground terminal can be continuously transmitted to the second electrode terminal through the field effect transistor NR3. While the second level signal is output outward through the second electrode terminal, the field effect transistor PL4 also remains in the on state under the excitation of the second level signal; thus, the continuous output of the first level signal and the second level signal is realized.

[0093] On the other hand, when the first electrode terminal receives the second level signal transmitted by the second switching unit 132 and the second electrode terminal receives the first level signal transmitted by the second switching unit 132, the field effect transistor PR4 and the field effect transistor NL3 are turned on. When the field effect transistor PR4 is turned on, the first level signal directly output from the power supply terminal can be continuously transmitted to the second electrode terminal through the field effect transistor PR4. While the first level signal is output outward through the second electrode terminal, the field effect transistor NL3 also remains in the on state under the excitation of the first level signal; when the field effect transistor NL3 is turned on, the second level signal directly output from the ground terminal can be continuously transmitted to the first electrode terminal through the field effect transistor NL3. While the second level signal is output outward through the first electrode terminal, the field effect transistor PR4 also remains in the on state under the excitation of the second level signal; thus, the continuous output of the first level signal and the second level signal is realized.

[0094] In one embodiment, as Figure 5 shown, the high-voltage level conversion circuit further includes a first current biasing module 151. The first current biasing module 151 is respectively connected to the external power supply terminal, the ground terminal of the floating power supply module 100, the source electrode of the field effect transistor NL3, and the source electrode of the field effect transistor NR3, and is used to generate a first bias current according to the external current provided by the external power supply terminal VD and output it to the source electrodes of the field effect transistor NL3 and the field effect transistor NR3; wherein, the current value of the first bias current is less than the current value of the first pulse signal or the current value of the second pulse signal.

[0095] The first current bias module 151 may include a field effect transistor NM1, a field effect transistor NM2, a field effect transistor NM3, and a capacitor C1. Among them, the drain and gate of the field effect transistor NM1, the gate of the field effect transistor NM2, the gate of the field effect transistor NM3, and the first end of the capacitor C1 are commonly connected and connected to the external power supply terminal VD. The source of the field effect transistor NM1, the source of the field effect transistor NM2, the source of the field effect transistor NM3, and the second end of the capacitor C1 are connected to the ground terminal of the floating power supply module 100. The drain of the field effect transistor NM2 is connected to the power supply terminal of the floating power supply module 100. The drain of the field effect transistor NM3 is connected to the source of the field effect transistor NL3 and the source of the field effect transistor NR3. When the drain of the field effect transistor NM1 receives the external current output from the external power supply terminal, the field effect transistor NM1, the field effect transistor NM2, and the field effect transistor NM3 are all turned on, and a bias current is generated and output to the source of the field effect transistor NL3 and the source of the field effect transistor NR3.

[0096] It can be understood that for the case where the low-voltage transmission module 110 outputs the first pulse signal, after receiving the first pulse signal, the field effect transistor PL1 is turned on. Through the field effect transistors NL1 and NL2, the current value of the first pulse signal is copied to the second electrode terminal, that is, copied to the drain of the field effect transistor NR3. According to the above, the bias current flows to the source of the field effect transistor NR3. Since the current value of the first bias current is less than the current value of the first pulse signal, the conduction ability of the field effect transistor NR3 is enhanced, that is, the pulling-down ability of the second electrode terminal of the latch module 120 is enhanced.

[0097] For the case where the low-voltage transmission module 110 outputs the second pulse signal, after receiving the second pulse signal, the field effect transistor PR1 is turned on. Through the field effect transistors NR1 and NR2, the current value of the second pulse signal is copied to the first electrode terminal, that is, copied to the drain of the field effect transistor NL3. According to the above, the bias current flows to the source of the field effect transistor NL3. Since the current value of the first bias current is less than the current value of the second pulse signal, the conduction ability of the field effect transistor NL3 is enhanced, that is, the pulling-down ability of the first electrode terminal of the latch module 120 is enhanced.

[0098] In one embodiment, the high-voltage level conversion circuit further includes a second current bias module 152, as Figure 6As shown, the second current biasing module 152 is respectively connected to the first current biasing module 151, the power supply terminal of the floating power supply module 100, the source electrodes of the field effect transistors PL4 and PR4; the first current biasing module 151 is further configured to conduct the conductive path between the second current biasing module 152 and the ground terminal of the floating power supply module 100 to drive the second current biasing module 152 to generate a second bias current, and the second current biasing module is further configured to output the second bias current to the source electrodes of the field effect transistors PL4 and PR4; wherein, the current value of the second bias current is less than the current value of the first pulse signal or the current value of the second pulse signal.

[0099] Wherein, as Figure 6 shown, the second current biasing module 152 may include a field effect transistor PM1 and a field effect transistor PM2. The drain electrode and the gate electrode of the field effect transistor PM1, and the gate electrode of the field effect transistor PM2 are connected to the drain electrode of the field effect transistor NM2. The source electrode of the field effect transistor PM1 and the source electrode of the field effect transistor PM2 are connected to the power supply terminal of the floating power supply module 100. The drain electrode of the field effect transistor PM2 is connected to the source electrodes of the field effect transistors PL4 and PR4. After the field effect transistor NM2 conducts the conductive path between the field effect transistor PM1 in the second current biasing module 152 and the ground terminal of the floating power supply module 100, a second bias current is generated, and the second current biasing module is further configured to output the second bias current to the source electrodes of the field effect transistors PL4 and PR4.

[0100] It can be understood that for the case where the low-voltage transmission module 110 outputs a first pulse signal, after the field effect transistor PL1 receives the first pulse signal, it conducts. In combination with the field effect transistors PL2 and PL3, the current value of the first pulse signal is copied to the first electrode terminal, that is, it is copied to the drain electrode of the field effect transistor PL4. According to the above, the second bias current flows to the source electrode of the field effect transistor PL4. Since the current value of the second bias current is less than the current value of the first pulse signal, the conduction ability of the field effect transistor PL4 is enhanced, that is, the pull-up ability of the first electrode terminal of the latch module 120 is enhanced.

[0101] For the case where the low-voltage transmission module 110 outputs a second pulse signal, after the field effect transistor PR1 receives the second pulse signal, it conducts. Through the field effect transistors PR2 and PR3, the current value of the second pulse signal is copied to the second electrode terminal, that is, it is copied to the drain electrode of the field effect transistor PR4. According to the above, the second bias current flows to the source electrode of the field effect transistor PR4. Since the current value of the second bias current is less than the current value of the second pulse signal, the conduction ability of the field effect transistor PR4 is enhanced, that is, the pull-up ability of the second electrode terminal of the latch module 120 is enhanced.

[0102] It can be seen that by setting the first current biasing module 151 and the second current biasing module 152, the pull-up ability of the first electrode terminal of the latch module 120 and the pull-down ability of the second electrode terminal can be enhanced simultaneously, or the pull-down ability of the first electrode terminal of the latch module 120 and the pull-up ability of the second electrode terminal can be enhanced simultaneously, thereby enhancing the level conversion ability of the high-voltage level conversion circuit.

[0103] In one embodiment, the high-voltage level conversion circuit further includes a filtering module 160, as Figure 7 shown, the filtering module 160 includes a first input terminal and a second input terminal. The first input terminal is connected to the first electrode terminal, and the second input terminal is connected to the second electrode terminal. The filtering module 160 is configured to maintain the output of the first level signal and the second level signal output by the latch module 120 at the previous output moment if the voltage values of the first level signal and the second level signal output by the latch module 120 are the same.

[0104] Among them, the filtering module 160 may include an inverter 211, an inverter 212, a NAND gate 221, a NAND gate 222, a NAND gate 231, a NAND gate 232, an inverter 241, and an inverter 242. Among them, the input terminal of the inverter 211 and the first input terminal of the NAND gate 221 are connected to the first electrode terminal, and the output terminal of the inverter 211 is connected to the second input terminal of the NAND gate 222; the input terminal of the inverter 212 and the first input terminal of the NAND gate 222 are connected to the second electrode terminal, and the output terminal of the inverter 212 is connected to the second input terminal of the NAND gate 221; the output terminal of the NAND gate 221 is connected to the first input terminal of the NAND gate 231; the output terminal of the NAND gate 222 is connected to the first input terminal of the NAND gate 232; the output terminal of the NAND gate 231 is connected to the second input terminal of the NAND gate 232 and the input terminal of the inverter 241, and the output terminal of the NAND gate 232 is connected to the second input terminal of the NAND gate 231 and the input terminal of the inverter 242.

[0105] It can be understood that due to the rapid rise or fall of the voltage of the floating power supply module 100, false pulses are likely to be generated, making the voltage values of the first level signal and the second level signal output by the latch module 120 the same. Taking the case where the first electrode terminal outputs a low level and the second electrode terminal outputs a high level at the previous output moment as an example, after passing through each logic gate circuit, finally, the inverter 241 outputs a high level and the inverter 242 outputs a low level; taking the case where the voltage value of the first electrode terminal jumps to a high level at the current output moment while the voltage value of the second electrode terminal still remains high as an example, after passing through each logic gate circuit, finally, the inverter 241 outputs a high level and the inverter 242 outputs a low level, which is the same as the output result at the previous output moment. Therefore, by setting the filtering module 160, the "glitches" generated in the output signal due to the rapid change of the voltage of the floating power supply module 100 can be filtered out, thereby ensuring that different level signals are output at the first electrode terminal and the second electrode terminal.

[0106] In addition, the high-voltage level conversion circuit may further be provided with a resistor R21, a resistor R22, a capacitor C21, and a capacitor C22 to filter the outputs of the first electrode terminal and the second electrode terminal. As Figure 8 shown, the first end of the resistor R21 is connected to the first electrode terminal, and the second end of the resistor R21 is respectively connected to the first end of the capacitor C21, the input terminal of the NOT gate 211, and the first input terminal of the NAND gate 221; the first end of the resistor R22 is connected to the second electrode terminal, and the second end of the resistor R22 is respectively connected to the first end of the capacitor C22, the input terminal of the NOT gate 212, and the first input terminal of the NAND gate 222; the second end of the capacitor C21 is connected to the second end of the capacitor C22.

[0107] In one embodiment, as Figure 9As shown, the low-voltage transmission module 110 includes a first NOT gate 311, a second NOT gate 312, a third NOT gate 351, a fourth NOT gate 352, a fifth NOT gate 353, a first delay unit 321, a second delay unit 322, a first NOR gate 331, a second NOR gate 332, a first NAND gate 341, and a second NAND gate 342. The input terminal of the first NOT gate 311 is used to receive an input signal, and the output terminal of the first NOT gate 311 is respectively connected to the input terminal of the second NOT gate 312, the input terminal of the second delay unit 322, and the first terminal of the second NAND gate 342. The output terminal of the second NOT gate 312 is respectively connected to the first terminal of the first NAND gate 341 and the input terminal of the first delay unit 321. The input terminal of the third NOT gate 351 is used to receive a control signal s, and the output terminal of the third NOT gate 351 is respectively connected to the control terminals of the first NOR gate 331 and the second NOR gate 332. The input terminal of the first NOR gate 331 is connected to the output terminal of the first delay unit 321, and the output terminal of the first NOR gate 331 is connected to the second terminal of the first NAND gate 341. The input terminal of the second NOR gate 332 is connected to the output terminal of the second delay unit 322, and the output terminal of the second NOR gate 332 is connected to the second terminal of the second NAND gate 342. The input terminal of the fourth NOT gate 352 is connected to the output terminal of the first NAND gate 341, and the output terminal of the fourth NOT gate 352 is connected to the gate of the field-effect transistor NM4. The input terminal of the fifth NOT gate 353 is connected to the output terminal of the second NAND gate, and the output terminal of the fourth NOT gate 352 is connected to the gate of the field-effect transistor NM5. The drain of the field-effect transistor NM4 is connected to the second terminal of the first switch unit 131, the drain of the field-effect transistor NM5 is connected to the second terminal of the second switch unit 132, and the source of the field-effect transistor NM4 and the source of the field-effect transistor NM5 are connected to the reference ground terminal GND. The control signal s is used to control whether the outputs of the first NOR gate 331 and the second NOR gate 332 are valid. The control signal s can be a high level, which is inverted to a low level by the third NOT gate 351 and then transmitted to the first NOR gate 331 and the second NOR gate 332. At this time, the inputs of the first NOR gate 331 and the second NOR gate 332 determine the outputs, realizing the validity of the outputs of the first NOR gate 331 and the second NOR gate 332.

[0108] Specifically, as Figure 10As shown, assume the input signal is A1. On the one hand, after the input signal A1 passes through the first delay unit 321, signal A2 is obtained. After signal A2 passes through the first NOR gate 331, signal A3 is obtained. After signal A3 passes through the first NAND gate 341 and the fourth NOT gate 352, signal A4 is obtained. Thus, signal A4 drives the field effect transistor NM4 to conduct, making the drain and source of the field effect transistor NM4 conduct, so as to output the electrical signal provided by the reference ground terminal GND, and a first pulse signal is obtained, where the pulse waveform of the first pulse signal is the same as that of signal A4. On the other hand, after the input signal A1 passes through the first NOT gate 311, signal A5 is obtained. After signal A5 passes through the second delay unit 322, signal A6 is obtained. After signal A6 passes through the second NOR gate, signal A7 is obtained. After signal A7 passes through the second NAND gate 342 and the fifth NOT gate 353, signal A8 is obtained. Thus, signal A8 drives the field effect transistor NM5 to conduct, making the drain and source of the field effect transistor NM5 conduct, so as to output the electrical signal provided by the reference ground terminal GND, and a second pulse signal is obtained, where the pulse waveform of the second pulse signal is the same as that of signal A8.

[0109] The embodiment of the present invention also provides a high-voltage level conversion circuit, and its specific structure is as Figure 11 shown. The working principle and beneficial effects of this high-voltage level conversion circuit can refer to the above-mentioned embodiment of the high-voltage level conversion circuit, and will not be elaborated here.

[0110] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A high-voltage level conversion circuit, characterized in that, it is applied to a floating power supply module, and the floating power supply module is used to provide a target signal. The high-voltage level conversion circuit includes: A low-voltage transmission module for outputting a low-voltage pulse signal; A latching module connected to the floating power supply module; A control module connected to the low-voltage transmission module, the latching module, and the floating power supply module respectively. The control module outputs the target signal in response to the low-voltage pulse signal to drive the latching module to continuously output the target signal directly output by the floating power supply module; wherein, the duration of the target signal output by the control module is the same as the pulse duration of the low-voltage pulse signal.

2. The high-voltage level conversion circuit according to claim 1, characterized in that, the low-voltage pulse signal includes a first pulse signal or a second pulse signal; the target signal includes a first level signal and a second level signal; the latching module includes a first electrode terminal and a second electrode terminal; the control module includes: A first switch unit, the first end of the first switch unit is connected to the floating power supply module, the second end of the first switch unit is connected to the low-voltage transmission module, the third end of the first switch unit is connected to the first electrode terminal, the fourth end of the first switch unit is connected to the second electrode terminal. The first switch unit outputs the first level signal to the first electrode terminal in response to the first pulse signal, and outputs the second level signal to the second electrode terminal; the latching module is further configured to continuously output the first level signal through the first electrode terminal, and continuously output the second level signal through the second electrode terminal; A second switch unit, the first end of the second switch unit is connected to the floating power supply module, the second end of the second switch unit is connected to the low-voltage transmission module, the third end of the second switch unit is connected to the second electrode terminal, the fourth end of the second switch unit is connected to the first electrode terminal. The second switch unit outputs the first level signal to the second electrode terminal in response to the second pulse signal, and outputs the second level signal to the first electrode terminal; the latching module is further configured to continuously output the second level signal through the first electrode terminal, and continuously output the first level signal through the second electrode terminal.

3. The high-voltage level conversion circuit according to claim 2, characterized in that, the first switch unit includes a field effect transistor PL1, a field effect transistor PL2, a field effect transistor PL3, a field effect transistor NL1, and a field effect transistor NL2; the drain of the field effect transistor PL1, the gate of the field effect transistor PL1, the gate of the field effect transistor PL2, and the gate of the field effect transistor PL3 are commonly connected and connected to the low-voltage transmission module; the source of the field effect transistor PL1, the source of the field effect transistor PL2, and the source of the field effect transistor PL3 are commonly connected and connected to the power supply terminal of the floating power supply module; The drain of the field effect transistor PL2, the drain of the field effect transistor NL1, the gate of the field effect transistor NL1, and the gate of the field effect transistor NL2 are commonly connected; The source of the field effect transistor NL1 and the source of the field effect transistor NL2 are commonly connected and are connected to the ground terminal of the floating power supply module; The drain of the field effect transistor PL3 is connected to the first electrode terminal; the drain of the field effect transistor NL2 is connected to the second electrode terminal.

4. The high-voltage level conversion circuit according to claim 3, characterized in that the high-voltage level conversion circuit further includes: a first clamping unit, the first end of the first clamping unit is connected to the source of the field effect transistor PL1, the second end of the first clamping unit is connected to the drain of the field effect transistor PL1, and the first clamping unit is used to clamp the voltage between the source and the drain of the field effect transistor PL1 within a first voltage threshold.

5. The high-voltage level conversion circuit according to claim 3, characterized in that the second switching unit includes field effect transistors PR1, PR2, PR3, NR1 and NR2; The drain of the field effect transistor PR1, the gate of the field effect transistor PR1, the gate of the field effect transistor PR2, and the gate of the field effect transistor PR3 are commonly connected and are connected to the low-voltage transmission module; The source of the field effect transistor PR1, the source of the field effect transistor PR2, and the source of the field effect transistor PR3 are commonly connected and are connected to the power supply terminal of the floating power supply module; The drain of the field effect transistor PR2, the drain of the field effect transistor NR1, the gate of the field effect transistor NR1, and the gate of the field effect transistor NR2 are commonly connected; The source of the field effect transistor NR1 and the source of the field effect transistor NR2 are commonly connected and are connected to the ground terminal of the floating power supply module; The drain of the field effect transistor PR3 is connected to the second electrode terminal; the drain of the field effect transistor NR2 is connected to the first electrode terminal.

6. The high-voltage level conversion circuit according to claim 5, characterized in that the high-voltage level conversion circuit further includes: a second clamping unit, the first end of the second clamping unit is connected to the source of the field effect transistor PR1, the second end of the second clamping unit is connected to the drain of the field effect transistor PR1, and the second clamping unit is used to clamp the voltage between the source and the drain of the field effect transistor PR1 within a second voltage threshold.

7. The high-voltage level conversion circuit according to claim 5, characterized in that the latch module includes field effect transistors PL4, PR4, NL3 and NR3; The source of the field effect transistor PL4, the source of the field effect transistor PR4, and the power supply terminal of the floating power supply module are commonly connected; The drain of the field effect transistor PL4, the gate of the field effect transistor PR4, the drain of the field effect transistor NL3, and the gate of the field effect transistor NR3 are commonly connected to serve as the first electrode terminal; The gate of the field effect transistor PL4, the drain of the field effect transistor PR4, the gate of the field effect transistor NL3, and the drain of the field effect transistor NR3 are commonly connected to serve as the second electrode terminal; The source of the field effect transistor NL3, the source of the field effect transistor NR3, and the ground terminal of the floating power supply module are commonly connected.

8. The high-voltage level conversion circuit according to claim 7, characterized in that, The high-voltage level conversion circuit further includes: A first current biasing module, which is respectively connected to an external power supply terminal, the ground terminal of the floating power supply module, the source of the field effect transistor NL3, and the source of the field effect transistor NR3, and is used to generate a first bias current according to the external current provided by the external power supply terminal and output it to the source of the field effect transistor NL3 and the source of the field effect transistor NR3; wherein, the current value of the first bias current is less than the current value of the first pulse signal or the current value of the second pulse signal.

9. The high-voltage level conversion circuit according to claim 8, characterized in that, The high-voltage level conversion circuit further includes: A second current biasing module, which is respectively connected to the first current biasing module, the power supply terminal of the floating power supply module, the source of the field effect transistor PL4, and the source of the field effect transistor PR4; The first current biasing module is further used to conduct the conductive path between the second current biasing module and the ground terminal of the floating power supply module to drive the second current biasing module to generate a second bias current, and the second current biasing module is further used to output the second bias current to the source of the field effect transistor PL4 and the source of the field effect transistor PR4; wherein, the current value of the second bias current is less than the current value of the first pulse signal or the current value of the second pulse signal.

10. The high-voltage level conversion circuit according to claim 2, characterized in that, The high-voltage level conversion circuit further includes: A filtering module, including a first input terminal and a second input terminal, the first input terminal is connected to the first electrode terminal, the second input terminal is connected to the second electrode terminal, and the filtering module is used to maintain the output of the first level signal and the second level signal output by the latching module at the previous output moment if the voltage values of the first level signal and the second level signal output by the latching module are the same.

11. The high-voltage level conversion circuit according to claim 2, characterized in that, The low-voltage transmission module includes a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a first delay unit, a second delay unit, a first NOR gate, a second NOR gate, a first NAND gate, a second NAND gate, a field effect transistor NM4, and a field effect transistor NM5; The input terminal of the first NOT gate is used to receive an input signal, and the output terminal of the first NOT gate is respectively connected to the input terminal of the second NOT gate, the input terminal of the second delay unit, and the first terminal of the second NAND gate; The output terminal of the second NOT gate is respectively connected to the first terminal of the first NAND gate and the input terminal of the first delay unit; The input terminal of the third NOT gate is used to receive a control signal, and the output terminal of the third NOT gate is respectively connected to the control terminal of the first NOR gate and the control terminal of the second NOR gate; The input terminal of the first NOR gate is connected to the output terminal of the first delay unit, and the output terminal of the first NOR gate is connected to the second terminal of the first NAND gate; The input terminal of the second NOR gate is connected to the output terminal of the second delay unit, and the output terminal of the second NOR gate is connected to the second terminal of the second NAND gate; The input terminal of the fourth NOT gate is connected to the output terminal of the first NAND gate, and the output terminal of the fourth NOT gate is connected to the gate of the field effect transistor NM4; The input terminal of the fifth NOT gate is connected to the output terminal of the second NAND gate, and the output terminal of the fourth NOT gate is connected to the gate of the field effect transistor NM5; The drain of the field effect transistor NM4 is connected to the second terminal of the first switch unit, the drain of the field effect transistor NM5 is connected to the second terminal of the second switch unit, and the source of the field effect transistor NM4 and the source of the field effect transistor NM5 are connected to the reference ground terminal.

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