Method and apparatus for encoding a video sequence using a DST-VII transform kernel

Abstract

A method and apparatus for encoding a video sequence using a discrete sine transform (DST) type-VII transform kernel comprises: generating a set of tuples of transform kernel elements associated with an n-point DST-VII transform kernel, the set of tuples comprising a first tuple comprising a plurality of transform kernel elements. A first sum of a first subset of the transform kernel elements of the first tuple is equal to a second sum of a second subset of the remaining transform kernel elements in the first tuple. Based on the generated set of tuples of transform kernel elements, an n-point DST-VII transform kernel is generated, the n-point DST-VII transform kernel comprising at least the transform kernel elements included in the set of tuples. A transform is performed on the video sequence using the n-point DST-VII transform kernel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 62 / 668,065, filed in the U.S. Patent and Trademark Office on May 7, 2018, and U.S. Application No. 16 / 218,076, filed on December 12, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to video coding and decoding technology, and more particularly, to a method and device for encoding a video sequence using a discrete sine transform (DST) type-VII transform kernel, and a computer-readable medium. Background Art

[0004] The Video Coding Experts Group ITU-T VCEG (Q6 / 16) and the Moving Picture Experts Group ISO / IEC MPEG (JTC 1 / SC29 / WG 11) released the H.265 / HEVC (High Efficiency Video Coding) standard in 2013 (version 1), and updated it in 2014 (version 2), 2015 (version 3), and 2016 (version 4). Since then, the ITU has been studying the potential need for standardization of future video coding technologies that will have compression capabilities that significantly exceed the compression capabilities of the HEVC standard (including its extensions).

[0005] In October 2017, the ITU issued a joint call for proposals (CfP) for video compression capabilities beyond HEVC. As of February 15, 2018, 22 CfP responses for Standard Dynamic Range (SDR), 12 CfP responses for High Dynamic Range (HDR), and 12 CfP responses for 360 video categories have been submitted.

[0006] All received CfP replies were evaluated at the 122MPEG / 10th JVET (Joint Video Exploration Team - Joint Video Experts Team) meeting in April 2018. Through careful evaluation, JVET officially launched the standardization of the next generation of video coding beyond HEVC, the so-called Versatile Video Coding (VVC), and its current version is VTM (VVC Test Model), namely VTM 1.

[0007] Compared to DCT-2 (for which fast methods have been extensively studied), implementations of DST-7 are still much less efficient than DCT-2. For example, VTM 1 includes matrix multiplications.

[0008] In JVET-J0066, a method is proposed for estimating different types of DCT and DST in JEM7 by applying an adjustment stage to transforms in the DCT-2 family (which includes DCT-2, DCT-3, DST-2, and DST-3), and the adjustment stage refers to matrix multiplication using sparse matrices, which requires a relatively small number of operations.

[0009] In JVET-J001, a method to implement n-point DST-7 using 2n+1-point discrete Fourier transform (DFT) was proposed.

[0010] Problem to be solved

[0011] The lack of an effective and fast implementation method for DST-7 limits the application of DST-7 in actual video codec implementations.

[0012] For different implementation scenarios, a matrix multiplication based implementation is preferred because it includes more general processing. However, in some cases, a fast method that can significantly reduce the number of operation counts is preferred. Therefore, it is highly desirable to identify a fast method that outputs essentially the same results as a matrix multiplication based implementation, just like the DCT-2 design in HEVC, which supports both matrix multiplication and partial butterfly implementations.

[0013] Existing fast methods for DST-7 (e.g., JVET-J0066 and JVET-J0017) fail to support all desirable features of transform designs in video codecs (including 16-bit intermediate operations, integer operations), and / or fail to provide identical results between fast method implementations and matrix multiplication-based implementations. Summary of the invention

[0014] According to aspects of the present disclosure, a method for encoding a video sequence using a discrete sine transform (DST) type-VII transform kernel includes: generating a set of tuples of transform kernel elements associated with an n-point DST-VII transform kernel, the set of tuples including a first tuple, the first tuple including a plurality of transform kernel elements; wherein a first sum of a first subset of the transform kernel elements of the first tuple is equal to a second sum of a second subset consisting of the remaining transform kernel elements in the first tuple; based on the generated set of tuples of the transform kernel elements, generating the n-point DST-VII transform kernel, the n-point DST-VII transform kernel including at least the transform kernel elements included in the set of tuples; and performing a transform on the video sequence using the n-point DST-VII transform kernel.

[0015] According to aspects of the present disclosure, a device for encoding a video sequence using a discrete sine transform (DST) type-VII transform kernel includes: at least one memory configured to store program code; at least one processor configured to read the program code and operate according to the instructions of the program code, the program code including: generation code configured to cause the at least one processor to generate a set of tuples of transform kernel elements associated with an n-point DST-VII transform kernel, the set of tuples including a first tuple, the first tuple including multiple transform kernel elements; wherein a first sum of a first subset of the transform kernel elements of the first tuple is equal to a second sum of a second subset consisting of the remaining transform kernel elements in the first tuple, and the generation code is further configured to cause the at least one processor to generate the n-point DST-VII transform kernel based on the generated set of tuples of the transform kernel elements, the n-point DST-VII transform kernel including at least the transform kernel elements included in the set of tuples; and execution code configured to cause the at least one processor to perform a transform on the video sequence using the n-point DST-VII transform kernel.

[0016] According to aspects of the present disclosure, a device for encoding a video sequence using a discrete sine transform DST type-VII transform kernel includes: a first generation module, used to generate a set of tuples of transform kernel elements associated with an n-point DST-VII transform kernel, the set of tuples including a first tuple, the first tuple including multiple transform kernel elements; wherein a first sum of a first subset of the transform kernel elements of the first tuple is equal to a second sum of a second subset consisting of the remaining transform kernel elements in the first tuple; a second generation module, used to generate the n-point DST-VII transform kernel based on the generated set of tuples of the transform kernel elements, the n-point DST-VII transform kernel including at least the transform kernel elements included in the set of tuples; and an execution module, used to perform a transform on the video sequence using the n-point DST-VII transform kernel.

[0017] According to aspects of the present disclosure, a non-volatile computer-readable medium is provided for storing instructions, wherein the instructions include one or more instructions, which, when executed by one or more processors of a device, cause the one or more processors to perform the above-mentioned method of encoding a video sequence using a DST-VII transform kernel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other features, properties and various advantages of the disclosed subject matter will become further apparent from the following detailed description and accompanying drawings, in which:

[0019] Figure 1is a flow chart of an example process of a method for decoding a video sequence using a discrete sine transform type DST-VII transform kernel.

[0020] Figure 2 is a simplified block diagram of a communication system according to an embodiment of the present disclosure.

[0021] Figure 3 is a schematic diagram of the placement of video encoders and decoders in a streaming environment.

[0022] Figure 4 is a functional block diagram of a video decoder according to an embodiment of the present disclosure.

[0023] Figure 5 is a functional block diagram of a video encoder according to an embodiment of the present disclosure.

[0024] Figure 6 is a schematic diagram of a computer system according to an embodiment. DETAILED DESCRIPTION

[0025] Based on the utilization of each feature / mode in the transformation basis of DST-7 (i.e., DST-VII), the present disclosure allows substantially similar results compared to the implementation based on matrix multiplication. In this way, some embodiments of this article save the computing resources of the encoder and / or decoder and improve efficiency.

[0026] As shown below, the 16-point DST-7 integer transform kernel used in the forward transform can be expressed as: {a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p}={8,17,25,33,41,48,55,62,67,73,77,81,84,87,88,89}.

[0027] As shown above, the element values ​​of the DST-7 transformation kernel include the following characteristics: a+j=l; b+i=m; c+h=n; d+g=o; and e+f=p.

[0028] According to an embodiment, the input vector for a 16-point transform is x={x0, x1, x2, ..., x15}, and the output transform coefficient vector is y={y0, y1, y2, ..., y15}.

[0029] Based on the above relationship between the transformation kernel elements, instead of implementing a·x0+j·x9+l·x11 (which requires 3 multiplication operations), one embodiment implements: a·(x0+x11)+j·(x9+x11) (which requires 2 multiplication operations).

[0030] In this way, to compute y0, instead of performing the following vector-by-vector multiplication: y0=a·x0+b·x1+c·x2+d·x3+e·x4+f·x5+g·x6+h·x7+i·x8+j·x9+k·x10+l·x11+m·x12+n·x13+o·x14+p·x15 (which requires 16 multiplication operations), one embodiment performs the following operations to obtain The result is basically similar: y0=a·(x0+x11)+b·(x1+x12)+c·(x2+x13)+d·(x3+x14)+e·(x4+x15)+f·(x5+x15)+g·(x6+x14)+h·(x7+x13)+i·(x8+x12)+j·(x9+x11)+k·x10 (which requires 11 multiplication operations).

[0031] In addition, when calculating y2, y3, y6, y8, y9, y11, y12, y14, y15, a similar implementation can be performed and the intermediate results (x0+x11), (x1+x12), (x2+x13), (x3+x14), (x4x15), (x5+x15), (x6+x14), (x7+x13), (x8+x12), (x9+x11), and k·x10 can be reused, respectively.

[0032] According to an embodiment, each third transformation basis vector starting from the second basis vector includes some replication patterns. For example, the second basis vector can be represented as:

[0033]

[0034] Furthermore, the second basis vector may be divided into three segments as shown above (eg, segment 0, segment 1, and segment 2). The three segments are copies of with sign changes, or in other words, "flipped" versions of each other. Thus, when calculating y1, instead of performing the following operation: y1=c·x0+f·x1+i·x2+l·x3+o·x4+o·x5+l·x6+i·x7+f·x8+c·x9-(c·x11+f·x12+i·x13+l·x14+o·x15) (which requires 16 multiplication operations), one embodiment may perform the following operation while obtaining a substantially similar result: y0=c·(x0+x9-x11)+f·(x1+x8-x12)+i·(x2+x7-x13)+l·(x3+x6-x14)+o·(x4+x5-x15) (which requires five multiplication operations).

[0035] In addition, when calculating y1, y4, y7, y10, and y13, the calculations can be performed in a similar manner, and the intermediate results (x0+x9-x11), (x1+x8-x12, (x2+x7-x13), (x3+x6-x14), and (x4+x5-x15) can be reused.

[0036] For the inverse transform, the transform kernel matrix is ​​the transpose of the transform kernel matrix used for the forward transform, and the two features listed above also apply to the inverse transform. In addition, it should be noted that the tenth basis vector is: {k, 0, -k, k, 0, -k, k, 0, -k, k, 0, -k, k, 0, -k, k}, which contains only one unique absolute value (i.e., k). Therefore, instead of using vector-by-vector multiplication to calculate y10: y10 = k·x0-k·x2+k·x3-k·x5+k·x6-k·x8+k·x9-k·x11+k·x12-k·x14+k·x15 (which requires 11 multiplication operations), an embodiment can perform the following operation while obtaining a substantially similar result: y10 = k·(x0-x2+x3-x5+x6-x8+x9-x11+x12-x14+x15) (which requires one multiplication operation).

[0037] For 64-point forward and backward DST-7, the above two features are also available, so similar fast methods discussed above also apply.

[0038] For 32-point forward and backward DST-7, the second feature is available, i.e., there are duplicated or flipped fragments in multiple parts of the basis vectors. Therefore, similar fast methods discussed above based on the second feature are also applicable. The first feature is also available in the 32-point forward and backward DST-7 transform kernels, but with different formulas as described below:

[0039] The elements of a 32-point transform kernel contain 32 different numbers (regardless of sign changes): {a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z,A,B,C,D,E,F}.

[0040] An example of a fixed-point assignment of elements is {a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z,A,B,C,D,E,F} = {4,9,13,17,21,26,30,34,38,42,46,49,53,56,60,63,66,69,71,74,76,78,81,82,84,85,87,88,89,89,90,90}.

[0041] It should be noted that the element values ​​of the 32-point floating-point DST-7 transform kernel have the following characteristics: #0: a+l+A=n+y; #1: b+k+B=o+x; #2: c+j+C=p+w; #3: d+i+D=q+v; #4: e+h+E=r+u; and #5: f+g+F=s+t.

[0042] The elements contained in each of the above 6 equations constitute a quintuple, for example, {a, l, A, n, y} is quintuple #0, and {b, k, B, o, x} is another quintuple #1.

[0043] According to an embodiment, the input vector for a 32-point transform is x={x0, x1, x2, ..., x31}, and the output transform coefficient vector is y={y0, y1, y2, ..., y31}.

[0044] Based on the above relationship between the transformation kernel elements, instead of implementing a·x0+l·x11+n·x13+y·x24+A·x26 (which requires 5 multiplication operations), one embodiment performs the following operations while obtaining substantially similar results: a·x0+l·x11+n·x13+y·x24+(n+yal)·x26, which can also be implemented as a·(x0-x26)+l·(x11-x26)+n·(x13+x26)+y·(x24+x26) (which requires 4 multiplication operations).

[0045] Similarly, the above simplified form of multiplication operation is also applicable to the other 5 quintuples, and the intermediate results, for example, for quintuple #0, (x0-x26), (x11-x26), (x13+x26), (x24+x26) can be pre-calculated and reused to calculate each transform coefficient.

[0046] However, it should be noted that due to rounding errors, the integer value assignment of the elements {a, b, c, ..., F} may not completely follow the above equation. For example, when {a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z, A, B, C, D, E, F} = {4, 9, 13, 17, 21, 26, 30, 34, 38, 42, 46, 49, 53, 56, 60, 63, 66, 69, 71, 74, 76, 78, 81, 82, 84, 85, 87, 88, 89, 89, 90, 90}, it is possible to use The allocation is done by scaling and rounding to the nearest integer.

[0047] For quintuple #1, b+k+B=9+46+88=143, and o+x=60+82=142.

[0048] Therefore, in order to obtain substantially similar results between matrix multiplication and the fast method, the embodiment adjusts the elements of each quintuple so as to perform operations substantially similar to equations defined elsewhere in this document. For example, quintuple #1 is adjusted to {b, k, o, x, B} = {9, 46, 60, 82, 87}. Alternatively, quintuple #1 is adjusted to {b, k, o, x, B} = {9, 46, 60, 83, 88}. Alternatively, quintuple #1 is adjusted to {b, k, o, x, B} = {9, 46, 61, 82, 88}. Alternatively, quintuple #1 is adjusted to {b, k, o, x, B} = {9, 45, 60, 82, 88}. Alternatively, quintuple #1 is adjusted to {b, k, o, x, B} = {8, 46, 60, 82, 88}.

[0049] Compared to matrix multiplication-based implementations (which require 256 multiplication operations and 256 addition / subtraction operations) or JVET-J0066 implementations (which require 152 multiplication operations and 170 addition / subtraction operations), some implementations herein allow 126 multiplication operations and 170 addition / subtraction operations while providing substantially similar results. In this way, some embodiments herein allow for increased efficiency and savings in computational resources for encoders and / or decoders.

[0050] Figure 1 1 is a flow chart of an example process 100 of a method for decoding a video sequence using a discrete sine transform (DST) type-VII transform kernel. In some embodiments, Figure 1 One or more process blocks of may be performed by a decoder. In some embodiments, Figure 1 One or more process blocks of may be performed by another device or a group of devices (eg, an encoder) separate from or including the decoder.

[0051] like Figure 1 As shown, process 100 may include generating a set of tuples of transform kernel elements associated with an n-point DST-VII transform kernel, wherein a first sum of a first subset of the transform kernel elements of the first tuple is equal to a second sum of a second subset of the remaining transform kernel elements of the first tuple (box 110).

[0052] like Figure 1 As further shown in FIG. 1 , process 100 may include generating an n-point DST-VII transform kernel based on the generated set of tuples of transform kernel elements (block 120 ).

[0053] like Figure 1 As further shown in , process 100 may include performing the transform using an n-point DST-VII transform check block.

[0054] According to an embodiment, different absolute element values ​​existing in one transform kernel, together with some predefined constants, may be divided into multiple tuples, and for each tuple, the sum of some absolute element values ​​is the same as the sum of the remaining absolute element values ​​in the same tuple.

[0055] For example, in one embodiment, the tuple is a triplet, which includes 3 elements, and the sum of the absolute values ​​of 2 elements is the same as the absolute value of the remaining 1 element. Alternatively, the tuple is a quadruple, which includes 4 elements, and the sum of the absolute values ​​of 2 elements is the same as the sum of the absolute values ​​of the remaining 2 elements. Alternatively, the tuple is a quadruple, which includes 4 elements, and the sum of the absolute values ​​of 3 elements is the same as the sum of the absolute values ​​of the remaining 1 element. Alternatively, the tuple is a quintuple, which includes 5 elements, and the sum of the absolute values ​​of 3 elements is the same as the sum of the absolute values ​​of the remaining 2 elements.

[0056] According to an embodiment, in addition to the existing different absolute element values ​​present in one transform kernel, predefined constants (which are powers of 2, e.g., 1, 2, 4, 8, 16, 32, 64, etc.) may also be considered as elements in the tuple.

[0057] According to an embodiment, the different absolute element values ​​present in the 16-point and 64-point DST-7 transform kernels are divided into a plurality of triplets, each triplet comprising 3 elements. Additionally or alternatively, the different absolute element values ​​present in the 32-point DST-7 transform kernels are divided into a plurality of quintuples, each quintuple comprising 5 elements.

[0058] According to an embodiment, for an integer transform kernel, the integer elements of the transform kernel can be further adjusted to precisely satisfy the characteristics as described above, i.e., the sum of the absolute values ​​of some elements in a tuple is the same as the sum of the absolute values ​​of the remaining elements in the same tuple, while maintaining good orthogonality of the transform kernel. For example, for a 32-point integer DST-7 kernel, the second tuple {b, k, o, x, B} is adjusted to {9, 46, 60, 82, 87}. Alternatively, for a 32-point integer DST-7 kernel, the second tuple {b, k, o, x, B} is adjusted to {9, 46, 60, 83, 88}. Alternatively, for a 32-point integer DST-7 kernel, the second tuple {b, k, o, x, B} is adjusted to {9, 46, 61, 82, 88}. Alternatively, for a 32-point integer DST-7 core, the second tuple {b, k, o, x, B} is adjusted to {9, 45, 60, 82, 88}. Alternatively, for a 32-point integer DST-7 core, the second tuple {b, k, o, x, B} is adjusted to {8, 46, 60, 82, 88}. Alternatively, for a 32-point integer DST-7 core, the sixth tuple {f, g, s, t, B} is adjusted to {26, 30, 71, 74, 89}. Alternatively, for a 32-point integer DST-7 core, the sixth tuple {b, k, o, x, B} is adjusted to {26, 30, 71, 75, 90}. Alternatively, for a 32-point integer DST-7 core, the sixth tuple {b, k, o, x, B} is adjusted to {26, 30, 72, 74, 90}. Alternatively, for a 32-point integer DST-7 core, the sixth tuple {b, k, o, x, B} is adjusted to {26, 29, 71, 74, 90}. Alternatively, for a 32-point integer DST-7 core, the sixth tuple {b, k, o, x, B} is adjusted to {25, 30, 71, 74, 90}.

[0059] According to an embodiment, the elements of the transform kernel may be further adjusted by simply +1 or -1 on the derived element value derived by scaling with a predefined constant and rounding to the nearest integer.

[0060] According to an embodiment, the elements of the transform kernel may be further adjusted by adding only +1, -1, +2 and -2 to the derived element values ​​derived by scaling with a predefined constant and rounding to the nearest integer.

[0061] According to an embodiment, by the matrix A·A T The orthogonality of the adjusted transform kernel denoted as A is measured by the sum of the absolute values ​​of −s·I, where s is a predefined scaling factor used to derive the integer transform kernel and I is the identity matrix.

[0062] although Figure 1An example block diagram of process 100 is shown, but in some implementations, process 100 may include more Figure 1 More blocks, fewer blocks, different blocks, or differently arranged blocks as depicted in the process 100. Additionally, or alternatively, two or more blocks of process 100 may be executed in parallel.

[0063] Figure 2 A simplified block diagram of a communication system (200) according to an embodiment of the present disclosure is shown. The communication system (200) may include at least two terminals (210-220) interconnected by a network (250). For one-way data transmission, a first terminal (210) may encode video data at a local location for transmission to another terminal (220) via the network (250). The second terminal (220) may receive encoded video data from another terminal from the network (250), decode the encoded video data, and display the recovered video data. One-way data transmission is common in applications such as media services.

[0064] Figure 2 A second pair of terminals (230, 240) is shown, which are provided to support bidirectional transmission of encoded video data, which can occur, for example, during a video conference. For bidirectional data transmission, each terminal (230, 240) can encode the video data collected at a local location for transmission to the other terminal via a network (250). Each terminal (230, 240) can also receive the encoded video data transmitted by the other terminal, and can decode the encoded video data and display the recovered video data on a local display device.

[0065] exist Figure 2 In the embodiment of the present disclosure, the terminals (210-240) may be servers, personal computers, and smart phones, but the principles of the present disclosure are not limited thereto. Embodiments of the present disclosure are applicable to laptop computers, tablet computers, media players, and / or dedicated video conferencing equipment. The network (250) represents any number of networks that transmit encoded video data between the terminals (210-240), including, for example, wired and / or wireless communication networks. The communication network (250) may exchange data in circuit switching and / or packet switching channels. The network may include a telecommunications network, a local area network, a wide area network, and / or the Internet. For the purposes of the present disclosure, unless explained below, the architecture and topology of the network (250) may be irrelevant to the operation of the present disclosure.

[0066] As examples of applications of the disclosed subject matter, Figure 3 The placement of a video encoder and decoder in a streaming environment is shown.The disclosed subject matter is equally applicable to other video-enabled applications including, for example, video conferencing, digital TV, storing compressed video on digital media including CDs, DVDs, memory sticks, etc., and the like.

[0067] The streaming system may include an acquisition subsystem (313), which may include a video source (301) such as a digital camera, which creates, for example, an uncompressed video sample stream (302). The sample stream (302) is depicted as a thick line to emphasize the high amount of data compared to the encoded video stream, which can be processed by an encoder (303) coupled to the camera (301). The encoder (303) may include hardware, software, or a combination of hardware and software to implement or implement various aspects of the disclosed subject matter as described in more detail below. The encoded video stream (304) is depicted as a thin line to emphasize the lower amount of data compared to the sample stream, which can be stored on a streaming server (305) for future use. One or more streaming clients (306, 308) can access the streaming server (305) to retrieve a copy (307, 309) of the encoded video stream (304). The client (306) may include a video decoder (310). The video decoder (310) decodes an incoming copy (307) of the encoded video stream and produces an output video sample stream (311) that can be presented on a display (312) or another presentation device (not depicted). In some streaming systems, the video streams (304, 307, 309) may be encoded according to certain video encoding / compression standards. Examples of such standards include ITU-T H.265. The video coding standard under development is informally referred to as Versatile Video Coding (VVC), and the disclosed subject matter may be used in the context of the VVC standard.

[0068] Figure 4 It may be a functional block diagram of a video decoder (310) according to an embodiment of the present disclosure.

[0069] The receiver (410) may receive one or more encoded video sequences to be decoded by the decoder (310); in the same or another embodiment, one encoded video sequence is received at a time, wherein the decoding of each encoded video sequence is independent of the other encoded video sequences. The encoded video sequence may be received from a channel (412), which may be a hardware / software link to a storage device storing the encoded video data. The receiver (410) may receive the encoded video data as well as other data, such as encoded audio data and / or auxiliary data streams that may be forwarded to their respective consuming entities (not shown). The receiver (410) may separate the encoded video sequence from the other data. To prevent network jitter, a buffer memory (415) may be coupled between the receiver (410) and an entropy decoder / parser (420) (hereinafter referred to as "parser"). When the receiver (410) receives data from a storage / forward device with sufficient bandwidth and controllability or from an isochronous network, it may not be necessary to configure the buffer memory (415), or the buffer memory may be made smaller. Of course, in order to be used on a traffic packet network such as the Internet, a buffer memory (415) may also be required, and the buffer memory may be relatively large and may have an adaptive size.

[0070] The video decoder (310) may include a parser (420) to reconstruct symbols (421) from an entropy coded video sequence. The types of symbols include information used to manage the operation of the video decoder (310) and potentially information used to control a display device such as a display (312) that is not part of the decoder but may be coupled to the decoder, such as Figure 4As shown in . The control information for the display device may be a parameter set fragment (not indicated) of Supplementary Enhancement Information (SEI message) or Video Usability Information (VUI). The parser (420) may parse / entropy decode the received coded video sequence. The coding of the coded video sequence may be performed according to a video coding technique or standard, and may follow principles known to those skilled in the art, including variable length coding, Huffman coding, arithmetic coding with or without context sensitivity, and the like. The parser (420) may extract a subgroup parameter set for at least one subgroup of the subgroups of pixels in the video decoder from the coded video sequence based on at least one parameter corresponding to the group. The subgroup may include a Group of Pictures (GOP), a picture, a tile, a slice, a macroblock, a coding unit (CU), a block, a transform unit (TU), a prediction unit (PU), and the like. The entropy decoder / parser may also extract information such as transform coefficients, quantizer parameter (QP) values, motion vectors, and the like from the coded video sequence.

[0071] The parser (420) may perform entropy decoding / parsing operations on a video sequence received from the buffer memory (415) to create symbols (421). The parser (420) may receive encoded data and selectively decode specific symbols (421). In addition, the parser (420) may determine whether to provide the specific symbol (421) to a motion compensation prediction unit (453), a scaler / inverse transform unit (451), an intra prediction unit (452), or a loop filter unit (456).

[0072] Depending on the type of coded video picture or portion of coded video picture (e.g., inter- and intra-pictures, inter- and intra-blocks) and other factors, the reconstruction of the symbol (421) may involve multiple different units. Which units are involved and how they are involved may be controlled by subgroup control information parsed by the parser (420) from the coded video sequence. For the sake of brevity, such subgroup control information flow between the parser (420) and the multiple units below is not described.

[0073] In addition to the functional blocks already mentioned, the decoder (310) can be conceptually subdivided into several functional units as described below. In a practical embodiment operating under commercial constraints, many of these units interact closely with each other and can be integrated with each other. However, for the purpose of describing the disclosed subject matter, it is appropriate to conceptually subdivide into the functional units below.

[0074] The first unit is a sealer / inverse transform unit (451). The sealer / inverse transform unit (451) receives quantized transform coefficients as symbols (421) from the parser (420) and control information, including which transform method to use, block size, quantization factor, quantization scaling matrix, etc. The sealer / inverse transform unit (451) can output a block including sample values, which can be input into an aggregator (455).

[0075] In some cases, the output samples of the scaler / inverse transform unit (451) may belong to an intra-coded block; that is, a block that does not use predictive information from a previously reconstructed picture, but may use predictive information from a previously reconstructed portion of the current picture. Such predictive information may be provided by an intra-picture prediction unit (452). In some cases, the intra-picture prediction unit (452) generates a block of the same size and shape as the block being reconstructed using surrounding reconstructed information extracted from the current (partially reconstructed) picture (456). In some cases, the aggregator (455) adds the prediction information generated by the intra-prediction unit (452) to the output sample information provided by the scaler / inverse transform unit (451) on a per-sample basis.

[0076] In other cases, the output samples of the scaler / inverse transform unit (451) may belong to an inter-frame coded and potentially motion compensated block. In this case, the motion compensated prediction unit (453) may access the reference picture memory (457) to extract samples for prediction. After the extracted samples are motion compensated according to the symbols (421), these samples may be added to the output of the scaler / inverse transform unit (in this case referred to as residual samples or residual signals) by the aggregator (455) to generate output sample information. The motion compensated prediction unit's retrieval of predicted samples from addresses within the reference picture memory may be controlled by motion vectors, and the motion vectors are provided to the motion compensated prediction unit in the form of the symbols (421), for example, including X, Y and reference picture components. Motion compensation may also include interpolation of sample values ​​extracted from the reference picture memory when using sub-sample accurate motion vectors, motion vector prediction mechanisms, and the like.

[0077] The output samples of the aggregator (455) may be employed by various loop filtering techniques in a loop filter unit (456). The video compression techniques may include in-loop filter techniques controlled by parameters included in the encoded video bitstream and available to the loop filter unit (456) as symbols (421) from the parser (420). However, the video compression techniques may also be responsive to meta-information obtained during decoding of a previous (in decoding order) portion of an encoded picture or encoded video sequence, and to previously reconstructed and loop filtered sample values.

[0078] The output of the loop filter unit (456) may be a sample stream that may be output to a display device (312) and stored in a reference picture memory (457) for subsequent inter-picture prediction.

[0079] Once fully reconstructed, certain coded pictures may be used as reference pictures for future prediction. Once a coded picture is fully reconstructed, and the coded picture is identified as a reference picture (e.g., by the parser (420)), a current reference picture (456) may become part of the reference picture memory (457), and a new current picture memory may be reallocated before starting reconstruction of a subsequent coded picture.

[0080] The video decoder (310) may perform decoding operations according to a predetermined video compression technique as recorded, for example, in the ITU-T H.265 standard. In the sense that the encoded video sequence follows the syntax of the video compression technique or standard, the encoded video sequence may conform to the syntax specified by the video compression technique or standard used, such as the syntax specified in the video compression technique document or standard, particularly in the profiles therein. For compliance, the complexity of the encoded video sequence is also required to be within the range defined by the hierarchy of the video compression technique or standard. In some cases, the hierarchy limits the maximum picture size, the maximum frame rate, the maximum reconstruction sampling rate (measured in, for example, mega samples per second), the maximum reference picture size, etc. In some cases, the limits set by the hierarchy may be further limited by the Hypothetical Reference Decoder (HRD) specification and metadata of the HRD buffer management signaled in the encoded video sequence.

[0081] In an embodiment, the receiver (410) may receive additional (redundant) data along with the encoded video. The additional data may be part of the encoded video sequence. The additional data may be used by the video decoder (310) to properly decode the data and / or more accurately reconstruct the original video data. The additional data may be in the form of, for example, temporal, spatial or signal-to-noise ratio (SNR) enhancement layers, redundant slices, redundant pictures, forward error correction codes, etc.

[0082] Figure 5 It can be a functional block diagram of a video encoder (303) according to an embodiment of the present disclosure.

[0083] The encoder (303) may receive video samples from a video source (301) (not a part of the encoder), which may capture video images to be encoded by the encoder (303).

[0084] The video source (301) may provide a source video sequence in the form of a digital video sample stream to be encoded by the encoder (303), wherein the digital video sample stream may have any suitable bit depth (e.g., 8-bit, 10-bit, 12-bit, ...), any color space (e.g., BT.601 Y CrCB, RGB, ...), and any suitable sampling structure (e.g., Y CrCb 4:2:0, Y CrCb 4:4:4). In a media service system, the video source (301) may be a storage device storing previously prepared videos. In a video conferencing system, the video source (301) may be a camera that captures local image information as a video sequence. The video data may be provided as a plurality of separate pictures that are given motion when viewed sequentially. The pictures themselves may be constructed as a spatial pixel array, wherein each pixel may include one or more samples depending on the sampling structure, color space, etc. used. The relationship between pixels and samples may be easily understood by those skilled in the art. The following description focuses on samples.

[0085] According to an embodiment, the encoder (303) may encode and compress pictures of a source video sequence into an encoded video sequence (543) in real time or under any other time constraints required by the application. Implementing an appropriate encoding speed is a function of a controller (550). The controller controls other functional units as described below and is functionally coupled to these units. For the sake of brevity, couplings are not shown in the figure. Parameters set by the controller may include rate control related parameters (picture skipping, quantizer, lambda value of rate distortion optimization technology, etc.), picture size, picture group (group of pictures, GOP) layout, maximum motion vector search range, etc. Those skilled in the art can easily identify other functions of the controller (550) because these functions may involve a video encoder (303) optimized for a certain system design.

[0086] Some video encoders operate in a manner that is readily understood by those skilled in the art as a "coding loop". As a simple description, the coding loop may consist of an encoding portion of an encoder (530) (hereinafter referred to as the "source encoder", which is responsible for creating symbols based on the input picture to be encoded and the reference picture) and a (local) decoder (533) embedded in the encoder (303). The decoder (533) reconstructs the symbols to create sample data in the same way as the (remote) decoder creates sample data (because in the video compression techniques considered in the disclosed subject matter, any compression between the symbols and the encoded video code stream is lossless). The reconstructed sample stream is input to a reference picture memory (534). Since the decoding of the symbol stream produces bit-accurate results that are independent of the decoder location (local or remote), the contents of the reference picture memory are also bit-accurate between the local encoder and the remote encoder. In other words, the reference picture samples "seen" by the prediction portion of the encoder are exactly the same sample values ​​that the decoder will "see" when using prediction during decoding. This basic principle of reference picture synchronization (and the drift that occurs when synchronization cannot be maintained, for example due to channel errors) is well known to those skilled in the art.

[0087] The operation of the "local" decoder (533) can be combined with the above Figure 4 The "remote" decoder described in detail for the video decoder (310) is identical. However, additional brief reference is made to Figure 5 , when symbols are available and the entropy encoder (545) and the parser (420) are capable of losslessly encoding / decoding the symbols into an encoded video sequence, the entropy decoding portion of the decoder (310) including the channel (412), the receiver (410), the buffer memory (415) and the parser (420) may not be fully implemented in the local decoder (533).

[0088] At this point it can be observed that any decoder techniques other than parsing / entropy decoding present in the decoder must also be present in the corresponding encoder in substantially the same functional form. The description of encoder techniques can be simplified because encoder techniques are reciprocal to the decoder techniques described comprehensively. A more detailed description is only required in certain areas and is provided below.

[0089] As part of the operation, the source encoder (530) may perform motion compensated predictive coding. The motion compensated predictive coding predictively encodes the input frame with reference to one or more previously encoded frames from the video sequence designated as "reference frames". In this manner, the encoding engine (532) encodes the differences between the pixel blocks of the input frame and the pixel blocks of the reference frame, which may be selected as a prediction reference for the input frame.

[0090] The local video decoder (533) may decode the encoded video data that may be designated as a reference frame based on the symbol created by the source encoder (530). The operation of the encoding engine (532) may be a lossy process. When the encoded video data is available at the video decoder ( Figure 5 When the video sequence is decoded at a remote location (not shown), the reconstructed video sequence may typically be a copy of the source video sequence with some errors. The local video decoder (533) replicates the decoding process that may be performed by the video decoder on the reference frame and may cause the reconstructed reference frame to be stored in the reference picture memory (534). In this way, the encoder (303) may store a copy of the reconstructed reference frame locally that has common content (absent transmission errors) with the reconstructed reference frame to be obtained by the remote video decoder.

[0091] The predictor (535) may perform a prediction search for the encoding engine (532). That is, for a new frame to be encoded, the predictor (535) may search the reference picture memory (534) for sample data (as candidate reference pixel blocks) or certain metadata, such as reference picture motion vectors, block shapes, etc., that may serve as appropriate prediction references for the new picture. The predictor (535) may operate pixel-by-pixel based on sample blocks to find a suitable prediction reference. In some cases, based on the search results obtained by the predictor (535), it may be determined that the input picture may have prediction references taken from a plurality of reference pictures stored in the reference picture memory (534).

[0092] The controller (550) may manage encoding operations of the source encoder (530), including, for example, setting parameters and subgroup parameters for encoding video data.

[0093] The outputs of all the above functional units may be entropy encoded in an entropy encoder (545). The entropy encoder performs lossless compression on the symbols generated by the various functional units according to techniques known to those skilled in the art, such as Huffman coding, variable length coding, arithmetic coding, etc., thereby converting the symbols into a coded video sequence.

[0094] The transmitter (540) may buffer the encoded video sequence created by the entropy encoder (545) in preparation for transmission over a communication channel (560), which may be a hardware / software link to a storage device that may store the encoded video data. The transmitter (540) may combine the encoded video data from the video encoder (303) with other data to be transmitted, such as encoded audio data and / or ancillary data streams (source not shown).

[0095] The controller (550) may manage the operation of the encoder (303). During encoding, the controller (550) may assign a certain coded picture type to each coded picture, but this may affect the coding techniques that can be applied to the corresponding picture. For example, a picture may generally be assigned to any of the following frame types:

[0096] An intra picture (I picture) may be a picture that can be encoded and decoded without using any other frame in the sequence as a prediction source. Some video codecs allow different types of intra pictures, including, for example, Independent Decoder Refresh pictures. Those skilled in the art are aware of the variations of I pictures and their corresponding applications and features.

[0097] A predictive picture (P picture) may be a picture that can be encoded and decoded using intra prediction or inter prediction, which uses at most one motion vector and a reference index to predict sample values ​​for each block.

[0098] Bidirectional predictive pictures (B pictures), which can be pictures that can be encoded and decoded using intra prediction or inter prediction, which uses up to two motion vectors and reference indices to predict the sample values ​​of each block. Similarly, multiple predictive pictures can use more than two reference pictures and associated metadata for reconstruction of a single block.

[0099] The source picture may typically be spatially subdivided into blocks of samples (e.g., blocks of 4×4, 8×8, 4×8, or 16×16 samples), and coded block by block. These blocks may be predictively coded with reference to other (already coded) blocks, which are determined according to the coding allocation applied to the block's corresponding picture. For example, blocks of an I picture may be non-predictively coded, or the blocks may be predictively coded (spatial prediction or intra-frame prediction) with reference to already coded blocks of the same picture. Blocks of pixels of a P picture may be non-predictively coded by spatial prediction with reference to one previously coded reference picture or by temporal prediction. Blocks of a B picture may be non-predictively coded by spatial prediction with reference to one or two previously coded reference pictures or by temporal prediction.

[0100] The video encoder (303) may perform encoding operations according to a predetermined video encoding technique or standard, such as ITU-T H.265 Recommendation. In operation, the video encoder (303) may perform various compression operations, including predictive encoding operations that exploit temporal and spatial redundancy in an input video sequence. Thus, the encoded video data may conform to the syntax specified by the video encoding technique or standard used.

[0101] In an embodiment, the transmitter (540) may transmit additional data when transmitting the encoded video. The source encoder (530) may include such data as part of the encoded video sequence. The additional data may include other forms of redundant data such as temporal / spatial / SNR enhancement layers, redundant pictures and slices, supplemental enhancement information (SEI) messages, visual usability information (VUI) parameter set segments, etc.

[0102] In addition, the proposed method can be implemented by a processing circuit (eg, one or more processors or one or more integrated circuits). In one example, one or more processors execute a program stored in a non-transitory computer readable medium to perform one or more proposed methods.

[0103] The above techniques may be implemented as computer software using computer-readable instructions and physically stored in one or more computer-readable media. Figure 6 A computer system 1200 is shown that is suitable for implementing certain embodiments of the disclosed subject matter.

[0104] The computer software may be encoded in any suitable machine code or computer language, and may be assembled, compiled, linked, or the like to create a code comprising instructions, which may be directly executed by one or more computer central processing units (CPUs), graphics processing units (GPUs), etc., or executed by decoding, microcode, or the like.

[0105] The instructions may be executed on various types of computers or components thereof, including, for example, personal computers, tablets, servers, smartphones, gaming devices, IoT devices, etc.

[0106] Figure 6 The components shown for computer system 1200 are exemplary in nature and are not intended to limit the scope of use or functionality of computer software implementing embodiments of the present application. The configuration of the components should not be interpreted as having any dependency or requirement on any component or combination of components shown in the exemplary embodiment of computer system 1200.

[0107] Computer system 1200 may include certain human-computer interface input devices. Such human-computer interface input devices may respond to input from one or more human users through tactile input (e.g., keyboard input, sliding, data glove movement), audio input (e.g., sound, applause), visual input (e.g., gestures), and olfactory input (not shown). The human-computer interface devices may also be used to capture certain media that are not necessarily directly related to conscious human input, such as audio (e.g., speech, music, ambient sound), images (e.g., scanned images, photographic images obtained from a still image camera), and videos (e.g., two-dimensional video, three-dimensional video including stereoscopic video).

[0108] The human-machine interface input device may include one or more of the following (only one of which is depicted): keyboard 601 , mouse 602 , touch pad 603 , touch screen 610 , data gloves, joystick 605 , microphone 606 , scanner 607 , camera 608 .

[0109] The computer system 1200 may also include certain human-computer interface output devices. Such human-computer interface output devices may stimulate the senses of one or more human users through, for example, tactile output, sound, light, and smell / taste. Such human-computer interface output devices may include tactile output devices (e.g., tactile feedback through a touch screen 610, a data glove, or a joystick 605, but there may also be tactile feedback devices that are not used as input devices), audio output devices (e.g., speakers 609, headphones (not shown)), visual output devices (e.g., screens 610 including cathode ray tube (CRT) screens, liquid crystal (LCD) screens, plasma screens, organic light emitting diode (OLED) screens, each of which has or does not have a touch screen input function, each of which has or does not have a tactile feedback function - some of which may output two-dimensional visual outputs or outputs of more than three dimensions by means such as stereoscopic picture output; virtual reality glasses (not shown), holographic displays, and smoke boxes (not shown)) and printers (not shown).

[0110] The computer system (1200) may also include human-accessible storage devices and their associated media, such as optical media including high-density read-only / rewritable optical disks (CD / DVD ROM / RW) 620 or similar media 621 with CD / DVD, a thumb drive 622, a removable hard drive or solid state drive 623, traditional magnetic media such as tapes and floppy disks (not shown), special-purpose ROM / ASIC / PLD-based devices such as security software protectors (not shown), and the like.

[0111] Those skilled in the art should also understand that the term "computer-readable media" used in connection with the disclosed subject matter does not include transmission media, carrier waves, or other transient signals.

[0112] The computer system 1200 may also include an interface to one or more communication networks. For example, the network may be wireless, wired, or optical. The network may also be a local area network, a wide area network, a metropolitan area network, an in-vehicle network, an industrial network, a real-time network, a delay-tolerant network, and the like. The network also includes local area networks such as Ethernet, wireless local area networks, cellular networks, including global systems for mobile communications (GSM), third generation (3G), fourth generation (4G), fifth generation (5G), long term evolution (LTE), etc.), television wired or wireless wide area digital networks (including cable television, satellite television, and terrestrial broadcast television), in-vehicle and industrial networks (including CANBus), and the like. Some networks typically require an external network interface adapter for connecting to some universal data ports or peripheral buses (649) (e.g., a universal serial bus (USB) port of the computer system 1200); other systems are typically integrated into the core of the computer system 1200 by connecting to a system bus as described below (e.g., an Ethernet interface integrated into a PC computer system or a cellular network interface integrated into a smart phone computer system). By using any of these networks, the computer system 1200 can communicate with other entities. The communication can be one-way, for receiving only (e.g., wireless television), one-way for sending only (e.g., CAN bus to certain CAN bus devices), or two-way, such as to other computer systems via a local or wide area digital network. Each of the above networks and network interfaces can use certain protocols and protocol stacks.

[0113] The above-mentioned human-machine interface devices, human-accessible storage devices, and network interfaces can be connected to the core 640 of the computer system 1200.

[0114] The core 640 may include one or more central processing units (CPUs) 641, graphics processing units (GPUs) 642, dedicated programmable processing units in the form of field programmable gate arrays (FPGAs) 643, hardware accelerators for specific tasks 644, and the like. These devices, as well as read-only memory (ROM) 645, random access memory (RAM) 646, internal mass storage (e.g., internal non-user accessible hard disk drives, solid state drives (SSDs), etc.) 647, and the like may be connected via a system bus 648. In some computer systems, the system bus 648 may be accessed in the form of one or more physical plugs so that it may be expanded by additional central processing units, graphics processing units, and the like. Peripheral devices may be attached directly to the core's system bus 648, or connected via a peripheral bus 649. The architecture of the peripheral bus includes a peripheral component interconnect (PCI), a universal serial bus USB, and the like.

[0115] The CPU 641, GPU 642, FPGA 643, and accelerator 644 may execute certain instructions, which in combination may constitute the above-mentioned computer code. The computer code may be stored in ROM 645 or RAM 646. Transient data may also be stored in RAM 646, while permanent data may be stored in, for example, internal mass storage 647. Fast storage and retrieval of any memory device may be achieved by using a cache memory, which may be closely associated with one or more CPUs 641, GPU 642, mass storage 647, ROM 645, RAM 646, etc.

[0116] The computer readable medium may have computer code thereon for performing various computer-implemented operations. The medium and computer code may be specially designed and constructed for the purpose of this application, or may be medium and code well known and available to those skilled in the art of computer software.

[0117] As an example and not a limitation, a computer system having architecture 1200, in particular core 640, can provide the function of executing software contained in one or more tangible computer-readable media as a processor (including CPU, GPU, FPGA, accelerator, etc.). Such computer-readable media can be a medium associated with the above-mentioned user-accessible mass storage, as well as a specific memory of core 640 having non-volatility, such as core internal mass storage 647 or ROM 645. Software implementing various embodiments of the present application can be stored in such a device and executed by core 640. According to specific needs, the computer-readable medium may include one or more storage devices or chips. The software can enable core 640, in particular the processor therein (including CPU, GPU, FPGA, etc.) to perform a specific process or a specific part of a specific process described herein, including defining a data structure stored in RAM 646 and modifying such a data structure according to a software-defined process. In addition or as an alternative, the computer system can provide a function that is logically hardwired or otherwise contained in a circuit (e.g., accelerator 644), which can replace the software or run with the software to perform a specific process or a specific part of a specific process described herein. Where appropriate, references to software may include logic, and vice versa. Where appropriate, references to computer-readable media may include circuits (such as integrated circuits (ICs)) storing the executing software, circuits containing the executing logic, or both. The present application includes any suitable combination of hardware and software.

[0118] Although the present application has described a number of exemplary embodiments, various changes, arrangements and various equivalent substitutions of the embodiments are within the scope of the present application. Therefore, it should be understood that those skilled in the art can design a variety of systems and methods, which, although not explicitly shown or described herein, embody the principles of the present application and are therefore within the spirit and scope of the present application.

Claims

1. A method for encoding a video sequence using a discrete sine transform DST type-VII transform kernel, characterized in that: include: generating a set of tuples of transform kernel elements associated with an n-point DST-VII transform kernel, the set of tuples comprising a first tuple comprising a plurality of transform kernel elements; wherein a first sum of a first subset of transformation core elements of the first tuple is equal to a second sum of a second subset consisting of remaining transformation core elements in the first tuple; Based on the generated set of tuples of the transform core elements, generating the n-point DST-VII transform core, the n-point DST-VII transform core at least including the transform core elements included in the set of tuples; and A transform is performed on the video sequence using the n-point DST-VII transform kernel.

2. The method according to claim 1, characterized in that The set of tuples includes {a,j,l}, {b,i,m}, {c,h,n}, {d,g,o} and {e,f,p}.

3. The method according to claim 2, characterized in that The n-point DST-VII transformation kernel is a 16-point DST-VII transformation kernel, which includes the transformation kernel elements and element k included in the set of tuples, and the 16-point DST-VII transformation kernel is expressed as {a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p}.

4. The method according to claim 2, characterized in that: a+j=l, b+i=m, c+h=n, d+g=o, and e+f=p.

5. The method according to claim 1, characterized in that The set of tuples includes {a,l,A,n,y}, {b,k,B,o,x}, {c,j,C,p,w}, {d,I,D,q,v}, {e,h,E,r,u} and {f,g,F,s,t}.

6. The method according to claim 5, characterized in that The n-point DST-VII transformation kernel is a 32-point DST-VII transformation kernel, which includes the transformation kernel elements included in the set of tuples and element m and element z. The 32-point DST-VII transformation kernel is expressed as {a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z,A,B,C,D,E,F}.

7. The method according to claim 5, characterized in that a+l+A=n+y, b+k+B=o+x, c+j+C=p+w, d+I+D=q+v, e+h+E=r+u, and f+g+F=s+t.

8. The method according to any one of claims 1 to 2, 4 to 5 and 7, characterized in that: n is equal to 16 or 64, wherein each tuple in the set of tuples includes three transform kernel elements.

9. The method according to any one of claims 1 to 2, 4 to 5 and 7, characterized in that: n is equal to 32, wherein each tuple in the set of tuples includes five transform kernel elements.

10. The method according to any one of claims 1 to 7, characterized in that: The tuples in the set of tuples include a first transformation core element, a second transformation core element, a third transformation core element, and a fourth transformation core element, wherein the sum of the absolute values ​​of the first transformation core element and the second transformation core element is equal to the sum of the absolute values ​​of the third transformation core element and the fourth transformation core element.

11. The method according to any one of claims 1 to 7, characterized in that: The tuples in the set of tuples include a first transformation core element, a second transformation core element, a third transformation core element, and a fourth transformation core element, wherein the sum of the absolute values ​​of the first transformation core element, the second transformation core element, and the third transformation core element is equal to the absolute value of the fourth transformation core element.

12. The method according to any one of claims 1 to 7, characterized in that: The tuples in the set of tuples include a first transformation core element, a second transformation core element, a third transformation core element, a fourth transformation core element, and a fifth transformation core element, wherein the sum of the absolute values ​​of the first transformation core element, the second transformation core element, and the third transformation core element is equal to the sum of the absolute values ​​of the fourth transformation core element and the fifth transformation core element.

13. A device for encoding a video sequence using a discrete sine transform DST type-VII transform kernel, characterized in that include: at least one memory configured to store program code; At least one processor is configured to read the program code and operate according to instructions of the program code, wherein the program code includes: generating code configured to cause the at least one processor to generate a set of tuples of transform kernel elements associated with an n-point DST-VII transform kernel, the set of tuples comprising a first tuple, the first tuple comprising a plurality of transform kernel elements; wherein a first sum of a first subset of the transform kernel elements of the first tuple is equal to a second sum of a second subset of the remaining transform kernel elements in the first tuple, and The generation code is further configured to cause the at least one processor to generate the n-point DST-VII transform kernel based on the generated set of tuples of the transform kernel elements, the n-point DST-VII transform kernel including at least the transform kernel elements included in the set of tuples; and The execution code is configured to cause the at least one processor to perform a transform on the video sequence using the n-point DST-VII transform kernel.

14. The device according to claim 13, characterized in that The set of tuples includes {a,j,l}, {b,i,m}, {c,h,n}, {d,g,o} and {e,f,p}.

15. The device according to claim 14, characterized in that The n-point DST-VII transformation kernel is a 16-point DST-VII transformation kernel, which includes the transformation kernel elements and element k included in the set of tuples, and the 16-point DST-VII transformation kernel is expressed as {a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p}.

16. The device according to claim 14, characterized in that a+j=l, b+i=m, c+h=n, d+g=o, and e+f=p.

17. The device according to claim 13, characterized in that The set of tuples includes {a,l,A,n,y}, {b,k,B,o,x}, {c,j,C,p,w}, {d,I,D,q,v}, {e,h,E,r,u} and {f,g,F,s,t}.

18. The device according to claim 17, characterized in that The n-point DST-VII transformation kernel is a 32-point DST-VII transformation kernel, which includes the transformation kernel elements included in the set of tuples and element m and element z. The 32-point DST-VII transformation kernel is expressed as {a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z,A,B,C,D,E,F}.

19. The device according to claim 17, characterized in that a+l+A=n+y, b+k+B=o+x, c+j+C=p+w, d+I+D=q+v, e+h+E=r+u, and f+g+F=s+t.

20. The device according to any one of claims 13 to 14, 16 to 17 and 19, characterized in that n is equal to 16 or 64, wherein each tuple in the set of tuples includes three transform kernel elements.

21. The device according to any one of claims 13 to 14, 16 to 17 and 19, characterized in that n is equal to 16 or 32, wherein each tuple in the set of tuples includes five transform kernel elements.

22. The device according to any one of claims 13 to 19, characterized in that The tuples in the set of tuples include a first transformation core element, a second transformation core element, a third transformation core element, and a fourth transformation core element, wherein the sum of the absolute values ​​of the first transformation core element and the second transformation core element is equal to the sum of the absolute values ​​of the third transformation core element and the fourth transformation core element.

23. The device according to any one of claims 13 to 19, characterized in that The tuples in the set of tuples include a first transformation core element, a second transformation core element, a third transformation core element, and a fourth transformation core element, wherein the sum of the absolute values ​​of the first transformation core element, the second transformation core element, and the third transformation core element is equal to the absolute value of the fourth transformation core element.

24. A device for encoding a video sequence using a discrete sine transform DST type-VII transform kernel, characterized in that include: A first generating module, configured to generate a set of tuples of transform core elements associated with an n-point DST-VII transform core, wherein the set of tuples includes a first tuple, and the first tuple includes a plurality of transform core elements; wherein a first sum of a first subset of transformation core elements of the first tuple is equal to a second sum of a second subset consisting of remaining transformation core elements in the first tuple; A second generating module, configured to generate the n-point DST-VII transform kernel based on the generated set of tuples of the transform kernel elements, wherein the n-point DST-VII transform kernel at least includes the transform kernel elements included in the set of tuples; and An execution module is used to perform transformation on the video sequence using the n-point DST-VII transformation kernel.

25. A non-volatile computer-readable medium, characterized in that: Used to store instructions, the instructions include one or more instructions, when the one or more instructions are executed by one or more processors of the device, the one or more processors are caused to execute the method according to any one of claims 1-12.

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