Data transfer circuit, method and storage device

Abstract

The application relates to a data transmission circuit, a method and a storage device. The data transmission circuit comprises a serial-parallel conversion module, a comparison module, a data conversion module and a write circuit module. The serial-parallel conversion module is used for batch receiving a plurality of external data and outputting initial parallel data according to the external data. The comparison module is used for comparing the received initial parallel data with global data to output a comparison result of whether the number of bits different between the initial parallel data and the global data exceeds a preset threshold. The data conversion module is used for transmitting the initial parallel data to a data bus after inversion in the case that the comparison result exceeds the preset threshold, and transmitting the initial parallel data to the data bus in the case that the comparison result does not exceed the preset threshold. The write circuit module is used for transmitting the data of the data bus to a global data bus. The application reduces the number of data inversion on the data bus and reduces the power consumption in the data transmission process on the data bus.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a data transmission circuit, method and storage device. Background Art

[0002] With the rapid development of semiconductor technology, the density and number of memory cells in the memory cell arrays of semiconductor memory devices are constantly increasing to meet the market demand for the storage capacity of semiconductor memory devices. To improve the speed and efficiency of writing or reading data into or from semiconductor memory devices, data is generally written or read into or from semiconductor memory devices in batches.

[0003] On the one hand, the increase in the density and number of memory cells in the memory cell array leads to an increase in the length of the data transmission path between the data pads and the memory array area. On the other hand, batch writing or reading data requires an increase in the data transmission bandwidth of the data transmission channel between the data pads and the memory array area. This results in a significant increase in the power consumption of the data transmission path between the data pads and the memory array area.

[0004] If the power consumption of the data transmission path between the data pad and the memory array area can be reduced while ensuring that the density and number of memory cells in the memory cell array are not reduced and the efficiency of batch reading or writing data is not reduced, the energy-saving performance of the semiconductor memory device will be effectively improved. Summary of the Invention

[0005] Based on this, it is necessary to provide a data transmission circuit, method and storage device to address the technical problems in the above-mentioned background technology, which can reduce the power consumption of the data transmission path between the data pad and the storage array area while ensuring that the density and number of storage cells in the storage cell array are not reduced and the efficiency of batch reading or writing data is not reduced, thereby effectively improving the energy-saving performance of the semiconductor storage device.

[0006] To achieve the above-mentioned and other purposes, the first aspect of the present application provides a data transmission circuit, including a serial-to-parallel conversion module, a comparison module, a data conversion module and a write circuit module, wherein the serial-to-parallel conversion module is used to receive multiple external data in batches and output initial parallel data according to the external data, wherein the preset bit width of the initial parallel data is the sum of the bit widths of the multiple external data; the comparison module is used to receive global data on a global data line and the initial parallel data, and compare the initial parallel data with the global data to output a comparison result of whether the number of bits that are different between the initial parallel data and the global data exceeds a preset threshold, wherein the initial parallel data is a bit width that is greater than a preset threshold. The row data and the global data have the same preset bit width; the data conversion module is electrically connected to the serial-to-parallel conversion module, the comparison module and the data bus, and is used to invert the initial parallel data and transmit it to the data bus when the comparison result exceeds the preset threshold; and transmit the initial parallel data to the data bus when the comparison result does not exceed the preset threshold; the write circuit module is used to transmit the data of the data bus to the global data bus; wherein, the data transmission path length between the serial-to-parallel conversion module and the data conversion module is less than the data transmission path length between the data conversion module and the write circuit module.

[0007] In the data transmission circuit of the above embodiment, a serial-to-parallel conversion module is provided to receive multiple external data in batches and output initial parallel data based on the received external data, wherein the preset bit width of the initial parallel data is the sum of the bit widths of the multiple external data, so as to realize batch input of data; a comparison module is used to compare the received initial parallel data with global data, and output a comparison result of whether the number of bits that the initial parallel data differs from the global data exceeds a preset threshold, wherein the initial parallel data and the global data have the same preset bit width; then, when the comparison result exceeds the preset threshold, the data conversion module is used to invert the initial parallel data and transmit it to the data bus, and when the comparison result does not exceed the preset threshold, the initial parallel data is transmitted to the data bus; and the write circuit module transmits the data on the data bus to the global data bus. This achieves the goal of reducing the number of flips of the write data during the transmission between the data pad and the storage array area while ensuring the accuracy of batch write data transmission, thereby effectively reducing the power consumption of the data in the transmission path. By setting the data transmission path length between the serial-to-parallel conversion module and the data conversion module to be shorter than the data transmission path length between the data conversion module and the write circuit module, abnormalities in the data bus transmission process of the written data are avoided, and the accuracy of the written data during transmission via the data bus with a longer transmission path is effectively improved. While ensuring that the density and number of storage cells in the storage cell array are not reduced and the efficiency of batch reading or writing data is not reduced, the power consumption of the data transmission path between the data pad and the storage array area is reduced, effectively improving the energy-saving performance of the semiconductor storage device.

[0008] In one embodiment, the data transmission circuit further includes a buffer enable module; the data conversion module is sequentially connected to the write circuit module via at least one of the buffer enable modules, and is used to buffer the data transmitted by the data bus, thereby ensuring the accuracy of the write data during transmission via the data bus with a longer transmission path, while reducing the input current of the data bus, thereby further reducing the power consumption of the data transmission path between the data pad and the storage array area.

[0009] In one embodiment, the global data bus includes a global data line and a complementary global data line, and the global data line and the complementary global data line transmit signals that are inverted from each other;

[0010] The transmitting the data of the data bus to the global data bus comprises:

[0011] transferring the data of the data bus to the global data line; and

[0012] The data of the data bus is inverted and then transmitted to the complementary global data line.

[0013] In the data transmission circuit in the above embodiment, a global data bus is provided to include a global data line and a complementary global data line, wherein the global data line and the complementary global data line transmit signals that are inverted from each other, and a write circuit module is provided to transmit data from the data bus to the global data line, and to invert the data from the data bus and transmit it to the complementary global data line, so that the data transmitted by the complementary global data line and the data transmitted by the global data line can serve as a reference to each other, thereby further improving the accuracy of the write data transmitted to the subsequent data line via the write circuit module.

[0014] In one embodiment, the comparison module includes a comparison unit and a state identification unit, the comparison unit is used to compare the initial parallel data and the global data bit by bit, and output the comparison state data of each bit; the state identification unit is electrically connected to the comparison unit, and is used to perform statistics on the comparison state data of each bit, and output the comparison result based on the statistical result.

[0015] In one embodiment, the data conversion module includes a first transmission unit, a first inverting unit, a second transmission unit and a second inverting unit. The first transmission unit is electrically connected to the serial-to-parallel conversion module and the data bus, and is electrically connected to the output end of the state identification unit through the first inverting unit, and is used to transmit the initial parallel data to the data bus when the comparison result does not exceed the preset threshold, and the preset threshold is half of the preset bit width; the second transmission unit is electrically connected to the data bus and the output end of the state identification unit, and is electrically connected to the serial-to-parallel conversion module through the second inverting unit, and is used to invert the initial parallel data and transmit it to the data bus when the comparison result exceeds the preset threshold.

[0016] In one embodiment, the write circuit module is configured to: receive a comparison result output by the state recognition unit, and generate a data polarity identification signal according to the comparison result.

[0017] In one embodiment, the transmission circuit further includes a read-write conversion circuit, which generates first data based on the data polarity identification signal and the data on the global data bus, and transmits the first data to a local data line or a complementary local data line. The local data line and the complementary local data line transmit signals of opposite phases, thereby accurately transmitting multiple external data input in batches via the serial-to-parallel conversion module to the local data lines. Because the data transmitted via the complementary local data lines can serve as a reference for the data transmitted via the local data lines, the accuracy of data transmission from the global data lines to the local data lines can be improved.

[0018] In one embodiment, the read-write conversion circuit includes a write enable module and a write drive circuit, the write enable module is used to generate a write enable signal and a write enable inverse signal based on the data polarity identification signal and the initial write enable signal; the write drive circuit is used to generate the first data based on the write enable signal, the write enable inverse signal and the data on the global data bus.

[0019] In one embodiment, the write enable module includes a first inverter, a first NOR gate, a second inverter and a second NOR gate, the first inverter is configured as: the input end is electrically connected to the initial write enable signal, and the output end outputs the first write enable inverse signal; the first NOR gate is configured as: the input end is electrically connected to the data polarity identification signal and the output end of the first inverter, and the output end outputs the write enable signal; the second inverter is configured as: the input end is electrically connected to the data polarity identification signal, and the output end outputs the data polarity identification inverse signal; the second NOR gate is configured as: the input end is electrically connected to the output end of the second inverter and the output end of the first inverter, and the output end outputs the write enable inverse signal.

[0020] In one embodiment, the write driver circuit includes a first switch unit, a second switch unit, a third switch unit and a fourth switch unit, the first switch unit is used to electrically connect the local data line and the global data line according to the write enable signal; the second switch unit is used to electrically connect the local data line and the complementary global data line according to the write enable inverse signal; the third switch unit is used to electrically connect the complementary local data line and the global data line according to the write enable inverse signal; and the fourth switch unit is used to electrically connect the complementary local data line and the complementary global data line according to the write enable signal.

[0021] In one embodiment, the read-write conversion circuit also includes a read driver circuit, which includes a fifth switch unit, a sixth switch unit, a seventh switch unit and an eighth switch unit. The control end of the fifth switch unit is electrically connected to the local data line, and is used to electrically connect the complementary global data line and the first node according to the control end signal; the sixth switch unit is used to electrically connect the first node and the ground end according to the read enable signal; the control end of the seventh switch unit is electrically connected to the complementary local data line, and is used to electrically connect the global data line and the second node according to the control end signal; the eighth switch unit is used to electrically connect the second node and the ground end according to the read enable signal.

[0022] In one embodiment, the data conversion module further includes a third transmission unit, a third inverting unit, a fourth transmission unit, and a fourth inverting unit. The third transmission unit is electrically connected to the serial-to-parallel conversion module and the global data line, and is electrically connected to the output end of the comparison module via the third inverting unit. If the comparison result does not exceed the preset threshold, the data on the global data line is transmitted to the serial-to-parallel conversion module. The fourth transmission unit is electrically connected to the global data line and the output end of the comparison module, and is electrically connected to the serial-to-parallel conversion module via the fourth inverting unit. If the comparison result exceeds the preset threshold, the data on the global data line is inverted and then transmitted to the serial-to-parallel conversion module. This reduces the number of flips of the read data during transmission between the storage array area and the data pad while ensuring the accuracy of batch read data transmission, thereby effectively reducing the power consumption of the read data in this transmission path.

[0023] In one embodiment, the data transmission circuit further includes a read circuit module, configured to transmit the data on the global data line to the third transmission unit, or to invert the data on the global data line via the fourth inversion unit and then transmit it to the fourth transmission unit, so that the data read in batches from the storage array area can be accurately read via the serial-to-parallel conversion module.

[0024] A second aspect of the present application provides a storage device comprising the data transmission circuit described in any one of the embodiments of the present application, for storing and transmitting data of a read operation or a write operation.

[0025] A third aspect of the present application provides a data transmission method, including:

[0026] Controlling the serial-to-parallel conversion module to receive multiple external data in batches and output initial parallel data according to the external data, wherein the preset bit width of the initial parallel data is the sum of the bit widths of the multiple external data;

[0027] a control comparison module receiving global data on a global data line and the initial parallel data, and comparing the initial parallel data with the global data to output a comparison result of whether the number of bits that differ between the initial parallel data and the global data exceeds a preset threshold, wherein the initial parallel data and the global data have the same preset bit width;

[0028] The control data conversion module controls the data conversion module to invert the initial parallel data and transmit the inverted data to the data bus if the comparison result exceeds the preset threshold value; and controls the data conversion module to transmit the initial parallel data to the data bus if the comparison result does not exceed the preset threshold value;

[0029] The write circuit module is controlled to transmit the data of the data bus to the global data bus, wherein the data transmission path length between the serial-to-parallel conversion module and the data conversion module is shorter than the data transmission path length between the data conversion module and the write circuit module.

[0030] In the storage device and data transmission method of the above embodiment, a serial-to-parallel conversion module is controlled to receive multiple external data in batches and output initial parallel data based on the received external data, wherein the preset bit width of the initial parallel data is the sum of the bit widths of the multiple external data, thereby realizing batch data input; a comparison module is controlled to compare the received initial parallel data with global data and output a comparison result indicating whether the number of bits that differ between the initial parallel data and the global data exceeds a preset threshold, wherein the initial parallel data and the global data have the same preset bit width; then, the data conversion module is controlled to invert the initial parallel data and transmit it to the data bus if the comparison result exceeds the preset threshold, and to transmit the initial parallel data to the data bus if the comparison result does not exceed the preset threshold; and a write circuit module is controlled to transmit the data on the data bus to the global data bus. Since the transmitted data generally includes a data string consisting of 0s and 1s, by applying a power saving algorithm to the process of batch writing data to the subsequent data line via the data bus, the number of data flips on the data bus is reduced while ensuring data transmission accuracy, thereby effectively reducing power consumption during data bus transmission. The invention reduces the number of times the written data is flipped during transmission between the data pad and the storage array area while ensuring the accuracy of batch write data transmission, thereby effectively reducing the power consumption of the data in the transmission path. By setting the data transmission path length between the serial-to-parallel conversion module and the data conversion module to be shorter than the data transmission path length between the data conversion module and the write circuit module, anomalies in the data bus transmission process of the written data are avoided, effectively improving the accuracy of the written data during transmission via the data bus with a longer transmission path. While ensuring that the density and number of storage cells in the storage cell array are not reduced and the efficiency of batch data reading or writing is not reduced, the power consumption of the data transmission path between the data pad and the storage array area is reduced, effectively improving the energy-saving performance of the semiconductor storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 This is a schematic diagram of the circuit principle of a data transmission circuit provided in the first embodiment of the present application;

[0033] Figure 2 This is a schematic diagram of the circuit principle of a data transmission circuit provided in the second embodiment of the present application;

[0034] Figure 3 This is a schematic diagram of a circuit principle of a data transmission circuit provided in the third embodiment of the present application;

[0035] Figure 4 This is a schematic diagram of the circuit principle of a data transmission circuit provided in the fourth embodiment of the present application;

[0036] Figure 5a This is a schematic diagram of a circuit principle of a data transmission circuit provided in a fifth embodiment of the present application;

[0037] Figure 5b for Figure 5a A schematic diagram of an implementation method;

[0038] Figure 6 This is a schematic diagram of a circuit principle of a data transmission circuit provided in a sixth embodiment of the present application;

[0039] Figure 7 This is a schematic diagram of a circuit principle of a data transmission circuit provided in the seventh embodiment of the present application;

[0040] Figure 8 This is a schematic diagram of a circuit principle of a data transmission circuit provided in an eighth embodiment of the present application;

[0041] Figure 9 This is a circuit diagram of a write enable module in a data transmission circuit provided in one embodiment of the present application;

[0042] Figure 10 This is a circuit diagram of a write driver circuit in a data transmission circuit provided in one embodiment of the present application;

[0043] Figure 11a This is a schematic diagram of a circuit principle of a data transmission circuit provided in a ninth embodiment of the present application;

[0044] Figure 11b for Figure 11a A schematic diagram of an implementation method;

[0045] Figure 12 This is a schematic diagram of a circuit principle of a data transmission circuit provided in the tenth embodiment of the present application;

[0046] Figure 13 A flowchart of a data transmission method provided in one embodiment of the present application is shown.

[0047] Description of reference numerals:

[0048] 100, data transmission circuit; 10, comparison module; 13, serial-to-parallel conversion module; 20, data conversion module; 30, first data line; 40, data bus; 41, write circuit module; 43, buffer enable module; 44, read circuit module; 421, global data line; 422, complementary global data line; 11, comparison unit; 12, state recognition unit; 21, first transmission unit; 22, first inverting unit; 23, second transmission unit; 24, second inverting unit; 25, third transmission unit; 26. Third inverting unit; 27. Fourth transmission unit; 28. Fourth inverting unit; 70. Read-write conversion circuit; 71. Write enable module; 72. Write drive circuit; 721. First switch unit; 722. Second switch unit; 723. Third switch unit; 724. Fourth switch unit; 73. Read drive circuit; 731. Fifth switch unit; 732. Sixth switch unit; 733. Seventh switch unit; 734. Eighth switch unit; 81. Local data line; 82. Complementary local data line. DETAILED DESCRIPTION

[0049] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. In addition, certain terms used throughout the specification and the following claims refer to specific components. It will be understood by those skilled in the art that manufacturers may refer to components by different names. This document does not intend to distinguish between components that have different names but the same function. In the following description and examples, the terms "include" and "comprise" are used in an open manner and should therefore be interpreted as "including, but not limited to..." Similarly, the term "connect" is intended to express an indirect or direct electrical connection. Accordingly, if one device is connected to another device, the connection may be accomplished by a direct electrical connection or by an indirect electrical connection through other devices and connectors.

[0051] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0052] Please refer to Figure 1 In one embodiment of the present application, a data transmission circuit 100 is provided, comprising a serial-to-parallel conversion module 13, a comparison module 10, a data conversion module 20, and a write circuit module 41. The serial-to-parallel conversion module 13 is configured to receive multiple external data in batches and output initial parallel data based on the external data. The preset bit width of the initial parallel data is the sum of the bit widths of the multiple external data. The comparison module 10 is configured to receive global data and initial parallel data on a global data line 421, and compare the initial parallel data with the global data to output a comparison result indicating whether the number of bits that differ between the initial parallel data and the global data exceeds a preset threshold. , the initial parallel data and the global data have the same preset bit width; the data conversion module 20 is electrically connected to the serial-to-parallel conversion module 13, the comparison module 10, and the data bus, and is used to invert the initial parallel data and transmit it to the data bus when the comparison result exceeds the preset threshold; and transmit the initial parallel data to the data bus when the comparison result does not exceed the preset threshold; the write circuit module 41 is used to transmit the data of the data bus to the global data bus; wherein, the data transmission path length between the serial-to-parallel conversion module 13 and the data conversion module 20 is less than the data transmission path length between the data conversion module 20 and the write circuit module 41.

[0053] As an example, please refer to Figure 1, by setting a serial-to-parallel conversion module 13 to receive multiple external data in batches and output initial parallel data based on the received external data, wherein the preset bit width of the initial parallel data is the sum of the bit widths of the multiple external data, so as to realize batch input of data; using a comparison module 10 to compare the received initial parallel data with the global data, and output a comparison result of whether the number of bits that differ between the initial parallel data and the global data exceeds a preset threshold, wherein the initial parallel data and the global data have the same preset bit width; then using a data conversion module 20 to invert the initial parallel data and transmit it to the data bus if the comparison result exceeds the preset threshold, and to transmit the initial parallel data to the data bus if the comparison result does not exceed the preset threshold; so that the write circuit module 41 transmits the data on the data bus to the global data bus. This achieves the goal of reducing the number of flips of the write data during the transmission between the data pad and the storage array area while ensuring the accuracy of batch write data transmission, thereby effectively reducing the power consumption of the data in the transmission path. By setting the data transmission path length between the serial-to-parallel conversion module 13 and the data conversion module 20 to be shorter than the data transmission path length between the data conversion module 20 and the write circuit module 41, abnormalities in the data bus transmission process of the written data can be avoided, and the accuracy of the written data during the data bus transmission process with a longer transmission path can be effectively improved. While ensuring that the density and number of storage cells in the storage cell array are not reduced and the efficiency of batch reading or writing data is not reduced, the power consumption of the data transmission path between the data pad and the storage array area is reduced, thereby effectively improving the energy-saving performance of the semiconductor storage device.

[0054] For further information, please refer to Figure 2 In one embodiment of the present application, the data transmission circuit 100 further includes a buffer enable module 43; the data conversion module 20 is sequentially connected to the write circuit module 41 via at least one of the buffer enable modules 43, for buffering the data transmitted by the data bus, thereby ensuring the accuracy of the write data during transmission via the data bus with a longer transmission path, while reducing the input current of the data bus, thereby further reducing the power consumption of the data transmission path between the data pad and the storage array area.

[0055] For further information, please refer to Figure 3In one embodiment of the present application, the global data bus includes a global data line 421 and a complementary global data line 422. Global data line 421 and complementary global data line 422 transmit signals that are inverted from each other. Transmitting data from the data bus to the global data bus includes: transmitting the data from the data bus to global data line 421; and inverting the data from the data bus and transmitting it to complementary global data line 422. In this embodiment, the data transmitted by complementary global data line 422 and the data transmitted by global data line 421 can serve as a reference for each other, further improving the accuracy of the written data transmitted to the subsequent data line via the write circuit module 41.

[0056] For further information, please refer to Figure 4 In one embodiment of the present application, the comparison module 10 includes a comparison unit 11 and a state identification unit 12. The comparison unit 11 is connected to the serial-to-parallel conversion module 13 via the first data line 30, and is used to compare the initial parallel data and the global data bit by bit, and output comparison state data for each bit. The state identification unit 12 is electrically connected to the comparison unit 11, and is used to collect statistics on the comparison state data of each bit, and output a comparison result based on the statistical result, so that when the comparison result exceeds a preset threshold, such as half of a preset bit width, the data conversion module 20 inverts the initial parallel data provided by the serial-to-parallel conversion module 13 and transmits it to the data bus 40; and when the comparison result does not exceed the preset threshold, the data conversion module 20 transmits the initial parallel data provided by the serial-to-parallel conversion module 13 to the data bus 40, thereby reducing the number of data flips on the data bus while ensuring data transmission accuracy. This achieves the goal of reducing the number of write data flips during transmission between the data pad and the storage array area while ensuring batch write data transmission accuracy, thereby effectively reducing data power consumption in the transmission path.

[0057] For further information, please refer to Figure 5a and Figure 5bIn one embodiment of the present application, the data conversion module 20 includes a first transmission unit 21, a first inverting unit 22, a second transmission unit 23, and a second inverting unit 24. The first transmission unit 21 is electrically connected to the serial-to-parallel conversion module 13 and the data bus 40, and is electrically connected to the output end of the state identification unit 12 through the first inverting unit 22. The first transmission unit 21 is configured to transmit the initial parallel data to the data bus 40 if the comparison result does not exceed a preset threshold, where the preset threshold is half the preset bit width. The second transmission unit 23 is electrically connected to the data bus and the output end of the state identification unit 12, and is electrically connected to the serial-to-parallel conversion module 13 through the second inverting unit 24. The second transmission unit 23 is configured to invert the initial parallel data and transmit it to the data bus 40 if the comparison result exceeds the preset threshold. This embodiment reduces the number of data flips on the data bus 40 while ensuring the accuracy of data transmission on the data bus 40, thereby effectively reducing power consumption during data transmission on the data bus 40.

[0058] For further information, please refer to Figure 6 In one embodiment of the present application, the write circuit module 41 is configured to: receive the comparison result output by the state identification unit 12, and generate a data polarity identification signal pl according to the comparison result, so as to facilitate the subsequent recovery of the flipped data according to the data polarity identification signal pl to ensure the accuracy of data transmission.

[0059] For further information, please refer to Figure 7 In one embodiment of the present application, the data transmission circuit 100 further includes a read-write conversion circuit 70. The read-write conversion circuit 70 generates first data based on the data polarity identification signal and the data on the global data bus. The first data may include the data on the global data line 421 or the inverted data on the global data line 421. The first data is transmitted to the local data line 81 or the complementary local data line 82. The local data line 81 and the complementary local data line 82 transmit signals with opposite phases to accurately transmit the multiple external data input in batches via the serial-to-parallel conversion module 13 to the local data line 81. Because the data transmitted by the complementary local data line 82 can serve as a reference to the data transmitted by the local data line 81, the accuracy of the data transmitted from the global data line 421 to the local data line 81 can be improved.

[0060] For further information, please refer to Figure 8In one embodiment of the present application, the read-write conversion circuit 70 includes a write enable module 71 and a write drive circuit 72. The write enable module 71 is used to generate a write enable signal WrEn and a write enable inverse signal WrEn_ according to the data polarity identification signal pl and the initial write enable signal we; the write drive circuit 72 is used to generate first data according to the write enable signal WrEn, the write enable inverse signal WrEn_ and the data on the global data line 421, and transmit the first data to the local data line 81 or the complementary local data line 82 to ensure the accuracy of data transmission.

[0061] As an example, see Figure 9 In one embodiment of the present application, the write enable module 71 includes a first inverter Inv1, a first NOR gate Nor1, a second inverter Inv2 and a second NOR gate Nor2. The input end of the first inverter Inv1 is electrically connected to the initial write enable signal we, and the output end of the first inverter Inv1 outputs the first write enable inverse signal We1_; the input end of the first NOR gate Nor1 is electrically connected to the data polarity identification signal pl and the output end of the first inverter Inv1, and the output end of the first NOR gate Nor1 outputs the write enable signal WrEn; the input end of the second inverter Inv2 is electrically connected to the data polarity identification signal pl, and the output end of the second inverter Inv2 outputs the data polarity identification inverse signal Pl_; the input end of the second NOR gate Nor2 is electrically connected to the output end of the second inverter Inv2 and the output end of the first inverter Inv1, and the output end of the second NOR gate Nor2 outputs the write enable inverse signal WrEn_. The write driver circuit 72 is controlled according to the write enable signal WrEn and the write enable inverse signal WrEn_ to generate first data according to the data on the global data line, and transmits the first data to the local data line LIO or the complementary local data line LIO_ to ensure the accuracy of data transmission.

[0062] As an example, see Figure 10 In one embodiment of the present application, the write driver circuit 72 includes a first switch unit 721, a second switch unit 722, a third switch unit 723, and a fourth switch unit 724. The first switch unit 721 is configured to electrically connect the local data line LIO and the global data line YIO according to a write enable signal WrEn; the second switch unit 722 is configured to electrically connect the local data line LIO and the complementary global data line YIO_ according to a write enable inverse signal WrEn_; the third switch unit 723 is configured to electrically connect the complementary local data line LIO_ and the global data line YIO according to a write enable inverse signal WrEn_; and the fourth switch unit 724 is configured to electrically connect the complementary local data line LIO_ and the complementary global data line YIO_ according to the write enable inverse signal WrEn_. This allows for recovery of transmitted data and ensures data transmission accuracy.

[0063] As an example, please refer to Figure 10In one embodiment of the present application, the read-write conversion circuit 70 further includes a read driver circuit 73, which includes a fifth switch unit 731, a sixth switch unit 732, a seventh switch unit 733, and an eighth switch unit 734. The control terminal of the fifth switch unit 731 is electrically connected to the local data line LIO and is configured to electrically connect the complementary global data line 422 to the first node a according to a control terminal signal. The sixth switch unit 732 is configured to electrically connect the first node a to the ground terminal according to a read enable signal. The control terminal of the seventh switch unit 733 is electrically connected to the complementary local data line LIO_ and is configured to electrically connect the global data line YIO to the second node b according to a control terminal signal. The eighth switch unit 734 is configured to electrically connect the second node b to the ground terminal according to a read enable signal. This embodiment effectively reduces the number of data flips during the write data transmission process, thereby reducing power consumption during the process of data passing through the serial-to-parallel conversion module 13, the data bus, the global data line YIO or the complementary global data line YIO_, and being written to the local data line LIO or the complementary local data line LIO_.

[0064] As an example, see Figure 11a and Figure 11b In one embodiment of the present application, the data conversion module 20 further includes a third transmission unit 25, a third inverting unit 26, a fourth transmission unit 27, and a fourth inverting unit 28. The third transmission unit is electrically connected to the serial-to-parallel conversion module 13 and the global data line 421, and is also electrically connected to the output end of the comparison module 10 via the third inverting unit. If the comparison result output by the comparison module 10 does not exceed a preset threshold, the data on the global data line 421 is transmitted to the serial-to-parallel conversion module 13. The fourth transmission unit is electrically connected to the global data line 421 and the output end of the comparison module 10, and is also electrically connected to the serial-to-parallel conversion module 13 via the fourth inverting unit. If the comparison result exceeds the preset threshold, the data on the global data line 421 is inverted and then transmitted to the serial-to-parallel conversion module 13. This reduces the number of flips in the transmission of read data between the storage array area and the data pad while ensuring the accuracy of batch read data transmission, thereby effectively reducing the power consumption of the read data in this transmission path.

[0065] For further information, please refer to Figure 12 In one embodiment of the present application, the data transmission circuit 100 further includes a read circuit module 44, which is configured to transmit data on the global data line 421 to the third transmission unit 25, or to invert the data on the global data line 421 via the fourth inversion unit 28 and then transmit the data to the fourth transmission unit 27. This allows the data read out in batches from the memory array area to be accurately read out via the serial-to-parallel conversion module 13.

[0066] Furthermore, in one embodiment of the present application, a storage device is provided, comprising the data transmission circuit described in any one of the embodiments of the present application, for storing and transmitting data of a read operation or a write operation.

[0067] For the specific definition of the storage device in the above embodiment, please refer to the specific definition of the data transmission circuit above, which will not be repeated here.

[0068] For further information, please refer to Figure 13 In one embodiment of the present application, a data transmission method is provided, comprising:

[0069] Step 102: Control the serial-to-parallel conversion module to receive multiple external data in batches and output initial parallel data according to the external data, wherein the preset bit width of the initial parallel data is the sum of the bit widths of the multiple external data;

[0070] Step 104: Controlling a comparison module to receive the global data on the global data line and the initial parallel data, and comparing the initial parallel data with the global data to output a comparison result of whether the number of bits that differ between the initial parallel data and the global data exceeds a preset threshold, wherein the initial parallel data and the global data have the same preset bit width;

[0071] Step 106, controlling the data conversion module to invert the initial parallel data and transmit it to the data bus if the comparison result exceeds the preset threshold; and to transmit the initial parallel data to the data bus if the comparison result does not exceed the preset threshold;

[0072] Step 108: Control the write circuit module to transfer the data of the data bus to the global data bus, wherein the data transmission path length between the serial-to-parallel conversion module and the data conversion module is shorter than the data transmission path length between the data conversion module and the write circuit module.

[0073] For details, please refer to Figure 13The system controls a serial-to-parallel conversion module to receive multiple external data in batches and output initial parallel data based on the received external data, wherein the preset bit width of the initial parallel data is the sum of the bit widths of the multiple external data, thereby realizing batch data input; controls a comparison module to compare the received initial parallel data with global data and outputs a comparison result indicating whether the number of bits that differ between the initial parallel data and the global data exceeds a preset threshold, wherein the initial parallel data and the global data have the same preset bit width; then controls the data conversion module to invert the initial parallel data and transmit it to the data bus if the comparison result exceeds the preset threshold, and to transmit the initial parallel data to the data bus if the comparison result does not exceed the preset threshold; and causes the write circuit module to transmit the data on the data bus to the global data bus. Since the transmitted data generally includes a data string consisting of 0s and 1s, by applying a power-saving algorithm to the process of batch writing data to be transmitted via the data bus to the subsequent data line, the number of data flips on the data bus is reduced while ensuring data transmission accuracy, thereby effectively reducing power consumption during data bus transmission. The invention reduces the number of times the written data is flipped during transmission between the data pad and the storage array area while ensuring the accuracy of batch write data transmission, thereby effectively reducing the power consumption of the data in the transmission path. By setting the data transmission path length between the serial-to-parallel conversion module and the data conversion module to be shorter than the data transmission path length between the data conversion module and the write circuit module, anomalies in the data bus transmission process of the written data are avoided, effectively improving the accuracy of the written data during transmission via the data bus with a longer transmission path. While ensuring that the density and number of storage cells in the storage cell array are not reduced and the efficiency of batch data reading or writing is not reduced, the power consumption of the data transmission path between the data pad and the storage array area is reduced, effectively improving the energy-saving performance of the semiconductor storage device.

[0074] In one embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the transmission method described in any embodiment of the present application is implemented.

[0075] It should be understood that although Figure 13 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 13At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0076] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0077] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present invention.

[0078] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A data transmission circuit, characterized in that: include: a serial-to-parallel conversion module, configured to receive a plurality of external data in batches and output initial parallel data according to the external data, wherein a preset bit width of the initial parallel data is the sum of the bit widths of the plurality of external data; a comparison module, configured to receive global data on a global data line and the initial parallel data, and compare the initial parallel data with the global data to output a comparison result indicating whether a number of bits by which the initial parallel data differs from the global data exceeds a preset threshold, wherein the initial parallel data and the global data have the same preset bit width; a data conversion module, electrically connected to the serial-to-parallel conversion module, the comparison module, and the data bus, configured to invert the initial parallel data and transmit it to the data bus if the comparison result exceeds a preset threshold; and to transmit the initial parallel data to the data bus if the comparison result does not exceed the preset threshold; A write circuit module, used for transmitting the data of the data bus to a global data bus; The length of the data transmission path between the serial-to-parallel conversion module and the data conversion module is shorter than the length of the data transmission path between the data conversion module and the write circuit module.

2. The data transmission circuit according to claim 1, wherein: Also included is a buffer enable module; The data conversion module is connected to the write circuit module in sequence via at least one of the buffer enabling modules, and is used to buffer data transmitted by the data bus.

3. The data transmission circuit according to claim 2, wherein: The global data bus includes a global data line and a complementary global data line, wherein the global data line and the complementary global data line transmit signals that are inverted to each other; The transmitting the data of the data bus to the global data bus comprises: Transmitting the data of the data bus to the global data line; as well as The data of the data bus is inverted and then transmitted to the complementary global data line.

4. The data transmission circuit according to any one of claims 1 to 3, characterized in that: The comparison module includes: a comparing unit, configured to compare the initial parallel data and the global data bit by bit, and output comparison status data for each bit; The state recognition unit is electrically connected to the comparison unit and is used to perform statistics on each bit of the comparison state data and output the comparison result according to the statistical result.

5. The transmission circuit according to claim 4, characterized in that The data conversion module includes: a first transmission unit, electrically connected to the serial-to-parallel conversion module and the data bus, and electrically connected to the output end of the state identification unit through a first inverting unit, and configured to transmit the initial parallel data to the data bus if the comparison result does not exceed the preset threshold, where the preset threshold is half of the preset bit width; A second transmission unit is electrically connected to the data bus and the output end of the state identification unit, and is electrically connected to the serial-to-parallel conversion module through a second inverting unit, and is used for inverting the initial parallel data and transmitting it to the data bus when the comparison result exceeds the preset threshold.

6. The data transmission circuit according to claim 5, characterized in that: The write circuit module is configured as follows: A comparison result output by the state recognition unit is received, and a data polarity identification signal is generated according to the comparison result.

7. The transmission circuit according to claim 6, wherein: It also includes a read-write conversion circuit, which generates first data based on the data polarity identification signal and the data on the global data bus, and transmits the first data to a local data line or a complementary local data line, wherein the local data line and the complementary local data line transmit signals that are inverted to each other.

8. The data transmission circuit according to claim 7, characterized in that: The read-write conversion circuit includes: A write enable module, configured to generate a write enable signal and a write enable inverse signal according to the data polarity identification signal and the initial write enable signal; A write driving circuit is configured to generate the first data according to the write enable signal, the write enable inverse signal and the data on the global data bus.

9. The data transmission circuit according to claim 8, characterized in that: The write enable module includes: The first inverter is configured to: have an input terminal electrically connected to an initial write enable signal, and an output terminal output a first write enable inverse signal; A first NOR gate is configured to: have an input end electrically connected to the data polarity identification signal and an output end of the first inverter, and have an output end outputting a write enable signal; A second inverter is configured to: have an input terminal electrically connected to the data polarity identification signal, and an output terminal output a data polarity identification inverse signal; The second NOR gate is configured such that: an input end is electrically connected to an output end of the second inverter and an output end of the first inverter, and an output end outputs a write enable inverse signal.

10. The transmission circuit according to claim 9, characterized in that The write driver circuit includes: a first switch unit, configured to electrically connect the local data line and the global data line according to the write enable signal; a second switch unit, configured to electrically connect the local data line and the complementary global data line according to the write enable inverse signal; a third switch unit, configured to electrically connect the complementary local data line and the global data line according to the write enable inverse signal; A fourth switch unit is configured to electrically connect the complementary local data line and the complementary global data line according to the write enable signal.

11. The transmission circuit according to claim 10, characterized in that: The read-write conversion circuit further includes a read drive circuit, and the read drive circuit includes: a fifth switch unit, a control end of which is electrically connected to the local data line, and configured to electrically connect the complementary global data line and the first node according to a control end signal; a sixth switch unit, configured to electrically connect the first node and a ground terminal according to a read enable signal; a seventh switch unit, a control terminal of which is electrically connected to the complementary local data line, and configured to electrically connect the global data line and a second node according to a control terminal signal; An eighth switch unit is configured to electrically connect the second node and a ground terminal according to a read enable signal.

12. The transmission circuit according to any one of claims 1 to 3, characterized in that: The data conversion module also includes: a third transmission unit, electrically connected to the serial-to-parallel conversion module and the global data line, and electrically connected to the output end of the comparison module through a third inverting unit, and configured to transmit the data on the global data line to the serial-to-parallel conversion module if the comparison result does not exceed the preset threshold; a fourth transmission unit, electrically connected to the global data line and the output end of the comparison module, and electrically connected to the serial-to-parallel conversion module through a fourth inverting unit, and configured to invert the data on the global data line and transmit the inverted data to the serial-to-parallel conversion module when the comparison result exceeds the preset threshold.

13. The transmission circuit according to claim 12, wherein: Also includes: The read circuit module is used to transmit the data on the global data line to the third transmission unit, or to invert the data on the global data line through the fourth inversion unit and then transmit it to the fourth transmission unit.

14. A storage device, characterized in that: include: The data transmission circuit according to any one of claims 1 to 13, used to store and transmit data of a read operation or a write operation.

15. A data transmission method, characterized in that: include: Controlling the serial-to-parallel conversion module to receive multiple external data in batches and output initial parallel data according to the external data, wherein the preset bit width of the initial parallel data is the sum of the bit widths of the multiple external data; a control comparison module receiving global data on a global data line and the initial parallel data, and comparing the initial parallel data with the global data to output a comparison result of whether the number of bits that differ between the initial parallel data and the global data exceeds a preset threshold, wherein the initial parallel data and the global data have the same preset bit width; The control data conversion module controls the data conversion module to invert the initial parallel data and transmit the inverted data to the data bus if the comparison result exceeds the preset threshold value; and controls the data conversion module to transmit the initial parallel data to the data bus if the comparison result does not exceed the preset threshold value; The control write circuit module transmits the data of the data bus to the global data bus, wherein, The length of the data transmission path between the serial-to-parallel conversion module and the data conversion module is shorter than the length of the data transmission path between the data conversion module and the write circuit module.

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