A memory repair method and apparatus

Abstract

The present application provides a memory repair method and apparatus. The method includes: detecting that the terminal device is powered on, and determining a first physical memory and a second physical memory; determining a target physical memory, where the target physical memory is the memory in the second physical memory that has the same capacity as the first physical memory and has no faults; swapping the physical address of the first physical memory and the physical address of the target physical memory in the address mapping relationship to obtain an updated address mapping relationship; in this way, regardless of whether the first physical memory has faults or not, the terminal device can write the data originally to be written to the first physical memory into the target physical memory, so as to achieve correct storage and retrieval of data, thereby ensuring that the terminal device can operate stably without replacing the faulty memory particles and improving the reliability of the terminal device.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular, to a method and device for memory repair. Background Art

[0002] Currently, mobile terminal devices mainly consist of three core hardware components: a low-power embedded processor, memory, and storage media. Among them, the memory is mainly responsible for supporting the hardware resources for the processor to execute instructions and process data, ensuring the stable operation of the operating system and application programs.

[0003] When physical damage such as early failure occurs in the memory, it will affect the data retention ability of the memory and cause the stored data to flip. For example, when the user stores data 1, it actually becomes data 0 in the memory. The abnormal change of the data temporarily stored in the memory will cause the program to run to an unexpected state, resulting in problems such as the operating system or application program crashing during operation or the device being unable to start, affecting the user experience. However, in the current technical solutions, for the repair method of terminal devices with physical memory failures, it is necessary to disassemble the faulty device and replace the faulty memory particles to achieve the purpose of repairing the device memory. However, such repair methods have the possibility of damaging other hardware and have a high operation risk. Summary of the Invention

[0004] This application provides a method and device for memory repair, which is used to provide a method for repairing the memory of a terminal without the need to replace hardware or use spare memory.

[0005] In a first aspect, an embodiment of this application provides a method for memory repair. This method can be applied to a terminal device or implemented by components of the terminal device, such as components such as a processing device, circuit, chip, etc. in the terminal device. The method includes: detecting that the terminal device is powered on, determining a first physical memory and a second physical memory, where the first physical memory and the second physical memory are used to store different data; determining a target physical memory, where the target physical memory is a memory in the second physical memory with a capacity equal to that of the first physical memory and without faults; swapping the physical addresses of the first physical memory and the target physical memory in the address mapping relationship to obtain an updated address mapping relationship; the address mapping relationship includes the corresponding relationship between different logical addresses and physical addresses.

[0006] Through the above method, through the exchange of hardware storage resources, the terminal device can write the data originally to be written to the first physical memory into the target physical memory, thereby realizing the correct storage and retrieval of data. Thus, without replacing the faulty memory particles, it can ensure the stable operation of the terminal device, avoid the first physical memory being damaged and unable to start up, and improve the reliability of the terminal device.

[0007] In a possible implementation method, before swapping the physical address of the first physical memory and the physical address of the target physical memory in the address mapping relationship, the data stored on the first physical memory is written into the target physical memory.

[0008] Through the above method, data loss or omission can be avoided, ensuring the normal operation of the terminal device.

[0009] In a possible implementation method, after updating the address mapping relationship, it is detected whether the first physical memory has a fault; if it is determined that there is a fault in the first physical memory, the updated address mapping relationship is maintained; if it is determined that there is no fault in the first physical memory, the physical address of the first physical memory and the physical address of the target physical memory are swapped back in the updated address mapping relationship.

[0010] In a possible implementation method, after it is determined that there is a fault in the first physical memory, fault information of the first physical memory is generated. The fault information is used to indicate that there is a fault in the first physical memory, and the fault information includes the physical address of the first physical memory, and / or, the logical address corresponding to the physical address of the first physical memory in the updated address mapping relationship.

[0011] In a possible implementation method, according to the fault identifier, the corresponding relationship of the first physical memory is deleted in the updated address mapping relationship.

[0012] Through the above method, the faulty memory can be avoided from being called, enabling the terminal device to operate normally without replacing the memory hardware.

[0013] In a second aspect, an embodiment of the present application provides a terminal device, including a processor and a memory. Among them, the memory is used to store one or more computer programs; when the one or more computer programs stored in the memory are executed by the processor, the terminal device can implement the method of any possible design in any of the above aspects.

[0014] In a third aspect, a terminal device is further provided, including: modules / units for executing the method of the first aspect or any possible design of the first aspect; these modules / units can be implemented by hardware or by hardware executing corresponding software.

[0015] In a fourth aspect, a chip is further provided. The chip is coupled to the memory in the terminal device described in the first aspect above, so that when the chip runs, it calls the program instructions stored in the memory to implement the method provided in the first aspect above.

[0016] In a fifth aspect, there is also provided a computer-readable storage medium, which includes a computer program. When the computer program runs on a terminal device, the terminal device is caused to execute the method provided in the first aspect as described above.

[0017] In a sixth aspect, there is also provided a computer program product, including instructions. When the instructions run on a computer, the computer is caused to execute the method provided in the first aspect as described above.

[0018] For the beneficial effects of the second to sixth aspects above, please refer to the beneficial effects of the technical solutions proposed in the first aspect, and they will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A It is a schematic structural diagram of a terminal device provided by an embodiment of the present application;

[0020] Figure 1B It is a schematic structural diagram of another terminal device provided by an embodiment of the present application;

[0021] Figure 2 It is a schematic flowchart of a memory repair method provided by an embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of an application scenario of a memory;

[0023] Figure 4 (a) is a schematic diagram of an address mapping relationship of a memory;

[0024] Figure 4 (b) is a schematic diagram of an address mapping relationship of a memory after hardware exchange provided by an embodiment of the present application;

[0025] Figure 5 (a) is a schematic diagram of an address mapping register provided by an embodiment of the present application;

[0026] Figure 5 (b) is a schematic diagram of a scenario of hardware storage resource exchange provided by an embodiment of the present application

[0027] Figure 5 (c) is a schematic diagram of an address mapping register after hardware exchange provided by an embodiment of the present application;

[0028] Figure 6 It is a schematic structural diagram of another terminal device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] Figure 1AA schematic structural diagram of a terminal device provided by an embodiment of the present application. The terminal device may include a processor 110, an internal memory 121, and an external memory 122.

[0030] 1) The processor 110 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured thereto. In one embodiment, a memory controller 1101 and a storage controller 1102 may also be provided within the processor 110. Among them, the memory controller 1101 is used to manage the memory and communicate with the processor 110. In the terminal device, data exchange between the processor 110 and the memory is carried out through the memory controller 1101. Similarly, the storage controller 1102 is used to manage the storage and communicate with the processor 110. In the terminal device, data exchange between the processor 110 and the storage is carried out through the storage controller 1101. The memory controller 1101 and the storage controller 1102 will be specifically introduced below and will not be repeated here.

[0031] 2) The internal memory 121, which can be simply referred to as memory, can be used to temporarily store computer-executable program codes and data. Exemplarily, the executable program codes include: operating systems (such as Android, IOS, etc.), application programs (such as camera applications, WeChat applications, etc.), computer programs required for at least one function (such as sound playback function, microphone function), etc. The data includes: data created during the use of the terminal device 100 (such as images, videos, etc. collected by the camera application), etc.

[0032] The memory has the characteristics of being able to read and write data at any time and having a very fast speed. It can directly exchange data with the processor 110 and can be used as a temporary data storage space for running applications. The memory includes various types of memories, such as dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR), etc.

[0033] 3) The external memory 122 can be a hard disk, which is a non-volatile memory and is usually used to persistently store computer-executable program codes and data. Different from the memory, the speed of reading and writing data on the hard disk is slower than that of the memory. Generally, when the operating system or an application is running, the program codes and / or data stored on the hard disk need to be first read into the memory, and then the processor 110 obtains the program codes and / or data from the memory. Correspondingly, the processor 110 executes various applications and data processing of the terminal device by running the codes stored in the memory.

[0034] All in all, the memory is a key hardware resource to ensure the stable operation of the operating system and applications. Currently, when the memory is damaged, the program instructions or data of the operating system cannot be correctly stored, which will affect the normal use of the terminal device. In this case, only by disassembling the terminal device and replacing the faulty memory particles therein can the memory of the device be repaired. However, this method may damage other hardware in the terminal device, and the operation risk is relatively high.

[0035] In view of this, the technical solutions of the embodiments of the present application are provided. In the embodiments of the present application, when it is detected that the terminal device is powered on, the first physical memory and the second physical memory are determined. A target physical memory that has the same size as the first physical memory and is determined to have no faulty memory particles is determined in the second physical memory. The hardware exchange between the target physical memory and the first physical memory is achieved by software means. In this way, regardless of whether the first physical memory has faults or not, the terminal device can write the data originally to be written into the first physical memory into the target physical memory, thereby realizing the correct storage and retrieval of memory data, and thus ensuring the stable operation of the terminal device without replacing the faulty memory particles, and improving the reliability of the terminal device.

[0036] In some embodiments of the present application, Figure 1A The illustrated terminal device 100 can be a user equipment (UE), including a handheld device, a vehicle-mounted device, a wearable device or a computing device. Such as a mobile phone, a tablet computer, a wearable device with wireless communication function (such as a smart watch), etc. Exemplary embodiments of portable electronic devices include, but are not limited to, those equipped with or other operating systems of portable electronic devices. The terminal device 100 can be a personal computer. Additionally, Figure 1A The illustrated structure does not constitute a specific limitation on the terminal device. In other embodiments of the present application, the terminal device may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or have different component arrangements. These components can be implemented in hardware, software, or a combination of software and hardware.

[0037] Exemplarily, taking the terminal device as a mobile phone as an example,Figure 1B The structural schematic diagram of the mobile phone 100 is shown.

[0038] The mobile phone 100 may include a processor 110, an external memory interface 120, an internal memory 121, a USB interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone interface 170D, a sensor module 180, a key 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a SIM card interface 195, etc.

[0039] It can be understood that the structure schematically shown in the embodiments of the present invention does not constitute a specific limitation on the mobile phone 100. In other embodiments of the present application, the mobile phone 100 may include more or fewer components than those shown in the figure, or combine certain components, or split certain components, or have different component arrangements. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0040] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors. Among them, the controller may be the nerve center and command center of the mobile phone 100. The controller may generate operation control signals according to the instruction operation code and timing signal to complete the control of fetching instructions and executing instructions.

[0041] A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory may save the instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use this instruction or data again, it can be directly called from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0042] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Miniled, a MicroLed, a Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the mobile phone 100 may include one or N display screens 194, where N is a positive integer greater than 1.

[0043] In the embodiments of the present application, the display screen 194 receives a touch operation of the user, and the processor 110 adds a unique tracking identifier corresponding to the service to the service startup entry in response to the touch operation.

[0044] The camera 193 (front camera or rear camera, or a camera can be used as both a front camera and a rear camera) is used to capture still images or videos. Generally, the camera 193 may include a photosensitive element such as a lens group and an image sensor. Among them, the lens group includes a plurality of lenses (convex lenses or concave lenses) for collecting the optical signals reflected by the object to be photographed and transmitting the collected optical signals to the image sensor. The image sensor generates an original image of the object to be photographed according to the optical signals.

[0045] Among them, the sensor module 180 may include a gyroscope sensor, an acceleration sensor, a proximity light sensor, a fingerprint sensor, a touch sensor, a rotation axis sensor, etc. Of course, the mobile phone 100 may also include other sensors, such as a temperature sensor, a pressure sensor, a distance sensor, a magnetic sensor, an ambient light sensor, a barometric pressure sensor, a bone conduction sensor, etc. (not shown in the figure).

[0046] Exemplarily, the display screen 194 of the mobile phone 100 displays the main interface, and the main interface includes icons of multiple applications (such as a camera application, a WeChat application, etc.). The user clicks the icon of the camera application in the main interface through the touch sensor 180K, triggering the processor 110 to start the camera application and turn on the camera 193. The display screen 194 displays the interface of the camera application, such as a viewfinder interface.

[0047] The wireless communication function of the mobile phone 100 can be implemented by the antenna 1, antenna 2, mobile communication module 151, wireless communication module 152, modulation and demodulation processor, baseband processor, etc.

[0048] The antenna 1 and the antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in the terminal device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization rate of the antennas. For example, the antenna 1 can be multiplexed as the diversity antenna of the wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0049] The mobile communication module 151 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc. applied to the terminal device 100. The mobile communication module 151 can include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 151 can receive electromagnetic waves by the antenna 1, filter, amplify, etc. the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor and convert it into electromagnetic waves through the antenna 1 for radiation. In some embodiments, at least some functional modules of the mobile communication module 151 can be arranged in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 151 and at least some modules of the processor 110 can be arranged in the same device.

[0050] The modulation and demodulation processor can include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. Subsequently, the demodulator transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, receiver 170B, etc.), or displays an image or video through the display screen 194. In some embodiments, the modulation and demodulation processor can be an independent device. In some other embodiments, the modulation and demodulation processor can be independent of the processor 110 and arranged in the same device as the mobile communication module 150 or other functional modules.

[0051] The wireless communication module 152 may provide solutions for wireless communications applied to the terminal device 100, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite systems (GNSSs), frequency modulation (FM), near field communication (NFC), infrared technology (IR), etc. The wireless communication module 152 may be one or more devices integrating at least one communication processing module. The wireless communication module 152 receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering processing on the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 152 may also receive the signals to be sent from the processor 110, perform frequency modulation and amplification on them, and convert them into electromagnetic waves through the antenna 2 for radiation.

[0052] In addition, the mobile phone 100 may implement audio functions through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor, etc. For example, music playing, recording, etc. The mobile phone 100 may receive inputs from the keys 190 and generate key signal inputs related to the user settings and function controls of the mobile phone 100. The mobile phone 100 may use the motor 191 to generate vibration prompts (such as incoming call vibration prompts). The indicator 192 in the mobile phone 100 may be an indicator light, which can be used to indicate the charging status, power change, and can also be used to indicate messages, missed calls, notifications, etc. The SIM card interface 195 in the mobile phone 100 is used to connect the SIM card. The SIM card can be in contact with and separated from the mobile phone 100 by being inserted into or removed from the SIM card interface 195.

[0053] It should be understood that in practical applications, the mobile phone 100 may include more or fewer components than Figure 1B shown, and the embodiments of the present application do not make limitations.

[0054] Some noun concepts related to the embodiments of the present application are introduced above. Next, the technical features involved in the embodiments of the present application are introduced.

[0055] 1) Address mapping relationship

[0056] There is a logical (virtual) address system inside the operating system, which corresponds to all physical addresses on the terminal device (including the addresses of the memory and the hard disk). Taking the address mapping relationship of the memory as an example, the address mapping relationship of the memory includes the correspondence between the logical (virtual) address and the physical address of the memory. Among them, the logical address refers to the address of the memory unit seen from the perspective of the operating system and application programs in the computer architecture. The physical address means that information is stored in the memory in bytes, and each byte unit is given a unique memory address, that is, the physical address, also called the actual address or absolute address. The physical address is unique, and the logical address and the physical address are relative.

[0057] Exemplarily, the terminal device uniformly addresses all storage spaces of the memory. After the unified addressing, each segment of the memory space has a unique logical address. This logical address is globally unique, which means that the space it indicates is unique on the terminal device. After allocating a physical space to a segment of the memory space, the logical address of this space has its corresponding physical address, and the physical address indicates which memory on the terminal device the space represented by the logical address actually locates in, and the offset in this memory, that is, the position of the physical space. Each segment of space here can have a preset size, which is not limited in the embodiments of the present application.

[0058] 2) Static memory allocation and dynamic memory allocation

[0059] In one implementation, the memory in the embodiments of the present application can be divided into statically allocated memory and dynamically allocated memory. The statically allocated memory and the dynamically allocated memory are pre-configured to store different data. For example, the statically allocated memory is used to store program instructions and data used by the operating system of the terminal device, hardware chips (such as sensors, cameras, etc.). The dynamically allocated memory is used to store program instructions and / or data used during the operation of the application program.

[0060] Exemplarily, the composition unit of the memory can be a memory block. Among them, the memory block can be a physical memory unit or a segment of logical memory space. In the memory, the statically allocated memory and the dynamically allocated memory can be divided by the memory block granularity, that is, the statically allocated memory and the dynamically allocated memory include one or more memory blocks. In practical applications, the data of the operating system and hardware chips is less than that of the application program. Therefore, the number of memory blocks of the statically allocated memory is generally less than that of the dynamically allocated memory.

[0061] Such as Figure 2As shown in the figure, the size of one memory block is 1GB, and the maximum logical address of statically allocated memory is 1023MB. Take the maximum logical address of statically allocated memory as its upper limit and align it upward with the size of the memory block. Then, the physical memory corresponding to the statically allocated memory can be the first 1GB of memory, and the remaining memory is for dynamically allocated memory. That is, the statically allocated memory can be located before the dynamically allocated memory and can include N memory blocks.

[0062] Among them, the performance of the memories corresponding to the statically allocated memory and the dynamically allocated memory can be the same or different, and the embodiments of the present application do not limit this. Generally, the performance of the memories corresponding to the two is the same. Hereinafter, an example in which the performance of the memories corresponding to the two is the same will be described.

[0063] For the convenience of understanding the technical solution of the present application, in the embodiments to be introduced later in the present application, the "first physical memory" is taken as the physical memory corresponding to the original "statically allocated memory" in the terminal device, and the "second physical memory" is taken as the physical memory corresponding to the original "dynamically allocated memory" in the terminal device as an example for introduction.

[0064] Next, the memory repair method provided by the present application will be introduced in conjunction with specific drawings. Please refer to Figure 3 which is the flowchart of this method. This method can be applied to Figure 1A or Figure 1B the terminal device shown in the figure. As shown in Figure 3 the figure, this method may include the following steps:

[0065] Step 301: The processor detects a trigger condition and determines the first physical memory and the second physical memory.

[0066] In the embodiments of the present application, the method process may be triggered when the processor detects that the trigger condition is met. Exemplarily, the trigger condition may be that the processor detects the startup of the terminal device. In practical applications, when an abnormal event occurs in the terminal device, such as a memory failure, it may cause the terminal device to restart. Therefore, when detecting the startup of the terminal device, triggering the process provided by the embodiments of the present application can quickly locate the fault problem. Specifically, the startup process includes but is not limited to the Bootrom stage, the Xloader stage, the Fastboot stage, the Kernel stage, and the Android stage. The timing of executing step 301 can be any stage of the startup, such as the Xloader stage. It should be understood that the earlier this process is executed, the more beneficial it is to reduce the impact of the faulty memory on the terminal device.

[0067] In one embodiment, the distribution information of the statically allocated memory is recorded in the device tree of the terminal device. The distribution information includes, but is not limited to, the maximum logical address of the statically allocated memory. Specifically, when performing step 301, the processor can obtain the distribution information of the statically allocated memory and determine the physical memory corresponding to the statically allocated memory according to the distribution information of the statically allocated memory. Here, the physical memory corresponding to the currently determined statically allocated memory is denoted as the first physical memory, and the remaining physical memory other than the first physical memory is denoted as the second physical memory, that is, the physical memory corresponding to the dynamically allocated memory.

[0068] Step 302: The processor detects the second physical memory and determines the target physical memory.

[0069] In an implementable manner, the processor can perform a patrol inspection on the second physical memory to detect whether there are faulty memory particles in the second physical memory. Its patrol inspection algorithm can be a lightweight algorithm, such as a read-write verification algorithm, or a general memtester algorithm, etc., or other custom patrol inspection algorithms. The embodiments of the present application do not limit this, and any algorithm capable of detecting whether there are faults in the memory is applicable to the embodiments of the present application. The specific implementation manners of different patrol inspection algorithms can follow the existing implementation mechanisms and will not be introduced in detail here. The following takes the read-write verification algorithm as an example to introduce the patrol inspection process.

[0070] Exemplarily, the patrol inspection method can detect in units of memory blocks, and subsequently, hardware storage resources can also be exchanged in units of memory blocks. Specifically, taking the detection of a memory block (assumed to be 1GB) as an example, the implementation process of its read-write verification algorithm can include:

[0071] Binary data "1" is written to each storage unit in the memory block respectively. Here, each storage unit refers to a storage unit that can store 1 bit of data. After a preset time, the data stored in each storage unit in the memory block is read. If the data read in a storage unit is still 1, it is determined that the storage unit has no fault. If it is 0, it is determined that the storage unit has a fault. The above method is only an example, and binary data "0" can also be written to each storage unit. After a preset time, it is verified whether the data read from each storage unit is consistent with the written data to determine whether it is damaged. In the embodiments of the present application, if one or more storage units in the memory block have faults, it is determined that the memory block has a fault.

[0072] Exemplarily, in the above inspection method, serial inspection can be performed during detection. For example, each memory block is detected one by one. Then, when dynamically allocated memory contains multiple memory blocks, these multiple memory blocks need to be detected sequentially and alternately. Additionally, by way of example, the inspection method can also be parallel inspection. For example, multiple memory blocks of multiple second physical memories are synchronously detected at the same time. In an actual product, the terminal device can include a multi-core processor, and this multi-core processor can perform parallel synchronous detection of multiple memory blocks. That is, at the same time, each core can detect a corresponding memory block, so as to achieve the purpose of quickly detecting whether multiple memory blocks have failures.

[0073] The above method can determine which memory blocks in the dynamically allocated memory have failures and which do not. In one possible case, the dynamically allocated memory includes multiple memory blocks without failures. Subsequently, based on these multiple memory blocks without failures, a target physical memory with the same size as the statically allocated memory can be determined.

[0074] Specifically, in the first implementation manner, according to the first quantity of the memory blocks included in the statically allocated memory, a continuous first quantity of memory blocks are selected from the multiple memory blocks without failures in the dynamically allocated memory. For example, if the statically allocated memory includes 1 memory block, then one memory block without failure can be selected in the dynamically allocated memory as the target physical memory. Another example is that if the statically allocated memory includes 2 memory blocks, then 2 consecutive memory blocks without failures can be selected in the dynamically allocated memory as the target physical memory.

[0075] In another embodiment, the memory blocks selected in the first embodiment can be further detected for the second time. If it is also determined during the second detection that these memory blocks have no faults, then these memory blocks are determined as the final target physical memory; otherwise, new physical memory is continuously screened and the second patrol inspection is performed until the end condition is met. Exemplarily, the end condition includes: 1) until the target physical memory is determined, or 2) the size of the faulty memory in the dynamically allocated memory reaches a preset threshold. For example, the preset threshold is the total number of memory blocks in the dynamically allocated memory. When it is determined through the first patrol inspection and / or the second patrol inspection that all the dynamically allocated memory has faults, the end condition is met. Another example is that the preset threshold is 80% of the total number of memory blocks in the dynamically allocated memory. When it is determined through the first patrol inspection and / or the second patrol inspection that 80% of the memory blocks in the dynamically allocated memory have faults, the end condition is met. If the number (or size) of the faulty memory blocks in the dynamically allocated memory exceeds the preset threshold, the current process is exited and the subsequent step process is not executed, that is, the exchange of the hardware storage resources is not performed; if the number of the faulty memory blocks in the dynamically allocated memory does not exceed the preset threshold, the subsequent exchange of the hardware storage resources is continued (see subsequent step 304). It should be understood that when the number of normal memory blocks in the dynamically allocated memory is small, it may cause the running speed of the application program to slow down. Therefore, through the above design, on the basis of ensuring that the terminal device can still run normally when the memory has faults, the impact on the running performance of the terminal device can be reduced.

[0076] It should be noted that the method of the second patrol inspection can be the same as that of the first patrol inspection. Please refer to the introduction during the first patrol inspection above and will not be elaborated here. Or the method of the second patrol inspection can also be different from that of the first detection. For example, a more reliable or accurate patrol inspection algorithm can be used for the second detection. The embodiments of the present application do not make any limitations in this regard. Any method that can detect whether the memory is damaged is applicable to the embodiments of the present application. In addition, here the second patrol inspection is taken as an example for illustration. Actually, depending on different requirements for the product reliability, the target physical memory can also be determined based on multiple patrol inspections. For example, after performing three or four patrol inspection operations, the target physical memory is finally determined.

[0077] Specifically, when screening the target physical memory in the dynamically allocated memory, it can be randomly screened, or in the order from near to far from the physical position of the first physical memory, or in the order of increasing address. For example, continuing to refer to Figure 2, where the first 1GB of physical memory is statically allocated memory, and the physical memory from the 2GB to the 8GB is dynamically allocated memory. If after the first inspection, it is determined that the memory from the 3GB to the 8GB in the dynamically allocated memory is all normal, that is, there is no faulty memory, then when screening the target physical memory, selection can start from the 3GB, and it is judged whether the physical memory corresponding to the 3GB can be used as the target physical memory. For example, if it is determined after the second detection that the physical memory corresponding to the 3GB has a fault, then it continues to be judged whether the physical memory corresponding to the 4GB can be used as the target physical memory, and so on, until the target physical memory is determined or the detection of the 3GB - 8GB is completed, or the size of the faulty memory detected reaches a preset threshold.

[0078] It should be noted that the above can be illustrated by taking the example of determining the target physical memory after the first inspection of all memory blocks in the dynamically allocated memory. Another implementable way is that if a second inspection is required when determining the target physical memory, it can be that after the first inspection of a memory block and it is determined that the memory block has no fault, a second inspection of this memory block is carried out in a timely manner. For example, as Figure 3 shown, in the serial detection method, after the first inspection of the memory block corresponding to the 2GB and it is determined that it has a fault, then the first inspection of the memory block corresponding to the 3GB is continued. If it is determined that it has no fault, then the second inspection of the memory block of this 3GB is continued. If it is still determined that there is no fault, then it can be determined that the physical memory corresponding to this 3GB is the target physical memory, without waiting for the first inspection of all memory blocks to be completed before performing the second inspection, so as to improve the efficiency of determining the target physical memory. It should be understood that in this way, if the first inspection has not been completed when determining the target physical memory, the first inspection of other memory blocks in the dynamically allocated memory can continue to be completed to determine the faulty memory blocks in the dynamically allocated memory, so as to comprehensively and timely detect the faulty memory. Subsequently, for the determined faulty memory blocks in the dynamically allocated memory, the processor can also generate the fault information of this memory block, and the fault information can include the physical address or logical address of this faulty memory block, etc. The processor can output the fault information of the faulty memory block, and subsequently the internal of the terminal device can process the faulty memory block according to the fault information, which will be specifically introduced below and will not be repeated here.

[0079] Step 303: The processor writes the data stored in the first physical memory into the target physical memory.

[0080] Before performing the hardware storage resource exchange, the processor can copy the data in the first physical memory to the target physical memory to ensure that after the hardware storage resource exchange is performed, data will not be lost and the system running state will not change.

[0081] The data in the first physical memory here can be pre-written or written after the device is powered on and starts up. Additionally, it should be noted that this step 303 is an optional step and not a mandatory one. Therefore, in Figure 2 it is represented by a dashed line.

[0082] It should be noted that if this method is executed during the Xloader startup phase, since for some products, memory is not used during the Xloader startup phase, that is, data is not written to statically allocated memory, therefore, in this scenario, step 303 is an optional step and not a mandatory one.

[0083] Step 304: The processor performs the exchange of hardware storage resources, that is, in the address mapping relationship, the physical address of the first physical memory and the physical address of the target physical memory are exchanged to update the address mapping relationship.

[0084] The address mapping relationship in step 304 can be the address mapping relationship of the memory. Specifically, the address mapping relationship includes the correspondence between the logical address and the physical address of the physical memory on the terminal device. In the embodiments of the present application, the physical memory includes the first physical memory and the second physical memory.

[0085] Please refer to Figure 1A and understand that in an implementable manner, the address mapping relationship of the memory in the embodiments of the present application can be stored on the memory controller 1101. Then the data interaction process between the CPU and the memory can include: The processor sends the logical address of the memory to be accessed to the memory controller 1101, and the memory controller 1101 determines the physical address corresponding to the logical address according to the address mapping relationship, so as to access the memory corresponding to the actual physical address and return the data retrieved from the memory to the processor.

[0086] In the embodiments of the present application, the exchange of hardware storage resources is actually achieved by modifying the address mapping relationship. Please refer to Figure 4 for a schematic diagram comparing the address mapping relationships before and after the exchange of hardware storage resources. Among them, Figure 4 Figure (a) shows the address mapping relationship of the memory before the exchange. From the perspective of the memory controller, the logical memory address of the first 1GB corresponds to the first 1GB of physical memory, the logical memory address of the second 2GB corresponds to the second 2GB of physical memory, the logical memory address of the third 3GB corresponds to the third 3GB of physical memory, and so on. That is, the statically allocated memory is the first 1GB of physical memory, and the physical memory from the second 2GB to the eighth 8GB is dynamically allocated memory.

[0087] Refer to Figure 4In (b), it is the address mapping relationship after the hardware storage resources of the target physical memory (the physical memory of the 3GB) and the first physical memory (the physical memory of the 1GB) are exchanged. After the exchange, from the perspective of the memory controller, the logical memory address of the 1GB corresponds to the physical memory of the 3GB. That is, after the exchange, the statically allocated memory is the physical memory of the 3GB, and the rest is dynamically allocated memory.

[0088] In Figure 4 (a), if there is a fault in the first physical memory, the terminal device cannot run properly. And in Figure 4 (b), since the target physical memory is the memory that is determined to have no fault, when the processor wants to access the statically allocated memory, the actual memory accessed is the target physical memory. In this way, it can be ensured that the operating system, hardware chips and other programs and data during the boot process of the terminal device can be correctly accessed and stored, so that the terminal device can still run normally without replacing the faulty memory.

[0089] The following specifically describes the method of modifying the address mapping relationship.

[0090] In an implementable manner, an address mapping register can also be set in the memory controller 1101, and the address mapping relationship of the memory is configured by the address mapping register. In other words, the exchange of hardware storage resources is actually achieved by changing the address mapping register. The following takes a commonly used 4-channel memory device as an example for illustration. Among them, the 4-channel memory device consists of 4 channels. Each channel is independent of each other and can be accessed in parallel. Each channel has an address mapping register responsible for the mapping of physical addresses and logical addresses. Please refer to Figure 5 , Figure 5 is a comparison schematic diagram of the address mapping registers of a 4-channel memory device before and after the exchange of hardware storage resources. In Figure 5 , assuming that the 4-channel memory device is an 8GB DDR, then each channel corresponds to 2GB. Given that each channel is responsible for address mapping by a 64-bit address mapping register, where a 64-bit address mapping register includes 16 hexadecimal digits (0 - f), and each hexadecimal digit from 0 to f represents 128MB (2GB / 16) of physical memory. That is, each character is used to uniquely identify a 128MB block of physical memory, that is, this character can be the physical address of the memory.

[0091] For example, Figure 5 (a) is a schematic diagram of each address mapping register of the original 4-channel memory device. The value of the address mapping register of each channel is 0x fedcba98 76543210, following the parallel access method of the existing 4-channel memory device. In Figure 5In (a) of , the four-channel numbers (four) "0"s and (four) "1"s represent the first 1GB (128 * 8 = 1024MB) of physical memory; the numbers "2" and "3" in the four channels represent the second 2GB of physical memory; similarly, the numbers "4" and "5" in the four channels represent the third 3GB of physical memory; and so on.

[0092] The sorting of hexadecimal numbers is used to represent logical addresses. For example, as shown in Figure 5 (a) and (b) of , these 16 numbers, in the order of arrangement (for example, Figure 5 the order from left to right in ), every two consecutive numbers represent 1GB of logical memory space. For example, the first two numbers represent the first 1GB of memory space, and the next two consecutive numbers represent the second 2GB of memory space, and so on.

[0093] Given that the statically allocated memory is the first 1GB of logical memory space, and the rest is dynamically allocated memory. Then in Figure 5 (a) of , the first 1GB of logical memory space corresponds to the first 1GB of physical memory. According to the distribution information of the statically allocated memory (the first 1GB of logical memory space), it can be determined that the statically allocated memory (the first physical memory) is the first 1GB of physical memory (the numbers 0 and 1).

[0094] Assume that the target physical memory is the third 3GB of physical memory (the numbers 4 and 5). Refer to Figure 5 (b) of , swap the first physical memory and the target physical memory. Refer to Figure 5 (c) of which shows the schematic diagram of each address mapping register after the hardware storage resources of the first physical memory and the target physical memory are exchanged. That is, in the address mapping relationship, the physical addresses of the target physical memory (the numbers 4 and 5) and the first physical memory (the numbers 0 and 1) are exchanged. After the replacement, the value of each channel's address mapping register is 0x fedcba9876103254. As Figure 5 (c) of shows that after the address mapping relationship is updated, the first 1GB of logical memory space corresponds to the third 3GB of physical memory, that is, the target physical memory. When the processor accesses the first 1GB of logical memory space, it actually accesses the target physical memory, thus achieving the hardware exchange

[0095] Actually, the address mapping register stores binary data. Each number from 0 to f is represented by 4-bit binary data. For example, f is 1111, e is 1110, d is 1101, and so on. This application can modify the address mapping relationship by modifying the bit values on the bits of the address mapping register.

[0096] Step 305, the processor performs a patrol inspection on the first physical memory to determine whether there is a fault in the memory blocks included in the first physical memory. If there is a fault, step 306 is executed; otherwise, step 308 is executed.

[0097] Step 306, the processor keeps the current address mapping relationship unchanged and generates fault information of the first physical memory.

[0098] Keep the address mapping relationship unchanged after the hardware storage resource exchange. For example, in Figure 5 the example shown, keep Figure 5 the address mapping relationship of (b) unchanged.

[0099] Generate fault information of the first physical memory. The fault information may include an identifier of the first physical memory, which is used to indicate that there is a fault in the first physical memory. Exemplarily, the identifier may be the physical address of the first physical memory, or the logical address corresponding to the first physical memory in the current address mapping relationship. For example, in Figure 5 (b) of, the logical address corresponding to the first physical memory (the 3GB memory space), or the index value of the faulty memory.

[0100] The index value here may be an index value compiled in units of memory blocks, or a finer-grained index value. For example, when detecting memory blocks, although the detection can be performed in units of memory blocks, when recording fault information, it can be refined to finer-grained faulty memories. For example, the detection is performed in units of 1GB, but the 1GB can be cut into 32 finer-grained memory blocks of 32MB. If a certain memory block is faulty, the index value of the memory block is recorded. The index value may include but is not limited to numbers, letters, etc. For example, the index value may be 0, 1, 2,..., N set according to the sorting of the memory blocks, where N is a positive integer. Of course, the above is an example with 32MB, and the embodiments of the present application are not limited thereto. For example, it may also be 16MB, 64MB, etc.

[0101] Step 307, the processor transfers the fault information to the kernel, and when the kernel is initialized, isolates the faulty memory.

[0102] The fault information here may include the identifiers of all faulty memories of the dynamically allocated memory (the current first physical memory belongs to the dynamically allocated memory), including the faulty memories determined by the first detection or the Nth detection of the second physical memory in step 302.

[0103] Based on the fault information, the kernel deletes the corresponding relationship of the faulty memory in the current address mapping relationship. For example, taking the first physical memory as an example, the mapping relationship of the first physical memory is deleted in the current address mapping relationship. It should be understood that the mapping relationship of the first physical memory deleted here does not refer to the address mapping register, but refers to deleting the mapping relationship between the logical address and the first physical memory in the address mapping relationship recorded on the processor side, so that the processor cannot call this logical address, and thus no longer calls the first physical memory. Similarly, for the faulty memory detected in the second physical memory, this method can also be used to process it to avoid calling the faulty memory and causing abnormal system operation, and no repeated description will be given here.

[0104] Step 308: Swap the physical address of the first physical memory and the physical address of the target physical memory to restore the address mapping relationship.

[0105] Specifically, in the current address mapping relationship, the physical address of the first physical memory and the physical address of the target physical memory are swapped again to restore the address mapping relationship before the hardware swap is executed. For example, based on the above example, in Figure 5 the current address mapping relationship is Figure 5 the mapping relationship shown in (b) of Figure 5 Swap the first physical address (numbers 0 and 1) and the target physical address (numbers 4 and 5) again to restore the address mapping relationship shown in (a) of

[0106] Optionally, before swapping the physical address of the first physical memory and the physical address of the target physical memory, copy the data in the target physical memory to the first physical memory to ensure that the running state of the system does not change after the swap.

[0107] The above description is based on the example where the first physical memory contains one memory block. When the first physical memory includes multiple memory blocks, in one implementable manner, steps 305 to 308 can be executed with the first physical memory as the granularity, that is, when the first physical memory includes multiple memory blocks, if one of the memory blocks is faulty, step 306 is executed; if all the memory blocks in the first physical memory are not faulty, step 308 is executed. In another implementable manner, steps 305 to 308 can be executed with the memory block as the granularity. For example, when the first physical memory includes multiple memory blocks, for the faulty memory block, when executing step 306 later, the address mapping relationship of this memory block is not modified; for the memory blocks that are not faulty, the address mapping relationship of this memory block can be restored to the state before the hardware storage resource swap is executed by executing step 308.

[0108] It should be noted that steps 305 to 308 are optional steps and do not have to be executed. Therefore, Figure 2 it is represented by a dashed line in

[0109] The above embodiments are introduced with the processor as the execution entity. In different startup phases, the processor may be different. For example, in the Xloader phase, the processor can be an MCU, which is a chip independent of the CPU and is used for boot initialization. Another example is that in the Fastboot phase, the processor can be the CPU. In different phases, the method flow of the embodiments of the present application may be different. For example, in the Xloader phase compared to the Fastboot phase, full-memory space detection can be achieved. However, in the Fastboot phase, since the system is already running in memory, it is impossible to directly detect the full-memory space. Therefore, it is necessary to check the memory bit by bit for damage through the method of hardware storage resource exchange. However, in the Fastboot phase, if the terminal device includes multiple CPUs, multiple CPUs can be used to perform memory detection in parallel. Since the MCU is used in the Xloader phase, the inspection speed is lower than that in the Fastboot phase when inspecting the memory. For the remaining processes, refer to the description of the above embodiments and will not be elaborated here.

[0110] In the above embodiments provided by the present application, in order to implement each function in the method provided by the above embodiments of the present application, the storage system may include a hardware structure and / or a software module, and implement the above functions in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module. Whether a certain function among the above functions is executed in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module depends on the specific application and design constraint conditions of the technical solution.

[0111] Figure 6 shows a schematic structural diagram of a terminal device 600. Among them, the device can be Figure 2 the terminal device in the shown embodiment, or located in the terminal device, and can be used to implement the functions of the terminal device. The terminal device 600 can be a hardware structure or a combination of a hardware structure and a software module.

[0112] As Figure 6 shown, the terminal device 600 includes: a processing unit 601, a storage unit 602; the storage unit 602 includes a first physical memory and a second physical memory; wherein, the first physical memory and the second physical memory are used to store different data;

[0113] The processing unit 601 is configured to detect the startup of the terminal device, determine the first physical memory and the second physical memory; determine the target physical memory, where the target physical memory is the memory in the second physical memory with a capacity equal to that of the first physical memory and without faults; swap the physical address of the first physical memory and the physical address of the target physical memory in the address mapping relationship to obtain an updated address mapping relationship; the address mapping relationship includes the corresponding relationship between different logical addresses and physical addresses.

[0114] In a possible implementation manner, the processing unit 601 is further configured to: before swapping the physical address of the first physical memory and the physical address of the target physical memory in the address mapping relationship, write the data stored on the first physical memory into the target physical memory.

[0115] In a possible implementation manner, the processing unit 601 is further configured to: after updating the address mapping relationship, detect whether the first physical memory has a fault; if it is determined that the first physical memory has a fault, maintain the updated address mapping relationship; if it is determined that the first physical memory has no fault, swap back the physical address of the first physical memory and the physical address of the target physical memory in the updated address mapping relationship.

[0116] In a possible implementation manner, the processing unit 601 is further configured to: after determining that the first physical memory has a fault, generate fault information of the first physical memory, where the fault information is used to indicate that the first physical memory has a fault, and the fault information includes the physical address of the first physical memory, and / or, the logical address corresponding to the physical address of the first physical memory in the updated address mapping relationship.

[0117] In a possible implementation manner, the processing unit 601 is further configured to: according to the fault identifier, delete the corresponding relationship of the first physical memory in the updated address mapping relationship.

[0118] Optionally, the computer-executable instructions in the embodiments of the present application may also be referred to as application program codes, and the embodiments of the present application do not make specific limitations thereto.

[0119] Those of ordinary skill in the art can understand that the various numerical numbers such as the first and the second involved in this application are only for the convenience of description and are not used to limit the scope of the embodiments of this application, nor do they represent the order of precedence. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one" means one or more. At least two means two or more. "At least one", "any one" or their similar expressions refer to any combination of these items, including any combination of single item (s) or plural item (s). For example, at least one (item, kind) of a, b, or c can represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, c can be single or multiple. "Multiple" means two or more, and other quantifiers are similar. In addition, for elements where the singular forms "a", "an", and "the" appear, unless the context clearly stipulates otherwise, they do not mean "one or only one", but mean "one or more than one". For example, "a device" means one or more such devices.

[0120] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are generated in whole or in part. The computer can be a general - purpose computer, a special - purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer - readable storage medium or transmitted from one computer - readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer - readable storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. that includes one or more available media integrated. The available medium can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, solid - state disk (SSD)), etc.

[0121] In the embodiments of the present application, the various illustrative logical units and circuits can be implemented or operate the described functions through a general-purpose processor, a digital signal processor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of the above designs. The general-purpose processor can be a microprocessor. Optionally, the general-purpose processor can also be any conventional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0122] The steps of the methods or algorithms described in the embodiments of the present application can be directly embedded in hardware, software units executed by a processor, or a combination of both. The software units can be stored in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from the storage medium and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and the storage medium can be disposed in an ASIC.

[0123] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one process or multiple processes in a flowchart and / or one block or multiple blocks in a block diagram.

[0124] Although the present application has been described in conjunction with specific features and their embodiments, it is obvious that various modifications and combinations can be made without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application defined by the appended claims, and are considered to cover any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A memory repair method, characterized in that, Including: Before detecting that the terminal device is powered on and the operating system is started, determine the static physical memory and dynamic physical memory included in the terminal device, where the static physical memory is used to store the startup files of the operating system, and the dynamic physical memory and the static physical memory are used to store different data; Perform a fault detection on the dynamic physical memory to determine a target physical memory; where the target physical memory is a memory area in the dynamic physical memory that has the same capacity as the static physical memory and has no faults; The terminal device further includes an address mapping relationship, and the address mapping relationship includes the correspondence between the first logical address space allocated for the static physical memory and the physical address of the static physical memory, and the correspondence between the second logical address space allocated for the dynamic physical memory and the physical address of the dynamic physical memory; In the address mapping relationship, exchange the physical address of the static physical memory and the physical address of the target physical memory to obtain an updated address mapping relationship; Detect whether the static physical memory has a fault; if it is determined that there is a fault in the static physical memory, maintain the updated address mapping relationship; if it is determined that there is no fault in the static physical memory, swap the physical address of the static physical memory and the physical address of the target physical memory in the updated address mapping relationship.

2. The method according to claim 1, characterized in that Before exchanging the physical address of the static physical memory and the physical address of the target physical memory in the address mapping relationship, it further includes: Write the data stored on the static physical memory into the target physical memory.

3. The method according to claim 1 or 2, characterized in that, After determining that there is a fault in the static physical memory, it further includes: Generate fault information of the static physical memory, where the fault information is used to indicate that there is a fault in the static physical memory, and the fault information includes the physical address of the static physical memory, and / or, the logical address corresponding to the physical address of the static physical memory in the updated address mapping relationship.

4. The method according to claim 3, characterized in that, This method further includes: According to the fault information, delete the corresponding relationship of the static physical memory in the updated address mapping relationship.

5. A device, characterized in that, Including a processing unit and a storage unit; the storage unit includes a static physical memory and a dynamic physical memory, where the static physical memory is used to store the startup files of the operating system, and the dynamic physical memory and the static physical memory are used to store different data; the device further includes an address mapping relationship, and the address mapping relationship includes the correspondence between the first logical address space allocated for the static physical memory and the physical address of the static physical memory, and the correspondence between the second logical address space allocated for the dynamic physical memory and the physical address of the dynamic physical memory; The processing unit is configured to, before detecting that the terminal device is powered on and the operating system is started, determine the static physical memory and the dynamic physical memory included in the device; perform a fault detection on the dynamic physical memory to determine a target physical memory, where the target physical memory is a memory area in the dynamic physical memory that has the same capacity as the static physical memory and has no faults; swap the physical address of the static physical memory and the physical address of the target physical memory in the address mapping relationship to obtain an updated address mapping relationship; detect whether there are faults in the static physical memory; if it is determined that there are faults in the static physical memory, maintain the updated address mapping relationship; if it is determined that there are no faults in the static physical memory, swap back the physical address of the static physical memory and the physical address of the target physical memory in the updated address mapping relationship.

6. The device according to claim 5, characterized in that, The processing unit is further configured to: Before swapping the physical address of the static physical memory and the physical address of the target physical memory in the address mapping relationship, write the data stored on the static physical memory into the target physical memory.

7. The device according to claim 5 or 6, characterized in that, The processing unit is further configured to: After determining that there are faults in the static physical memory, generate fault information of the static physical memory, where the fault information is used to indicate that there are faults in the static physical memory, and the fault information includes the physical address of the static physical memory, and / or, the logical address corresponding to the physical address of the static physical memory in the updated address mapping relationship.

8. The device according to claim 7, wherein The processing unit is further configured to: According to the fault information, delete the corresponding relationship of the static physical memory in the updated address mapping relationship.

9. A device, characterized in that, Comprising a processor and a memory; The memory is configured to store computer programs or instructions; The processor is configured to execute the computer programs or instructions in the memory to perform the method according to any one of claims 1-4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a computer program, and when the computer program runs on an electronic device, the electronic device is caused to perform the method according to any one of claims 1-4.

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